Frequency Synthesizer Design Example

High-speed Serial Interface
Lect. 11 – Charge-pump PLL 2
1
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

• 2nd order vs. 3rd order
CPPLL
2
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

2nd-order CPPLL
• VCO Control voltage with RC loop filter
– V = V C + V R
2013-1
Ripples in V during locking process
3
High-Speed Circuits and Systems Lab., Yonsei University

2nd-order CPPLL
• After locking, V should be constant
– But in real PLLs, V fluctuates periodically due to non-ideal effects
– Example: Delay mismatch between UP and DOWN path
4
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

3 rd -order CPPLL
• Additional parallel capacitor
– Reduces fluctuation on the control voltage
[rad]
ϕ ref
PD +
Voltage
[I] Loop [V] [rad]
[rad]
Charge
Controlled
Filter
pump
Oscillator
I CP 1
K VCO
R+
2π
( + 1
sC)∥ 1
s
ϕ vco
=
Main
Divider
1
M
2 ( + 1 )∥ 1
1+
2 ( + 1 )∥ 1
1
5
=> Additional Pole
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

3 rd -order CPPLL
• Phase margin for 3 rd -order CPPLL
Magnitude [dB]
-40dB/dec
-20dB/dec
Phase [deg]
z LF
GB(Gain=0dB)
p LF
-90
without additional pole
Phase margin
-180
6
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

3 rd -order CPPLL
• Design guide for 3 rd -order CPPLL
– For initial damping factor analysis, use 2 nd -order CPPLL
– Rule of thumb: C 1 > 10 x C 2
– For more precise analysis including phase margin,
use behavior simulator: MATLAB, CppSIM
7
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

Input Noise filtering
• Input noise
ϕ noise
PD +
Charge
pump
Loop
Filter
Voltage
Controlled
Oscillator
ϕ out
Main
Divider
– Noise transfer function
=
=
2 ( + 1
)
1+
2 ( + 1
)
1
=
(2 + )/
+2 +
– Low pass filter for input noise
8
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

Optimal PLL Bandwidth
• Clock generation
– With clean reference clock small input noise
High BW desired
• Clock recovery
– Noisy input
Low BW desired
9
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

VCO Noise
• VCO is not ideal
– Oscillation frequency shifts with time Phase noise
• Single Sideband Noise Spectral Density
= 10
10
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

VCO Phase noise
• Phase noise model for VCO
– Leeson's model: single-sideband phase noise in dBc/Hz
= 10 1 2
2
+1
+1
• where f 0 : output frequency,
Q l : loaded Q
f m : offset from the output frequency (Hz)
f c : 1/f corner frequency
F: noise factor of the amplifier
k: Boltzmann's constant
T: absolute temperature in Kelvins
P s : oscillator output power
11
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

Phase noise
• Phase noise model in VCO
L(f)
Noise floor
f c
f o /2Q L
f offset
12
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

VCO Noise filtering
• VCO phase noise
ϕ noise
ϕ ref
PD +
Charge
pump
Loop
Filter
Voltage
Controlled
Oscillator
ϕ out
Main
Divider
– For noises added after VCO
=
=
1
1+
2 ( + 1
)
1
=
+2 +
High pass filter
13
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

Phase noise
• VCO phase noise filtering
L(f)
Filtering
by PLL
VCO phase noise
Filtered phase noise
f offset
– Optimal PLL Bandwidth
14
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

Phase noise
• Higher bandwidth is better for poor VCO
L(f)
Filtering
by PLL
VCO phase noise
Filtered phase noise
f offset
15
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

Noise filtering
• VCO supply noise
V noise
,
ϕ ref
PD +
Charge
pump
Loop
Filter
VCO
ϕ out
Main
Divider
=
=
,
1+
2 ( + 1
)
=
1
,
+2 +
– 1 zero at DC and 2 poles
Band-pass filter
16
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

Noise filtering
• Noise filtering characteristics
• Many trade-offs for PLL design
Lab project!
17
High-Speed Circuits and Systems Lab., Yonsei University
2013-1

Frequency Synthesizer Design Example
• Why do we need frequency synthesizer
Sometimes we want to change the clock speed.
Multi-purpose device.
CPU overclocking
Multi-purpose device
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• How to generate a clock signal with a frequency of more than one
Large power & chip area
Low power & chip area
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Integer-N frequency synthesizer
output clock frequency : N*fref, (N+1)*fref, (N+2)*fref, …
Frequency resolution : fref
Hard to have a high frequency resolution..
Ref.
CK
PFD
Charge Pump
V cont
VCO
%N*fref
%N,%2N,%3N,%4N,..
Counter based
frequency divider
Ratio
select
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Fractional-N frequency synthesizer
output clock frequency : N*fref, (N+0.01)*fref, (N+0.02)*fref, …
Frequency resolution : 0.01*fref
Ref.
CK
PFD
Charge Pump
V cont
VCO
%N*fref
%N,%N+0.01,%N+0.02,..
Impossible to
implement
Ratio
select
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Fractional-N frequency synthesizer
output clock frequency : N*fref, (N+0.01)*fref, (N+0.02)*fref, …
Frequency resolution : 0.01*fref
N=45454545…
N avg =4.5
N=44454445…
N avg =4.25
N=45554555…
N avg =4.75
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Fractional-N frequency synthesizer
Output frequency range : 200MHz ~ 250MHz
Frequency resolution : 12.5MHz
Reference clock frequency : 50MHz
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• PFD (Phase and Frequency detector) design
Ref.CK and VCO.CK, which one is faster
How fast
Ref.CK
VCO.CK
Lead
Lag
Reset
Phase difference = Lead pulse area – Lag pulse area
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Charge pump design
With loop filter, it works as an integrator.
UP & DOWN current should be same.
Vsg
Vsd
1 WP
IUP KP ( Vsg | Vthp |)(1 Vsd
)
2 L
P
Vgs
Vds
1 WN
I
Down
KN ( Vgs Vthn )(1 Vds
)
2 L
N
Can not make them as same!
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Charge pump design
With loop filter, it works as an integrator.
UP & DOWN current should be same.
1. Icp is determined by Mn1, Nbias.
2. According to KCL, Red up, down current must
be same.
3. Pbias is determined to maintain same Red
up,down current, even if Vsd of Mp2 and Vds of
Mn1 is changed.
4. Blue up,down current is copy of Red up,down
current.
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• VCO (voltage controlled oscillator) design
Under all PVT condition, it must meet the target
frequency range. (200MHz ~ 250MHz)
A B C
1 01 01
1
Period = 6*T D (gate delay)
Frequency = 1/period
T D T D T D T D
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• VCO (voltage controlled oscillator) design
Under all PVT condition, it must meet the target
frequency range. (200MHz ~ 250MHz)
A B C
T D control
Fosc
250MHz
T D T D T D T D
200MHz
T D control
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Frequency divider design
4, 4.25, 4.5, 4.75, 5 dividing ratio
4 dividing ratio
0
- Target
Output frequency range : 200MHz ~ 250MHz
Frequency resolution : 12.5MHz
Reference clock frequency : 50MHz
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Frequency divider design
4, 4.25, 4.5, 4.75, 5 dividing ratio
5 dividing ratio
1
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Frequency divider design
4, 4.25, 4.5, 4.75, 5 dividing ratio
4.5 dividing ratio N control implementation
010101
0101…
Delta-sigma modulator
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Frequency divider design
4, 4.25, 4.5, 4.75, 5 dividing ratio
4.5 dividing ratio N control implementation
10
10
-10
100
10
0
1
0 1
0
1
01 0001000100…
11 0111011101…
DSM output is periodic!
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Frequency divider design
4, 4.25, 4.5, 4.75, 5 dividing ratio
Randomizing the division value!
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Chip_layout
PFD,CP,VCO
Counter_based_frequency_divider,
3 rd _order_DSM
Input_frequency=12.5MHz
Output_frequency_range=100MHz~250MHz
Frequency_resolution=0.05MHz
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Measurement setup
Out.CK
Oscilloscope
Crystal
Oscillator
Ref.CK
Frequency
Synthesizer
Out.CK
Spectrum
Analyzer
N_control
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Measurement result
frequency range
Center Frequency : 100 MHz
Center Frequency : 250 MHz
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Measurement result
frequency resolution
Center Frequency : 100 MHz
Fractional Code : 00000000
(12.5MHz X
)
Center Frequency : 100.05 MHz
Fractional Code : 00000001
(12.5MHz X
)
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1

Frequency Synthesizer Design Example
• Measurement result
clock waveform
Frequency : 100 MHz
Frac. code : 00000000
RMS Jitter : 49.68 ps
P2P Jitter : 350 ps
RMS Jitter UI : 0.0049 UI
High-Speed Circuits and Systems Lab.,Yonsei University 2013-1