Gbps급 LVDS I/O에 관한 연구 - 초고속 회로및 시스템 연구실 - 연세대 ...

20/10 Z 0 =50Ω, Td=4ns 20/10 3Voltage (V)2120n 40n 60n 80nTime (sec)

R 0 =50Ω R T =50Ω+/- 5mAZ 0 =50Ω+-

2tutatr

VDDt = 0t = τ n

Output bufferIIn+ChannelInput bufferIn-In-In+100ΩI = 3.5 ~ 4 mA

Data InData out100 ΩHigh-gain amp.Differential amp. outnoutpinpinn

out2poutpoutnout2n outnoutpin pin n

1.3 V1.1 V2UI 2.5 V0.5 V2UI 2.5 V0.5 V2UI

Data InData OutPre-driverMain-driver OutnOutpInpInn+-

iaspinpinninninpoutpoutnbiaspoutpoutnbiasn+ -

2.5 V1 V2UI 1.4 V1 V2UI 1.4 V1 V2UI

LVDS input bufferOpen drain output buffer InpInn

Input bufferOutput buffer Input bufferOpen drainoutput buffer

LVDSOpen drainAgilent 81250PPG/BERTTek 11801C

Agilent 81250PPG/BERTLVDSTek TDS694C

그림 4.3 (a) 1Gbps signal(11001010).그림 4.3 (b) 1.5Gbps signal(11001010).그림 4.3 (c) 2Gbps signal(11001010).0.8ns40m V1 1 0 0 1 0 1 0그림 4.3 (d) 3Gbps signal(11001010).

1 Gbps1.5 Gbps11 00 1 0 1 02 Gbps2.5 Gbps

Transmission Line Structure1.45 16Er = 4.5 (FR4)8단위: mil

4UI 4UI

Ball on Package Stripline in Package Bond Wire1 Ohm1 Ohm0.25 pF0.605 nH Z = 50 Ohm120 ps delay0.25 pF0.605 nH0.01 pF0.01 pF0.605 nH0.605 nHZ = 50 Ohm120 ps delay0.25 pF0.25 pF1 Ohm1 Ohm

Board traceSMADiePackageVddGnd

CABD 100ps/div

SMA63 Ω µ-strip(td=230ps)Package0.6 pF 1.5 nH 1.15 pF 50 Ω 50 ΩPulse GenerationT e s t C irc u it

N1N2 N1N2 N1N2

(a)Package 63 Ω µ -strip SMACable(c)(b) V 2UIV 2UIV2UI