A 40-Gb/s Clock and Data Recovery Circuit in 0.18-um CMOS ...

A 40-Gb/s Clock and Data RecoveryCircuit in 0.18-um CMOS TechnologyJri Lee, Student Member ,IEEE, and Behzad Razavi, Fellow, IEEEIEEE Jorunal of Solid State Circuits, VOL. 38, NO. 12, DECEMBER 2003Dae-hyun Kwon

Contents Clock and Data Recovery circuits– Why quarter-rate?– CDR building blocks Sampler Xor V/I converter VCO– Non-ideal Effect Staggered Outputs Group velocity– Results– Conclusion

Clock and Data Recovery Circuits Why quarter-rate CDR?– The limitation of fabrication 0.18-um fT=50[GHz] Gain X BW =constant, Gain=1 BW=? Fanout one 12 Gb/s220SEC 65nm200Transit Frequency [GHz]180160140120100806040Freescale SOI 130nmTSMC 180nmSEC 130nmTSMC 65nmTSMC 90nm180 160 140 120 100 80 60Technology [nm]

Clock and Data Recovery Circuits Why quarter-rate CDR?– Half –rate CDR Latch X 4 (necessary inductor X 8)– The speed limitation of frequency divider– Lots of FF(Flip-Flop) for making full or half-rate CDR

Clock and Data Recovery Building Blocks Sampler Design– Conventional type of Flip-Flop Voltage headroom speed limitation Data can affect to the output without isolation– Inductive peaking type Bulky

Clock and Data Recovery Building Blocks Modified Flip-FlopConventional typeInductive peakingModified FF– Isolation input and output Clock feed-through– Solving problem of voltage headroom– Without inductor small area– Systematic delay mismatch Buffering with Cherry-Hopper Amp.

Clock and Data Recovery Building Blocks Xor– Conventional type voltage headroom and speed limitation– Other types of Xor is used– Controlling the V GS , Xor can be operated

Clock and Data Recovery Building Blocks V to I converter– Not switch every phase comparison Free from dead-zone Dead-zone cause of Charge pump (Every phase switching for current flowing) Dead-zoneBang-bang PD gainIDataDataClockDead-zoneΔɸupdownCK0 CK45 CK90HighupLowHighdownLow

Clock and Data Recovery Building Blocks Voltage controlled Oscillator– LC oscillator Lower phase noise & larger voltage swing

Clock and Data Recovery Building Blocks Phase Detector– Bang-bang PD– Sampler X 8 + Xor X 8 quarter-rate clock sampling

Non-ideal Effects Staggered OutputsDQ0 45 90 1350 45 90 135No data transitionCK0D QCK45X1X2I1DQVCODCK90QX3I2X1CK135X4X2X3I1I2– Low pass filter extract value of the V/I output– Misalignment creates ripple on the oscillator control Voltage– Kvco = 1GHz / VVcont87.5 ps

Non-ideal Effects Group Velocity– Limited BW of CDR reject jitter– Data duty cycle + Multiphase clock align– Without inductor and compact layout for decreasing length between input Flip-Flop

Results Test set-up & Experimental results– PRBS 2 31 -1– BER = 10 -6– RMS jitter =0.9 [psec]– Power dissipation = 144 [mW]

Results

Conclusion 0.18 – um CMOS technology being used for 40-Gb/s CDR Without inductors, Flip-Flop could sample the 40-Gb/s data with 10GHzclock Decreasing dead-zone by using V to I converter Decreasing phase noise by making VCO with LC, passive components

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