Schematic - Glacier - Lawrence Berkeley National Laboratory

1 

2 

1 

2 

A 

8 

4 

1 

2 

1 

2 

1 

2 

1 

2 

S 

2 

2 

1 

5 

6 

7 

8 

1 

2 

1 

4 

2 

+ 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

B 

C 

D 

E 

Since the sensor u ses about 

60mW, it would be p rudent to 

disable power to it when not 

C75 

1uF X7R C82 

TP60 

needed. 

5Vanalog 

110nF 

Place series resis tors near 

It remains to be seen how 

1 

R279 162K 1% 

remote sources. C apacitors 

0-2.5V span 

-5V 

prudent it is to f loat the 

U26 

2-Pin Header 

U68 

near ADC. 

R338 

ground lead. The 

3.3V 

R3 100K 1% 

1 

10 

alternative may be a P-FET 

BAROMETER 

Ain0 

SC_nCS5 

4 1 2 

R13 150K 1% 

5Vanalog 

2 

SDA 

Out 

3 

BAROMETER R5 10K 1% 

Ain1 

3 

9 

in the Vcc enable d by the 

Gnd 

SC_SCLK 

150K 1% 

R6 10K 1% 

N-FET. 

Imon+5V 

4 

Ain2 SCL 

R4 

R7 10K 1% 

5 

Ain3 

Imon+3.3V 

R339 

100K 1% 

R8 10K 1% 

Ain4 

Imon+2.5V 

6 

R104 10K 1% 

MPXA4115A 100K 1% 

R9 10K 1% 

Imon+1.8V 

7 

Ain5 

R10 10K 1% 

Imon-5V 

8 

Ain6 

DISC-OneSPE R11 10K 1% 

16 

Ain7 

12 

Q7 

R12 10K 1% 

Ain8 Vdd 

3.3V 

4 1.8V 

15 

4 

2N7002 

2.5V 

R142 10K 1% 

14 

Ain9 

R367 20 

-(-5/2.5)-(+3.3+2.5+1. 8)/4 =Vout 

R233 100K 1% 

13 

Ain10 

11 

3.3V 

Vout=Vs(0.009*P-0.09 5)+/-Error 

Ain11-RefGnd 

BAROMETER_ENA 

G 

2 - 0.825 - 0.625 - 0.4 50) = 0.100V 

C14 

P = 10.55555556+(111.111 1111*Vout/Vs) 

Lets just assume tha t if +5 is 

R1 MAX1139EEE 

C9 2.2uF 6.3V Tan 

5V and Baro are scaled by the same 

100nF 

R407 

gone, we're dead. T he 5V CPU 

100K 1% 

factor, so are in the s ame units. 

10K 1% 

supervisory chip input will cause 

The FET switch, Q7, may introduce a 

reboot below about 4.750V. 

(2.500/4096) x count 

TI claims to have a lower power part, little offset due to its on 

C10 C3 C5 C7 C373 C435 

but only accurate to 2 deg C (probably resistance of abou t 5 ohms. 

100nF 100nF 100nF 100nF 100nF 100NF 

within the -25C and abov e range)... 

C2 C4 C6 C8 C434 C1 

100nF 100nF 100nF 100nF 100nF 100nF 

SC_SCLK 

U55 

2 

7 

6 

5 

SCL 

A0 

A1 

A2 

Vdd 

GND 

SDA 

Tout 

DS1631U 

1 

3 

D 

R51 

10K 1% 

3.3V 

Vs 

NC 

NC 

NC 

NC 

NC 

SC_nCS7 

1 2 

Part values ending in "*" should 

not be mounted. These parts are 

for diagnostics or implementation 

of alternate methodologies. 

4.25 mW x 4 + 7.5mW = 24.5 mW 

plus 3.3mW when converting temperature 

+ 6mW x 10V/conv_ef f = 67 mW 

Place series resis tors near 

remote sources. C apacitors 

near ADC. 

R819 10K 1% 

DISC-MultiSPE 

1 

10 

FADC_0_Ref 

SC_nCS6 

R820 10K 1% 

2 

Ain0 SDA 

R821 150K 1% 

SingleLED-BRIGHTNESS-CTL 

3 

Ain1 

9 

R822 10K 1% 

Ain2 SCL 

SC_SCLK 

DAC0_A 

4 

DAC0_B 

R823 150K 1% 

5 

Ain3 

R824 10K 1% 

R825 10K 1% 

DAC0_C 

6 

Ain4 

R826 150K 1% 

Ain5 

Analog_Ref 

7 

R105 10K 1% 

DAC1_A 

R827 10K 1% 

8 

Ain6 

3 R828 150K 1% 

3 

DAC2_B 

16 

Ain7 

12 

3.3V 

R830 10K 1% 

DAC1_C 

15 

Ain8 Vdd 

R831 150K 1% 

Ain9 

Pedestal 

14 

R829 20 

FE_TEST_PULSE_AMPL 

R832 150K 1% 

13 

Ain10 

11 

Ain11-RefGnd 

C437 

MAX1139EEE 

C436 2.2uF 6.3V Tan 

We will need to assig n off page 

100nF 

connectors on the ATWD page for the 

DACx_y input s.... 

R310 

100K 1% 

R313 

100K 1% 

R307 

100K 1% 

R314 

100K 1% 

R309 

100K 1% 

R308 

100K 1% 

C438 C440 C442 C444 C446 C448 

100nF 100nF 100nF 100nF 100nF 100NF 

C439 C441 C443 C445 C447 C449 

100nF 100nF 100nF 100nF 100nF 100nF 

U97 

0-2.5V span 

FADC_0_Ref 

R36 100 

1 2 

C385 

10uF 6.8V Tan 

C386 

100nF 

1 2 

R39 

20 

Note that this FADC is differ ential input. 

Amplifier and shaper stages are DC coupled. The 

'bottom' of the span depends on the setting of 

the ATWD pedestal voltage. I.e., Pedestal for the 

FADC = Pedestal for the ATWD. V+ in must be set 

to ( Vpedestal - (span/2) ) vol ts, or a few mV 

lower. 

100 mW 

U30 

R132 

9 

17 R436 100 1 2 

FLASH_AD_D0 

20 

VIN+ 

D0 

18 R437 100 1 2 

FLASH_AD_D1 

FADC_In 

10 

D1 

19 R438 100 1 2 

VIN- 

D2 

FLASH_AD_D2 

20 R439 100 1 2 

U23 

The (differential input) 4 0 MHz ADC non 

D3 

FLASH_AD_D3 

21 R440 100 1 2 

FLASH_AD_D4 

SC_nCS2 

8 

3 

DISC-MultiSPE 

inverting input, used as th e center-scale 

D4 

22 R441 100 1 2 

FLASH_AD_D5 

C121 

SC_SCLK 

10 

CS OUTA 

2 

D5 

reference. 

25 R442 100 1 2 

100nF 

FLASH_AD_D6 

SC_MOSI 

9 

SCLK FBA 

R14 10K 1% 

D6 

26 R443 100 TP1 

DAC-DO0 

DIN 

1 2 

D7 

FLASH_AD_D7 

1 2 

3.3V 

12 

4 

DAC-UP0 

DISC-OneSPE 

27 R444 100 1 2 

D8 

FLASH_AD_D8 

13 

DOUT OUTB 

5 

2 28 R445 100 1 2 

1 

D9 

FLASH_AD_D9 

14 

UPO FBB 

R15 10K 1% 

2 

C26 

U12 

PDL 

FADC_0_Ref 

SC_CL 

7 

17 

10uF 6.8V Tan 

1 

OTR FLASH_NCO 

7 

CLKx2 

TP* 

CL OUTC 

16 

13 

2 

FBC 

R16 10K 1% 

5V output 

C125 

CLK 

8 

18 

100nF 

C124 

nCLKx2 

OUTD 


14 

C126 

FLASH_AD_STBY 

VR2.5 

15 

19 

100nF 

6 

PDWN 

2 

R262 39K FIN1018K8X 

REFCD FBD 

6 

R17 10K 1% 

REFT MODE 

5 

R405 

REFAB 

5Vanalog 

REFB 

24 

20 

DVdd 

2.5V 

11 

100nF JU28 

DGND 

7 

1 

20 

Open Ckt 4 

AVdd 

12 

B18 

C13 

AGND VDD 

C294 

VREF AVdd 

3.3V 

1 2 3 

23 

100nF 

ADC-REF 

1 2 

SENSE DGnd 

8 

LI0805D121R 

C270 

MAX5250BEAP 

10uF 6.8V Tan 

1 2 

AGnd 

11 

R45 Ra* 

1 2 

AGnd 

C15 

Open Ckt 

JU27 

C29 C127 

100nF 

AD9215BRU-65 

Jumper 

100nF 100nF 

OSCON_6SC6R8M 

Components w hose 

C295 

value ends i n "*" 

100nF 

are not to be 

mounted. 

NC 

NC 

15 

16 

R46 

Strap SENSE to Gnd fo r 2V Span. 

Open Ckt Ra* 

Strap SENSE to VREF fo r 1V span. 

U28 

Strap SENSE to Voltage Div ider for span 

=1.0(1+Ra/ Rb). 

SC_nCS3 

8 

3 

CS OUTA 


SC_SCLK 

10 

2 

SC_MOSI 

9 

SCLK FBA 

R22 10K 0.1% 

TP2 

DAC-DO1 12 

DIN 

4 

DAC-UP1 

DOUT OUTB 

Clamp 

13 

5 

1 

14 

UPO FBB 

R23 10K 0.1% 

TP* 

SC_CL 

7 

PDL 

17 

CL OUTC 

FL_REF 

U24 

16 

FBC 

R24 10K 0.1% 

5Vanalog 

3 

18 

VCC 

OUTD 

DAC_Out_1 

1 

15 

19 

C12 

OUT 

REFCD FBD 

6 

R25 10K 0.1% 

REFAB 

+ 

C16 

100nF* 

100nF 

11 

5Vanalog 

1 DGND 

1 

20 

1 

AGND VDD 

GND 

TLE2425ID 

C451 

OSCON_6SC6R8M 

MAX5250BEAP 

10 bit DAC 

C17 

100nF 

R26 10K 1% 

R18 10K 1% 

R19 10K 1% 

R20 10K 1% 

R21 10K 1% 

R27 10K 0.1%* 

R28 10K 0.1%* 

R29 10K 0.1%* 

Title 

Digital Optical Module AD/DA 

Size Document Number Rev 

C 1.1 

A 

B 

C 

D 

Friday, May 16, 2003 

Date: Sheet of 4 15 

E

1 

2 

1 

2 

5 

3 

5 

4 

3 

2 

7 

8 

4 

1 

A 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

5 

2 

1 

2 

1 

2 

1 

2 

1 

2 

5 

2 

1 

1 

2 

2 

1 

2 

1 

2 

1 

2 

1 

2 

5 

2 

5 

2 

1 

2 

1 

2 

2 

1 

2 

1 

2 

1 

2 

1 

6 

1 

6 

1 

2 

7 

4 

5 

2 

1 

2 

1 

2 

1 

2 

5 

2 

S 

S 

1 

2 

1 

2 

1 

2 

5 

2 

5 

2 

B 

C 

D 

E 

Nov 25, '0 2 GTP 

R278 20 

Name chang e to 

1 2 

5Vanalog 

eliminate 

C83 

naming con flict 

1 2 

Caution: The comparato rs are 5V 

Vref1 2 

C151 

parts that cannot be op erated from 

Per criterion established July 2002 (gtp&drn) the design goal for the 

10uF 6.8V Tan 

3.3V. Care must be take n to protect 

IceCube DOM is 200 PE = 1V into the ATWD dic tated by PMT saturation 

33pF NPO 

1 2 

TP70 the driven 3.3 V part. 

5Vanalog 

behavior. Namely, the PMT NEVER delivers mor e than about 2V, and is 

C154 

1 

2-Pin Header 

linear to about 1V into a 50 ohm load (100 oh m || back-termination). 

R348 

100nF 

U1 

R35 2400 51 

R351 2.2K 

R40 

DISC-MultiSPE 

1 2 

U2 MAX9013EUA 

2 

C409 

MSPE_Q 

5Vanalog 

1 2 

2 

7 

1 2 

R390 10uF 6.8V Tan 

C323 

R38 C355 + C371 

MSPE_QBar 3 

4 R352 51 

MSPE_QBar 

MultiSPE-C 

1 21 2 

10 10uF 6.8V Tan 

1 2 

3 

5Vanalog 

5 

- 

8 

47pF NPO 

1100nF 

5 

1 2 

Open Ckt 

Latch 5 

10 

Vref 

MSPE_Q 

5 

6 

7 R322 2 151 

MultiSPE 

C410 

1 2 

12 

1 2 

R75 

1 2 

C20 

Q8 

100 

SPE_QBar 

R353 51 

5Vanalog 

2 1 

10uF 6.8V Tan 

2N7002 

11 

10 

OneSPE-C 

Locate these amplifiers --> 

100nF 

R47 

C25 

1 2 

G 

MultiSPE-nL 

15 

51 U43 100nF 

R32 20 

C21 

TP71 

close to the PMT signal 

U66 

1 2 

R349 

U3 

1 

3 

100nF 

2-Pin Header 2 1 

SPE_Q 14 

13 R354 51 

+ 

input. 

Transmission line 

SPE_Q 

OneSPE 

3 

1 1 2 

2 

7 

R371 

+ 

1 

1 2 4 

+ R355 10K 1% 

- 

FSTD3125M 

1 2 4 

51 

Vref 

3 - 

8 SPE_QBar 

2.2K 

R391 

- 

1 2 

R42 

AD8014RT 

100nF 

Latch 5 

169 

AD8014RT 

205 

C281 R41 243 1% 

C372 

47pF NPO 

R43 

R392 

Vref 

2 1 

R44 2.2K 

499 1% 

2 1 

1 2 MAX9013EUA 

Q14 

C282 

R48 x2.5 

2N7002 

Vref x4 499 1% C358 100nF 

499 1% 

C356 

DISC-OneSPE 

G 

OneSPE-nL 

10uF 6.8V Tan 

100nF 

1*1.3*5 + 2*1.3*5 + 6.8*10 + 2* 1.15*10+2*1.1*5+ 

C412 

Vref 

2 1 

3*0.4*10=13 4 mW 

C411 100nF 

R370 

opamp comparator, 1135 80 14 8014 8005 

10uF 6.8V Tan 

10K 1% 

B19 10uF 6.8V Tan 

5Vanalog 

1 2 

AD advertises that these (400 MHz) amplifiers re cover in 60 ns. At 5 mW 

C32 

per stage, they give slightly less performance than an HA1135 at 1/10th 

the current. Saturation is not a big issue for t he (latching) comparator 

LI0805D121R 1 2 

R49 

Calibration input 

input, since latch recovery is contr olled by the FPGA 

C30 

2 1 

5Vanalog 

100nF 

test-point. Drive 

2 1 

4 Analog_Ref 

1 2 

10 

4 

with 5V square 

If we have power to burn, once all revisions are taken into account, the 

R57 100 

Clamp 

C31 100nF 

TP67 

850 MHz bandwidth HA1135 may prove to be a bett er choice as comparator 

X5.33 

C33 10uF 6.8V Tan 

wave to generate 

R52 

input amplifier, as one stage should hav e less delay than 2. 

33 U44 

X3 1 2 

1 2 3 

R53 

U48 

1 

fixed amplitude 

+ 

6 

1 2 

3 

R325 20 

2-Pin Header 

The comparators exhibit less trigger delay i f driven by a positive 

+ 

test pulses. 

2 

- 

1 

1 2 

ATWD_IN_0 

signal, so the second gain stage inverts. The first one buffers 

HFA1135IB 

20 

4 

to minimize load on the PMT signal. 

B30 X 5.36 R58 

- 

AD8014RT 

LI0805D121R 

-5V X 3.0 optimized for 200 MHz BW 


If test pulser, U52, injects too much power supply noise, it will 

100 

-5V 

C35 100nF Also try observi ng the 

FE_TEST_PULSE 

have to go, in favor of something that is quieter. 

1 2 

5Vanalog 

performance of this 

R56 

stage with 499 a nd 249 

R59 

C34 100nF 

R62 10 

A 

C 

C122 

1 2 

1 2 

C38 10uF 6.8V Tan ohm feedback div ider. 

1nF NPO 

C408 

499 

2 1 See if it is st ill as 

JP6 R106 

C37 

100nF 

CR1 

41.2 1% 

stable. It shoul d have 

C360 

2 1 

R61 

1 

more bandwi dth. 

1 2 

BAS70-04 

2 

16.8 

R107 

C42 

10uF 6.8V Tan 

1K 1% 

R326 1K 1% 3.3V 

Vref 100nF 

R60 

2 Pin Header 33 

1 2 

C285 10uF 6.8V Tan 

180 1% optimized for 200 MHz BW 100nF C361 

R100 20 

Vref 

R108 R99 

SamTec SMM-102 -01-S-D 

3.3V 

Open Ckt 10K 1%* 

Thru-Hole 2x2 2m m socket 

C220 

mates with S amTec 

100nF 

U52 

TW-02-01-S-D-120-08 0 2x2 2mm 

3 R408 C265 

break-away h eader 

JU12 

3 

5Vanalog 

1 2 

NC7SZ126M52 

4 

1 2 TP69 

In Out 

1 

2-Pin Header 

Open Ckt 

C227 100nF 

499 

60 ns coax d elay 

TP68 

C228 10uF 6.8V Tan 

R815 5pF NPO 

JU11 

1 

assembly 

2-Pin Header 

X4.33 1 2 

Open Ckt 

R273 

U41 

TP65 

2.7K* 

1 2 

R323 20 

1 

3 

2-Pin Header 

R324 

+ 

1 

1 2 

ATWD_IN_1 

300 

1 2 4 

- 

JP5 

JP19 

AD8014RT 

5Vanalog 

300 1% X4.33 

JP4 

1 2 

2 1 

C359 

C229 100nF 

A 

C 

3 4 

4 3 

C341 

1 2 

1 

Dly_Line_In 

SMM-102-01-S-D 

SMM-102-01-S-D 

Dly_Line_Out 

Vref 100nF 

Vref 

CR3 

-5V 

C383 10uF 6.8V Tan 

C230 

BAS70-04 

5Vanalog 

1 2 

2 1 

OE 

1 2 

1 2 

1 2 

CA 

1 2 

1 2 

1 2 

1 2 

10uF 6.8V Tan 

1 2 

Coax_SMB_75_ohm 

C 

A 

C40 

10uF 6.8V Tan 

EAP 2709-1511-00 1 or the 

1 2 

R186 

2709-7511-001 PCB or 

BAS70-04 

JU40 

R54 

100nF 

1 2 

equivalent 

CR8 

1 2 

Test pulse inj ection 

1 2 

63.4 1% 

TP72 

1K 1% 

eapconnectors.co m, e.g. 

C36 

Vref 

(if it doesn't work, 

Open Ckt R30 

U53 

1 

2-Pin Header 

AMP 414244-1 

JP13 

1 2 remove transf ormer, Inject- 

1 2 

3 

R101 10 

+ 

and use jum per.) 

1 1 2 

2 

100nF 

31.6 1% 

ATWD_IN_2 

4 

1 

- 

C41 

AD8014RT 

1 2 

If the PMT delivers 3V into a 50 ohm load, then change 

HEADER 2 

the divider resistors to R30=31.6 a nd R54=63.4 Leave 

2 -5V 

10uF 6.8V Tan 

2 

the gain of the amplifier unchanged. The design goal 

R64 

C384 C39 

is to have the PMT saturation volta ge within the span 

10K 1% 

of the ATWD. 

10uF 6.8V Tan 100nF 

0.47uF Y5V 

Samsung CL31F4 74ZBNC 

(0.12) 

R34 

1 2 1 2 

3.3V 

1K 1% R31 1K 1% 

C58 

C54 

100nF Vref 

10uF 6.8V Tan 

1 2 

10uF 6.8V Tan 

5 8 

D 

D 

1 2 

CA 

8 16 

CA 

C46 10uF 6.8V Tan 

C44 100nF 

C45 100nF 

R65 10 1 2 

5Vanalog 

1 2 

1 2 

5Vanalog 

1 2 

5Vanalog 

C43 100nF 

C47 10uF 6.8V Tan 

C48 10uF 6.8V Tan 

1 2 

1 2 

1 2 

TP66 The shaped signal path design was from 

R69 511 

U54 

U15 

U16 

1 

2-Pin Header 

Harold Yaver of the Engineering Department. 

1 2 3 

R70 205 R71 205 

3 

R72 205 R73 205 

3 

R74 

+ 

+ 

+ 

1 1 2 1 2 

1 

1 2 1 2 

1 

1 2 

-Modifications added to insure stable offset behavior, 

FADC_In 

4 

4 

4 

and to offset the output to match the input range of 

5Vanalog 

- 

AD8005RT 

- 

AD8005RT 

- 

AD8005RT Jumper 

-5V 

C52 

C53 

the ADC 

C49 100nF 

C50 100nF 

C51 100nF 

MAX4166ESA 

1 2 

1 2 

1 2 Jan 19, 2003 Correct reversed polarized 

1 1 

-5V -5V 

U74 

Distribute capacitors around th e island of Vref. 

R76 

C24 

C56 

C27 

capacitors on analog stages. gtp 

3 

R264 24.9 1% If some are not needed, they ma y not be mounted. 

C23 100nF 

10 C55 

100nF 

2 1 

100nF 

C57 

PEDESTAL 

+ 

6 

1 2 

Vref 

1 2 

2 1 

1 2 

1 2 

2 1 

2 

10uF 6.8V Tan 

- 

C283 

+ + + + 

R79 10uF 6.8V Tan 

R81 1.5K 1% R82 

R83 1.5K 1% R84 10uF 6.8V Tan 

C284 

Vref 1 2 2 1 1 2 

2 1 1 2 1 2 

2 1 1 2 1 2 

3K 1% 

3K 1% 

Lawrence Berkeley National Laboratory 

GTP/JL/DRN/HY 

C422 C428 

1.5K 1% R80 2.49K 1% 

C60 33pF NPO 

C22 

C61 33pF NPO 

Title 

C272 C420 C273 C419 C418 10uF 6.8V Tan 10uF 6.8V Tan C18 

C19 

1 2 

1 2 

Digital Optical Module Analog Front End 

R265 10K 1% 

100nF 100nF 100nF 100nF 100nF 

10uF 6.8V Tan 

10uF 6.8V Tan 

10uF 6.8V Tan 

1 2 

C423 C421 


10uF 6.8V Tan 10uF 6.8V Tan 

C 0 

to... Martin Keste l 3/30/03 

Date: Friday, May 16, 2003 

Sheet 5 of 15 

A 

B 

C 

D 

E 

SDW N 

Vcc 

Vee 

100nF 

1 2 

10uF 6.8V Tan 

Vref 

110pF NPO 

1 2 

Vref 

110pF NPO 

1 2

A 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

U82B 

B 

COINC_UP_A 

R393 100 C413 22pF NPO 

1 2 COINC_UP_ABAR 

C 

D 

EB_nCS0 

R3944.7K 

E 

IO_Bank 12 

EB_nCS1 

R3954.7K 

not includi ng 

R396 100 C414 22pF NPO 

multi_purpo se 

COINC_UP_B 

1 2 COINC_UP_BBAR 

EB_nCS2 

R3974.7K 

pins 

EB_nCS3 

R3984.7K 

K2 

R86 100 C415 22pF NPO 

IO-*LVDSOUT05n 

FL_TRIGGER 

COINC_DOWN_A 1 2 COINC_DOWN_ABAR 

3.3V 

L1 

U82F 

Flash Chip Select routed throu gh PLD 

U82K 

IO-*LVDSOUT06p L2 

COM_DB6 

U82H 


COM_DB7 

R400 100 C416 22pF NPO 

IO_Bank_8 

IO_Bank_2 

B5 

M1 

COINC_DOWN_B 1 2 COINC_DOWN_BBAR 

EB_nCS0 

EB_nCS[0..3] 

SD_CLK 

IO_Bank_6 

K17 

SD_CLK G7 

SD_nCLK 

IO-*LVDSOUT07p 

M2 

COM_DB8 

EBI_CS0 

H20 EB_nCS1 

SD_CLK_N 


COM_DB9 

FA[0..17] 

FA0 

EBI_CS1 

SD RAM 

F7 

EB_nCS2 

SD_CLKE 

AB26 

L21 

Extension 

J19 

SD_CLKE 

FA1 AB25 IO-*RXINCLK1p_LVDSIO-L21 

EBI_CS2 

Bus 

R1 

M22 

G20 EB_nCS3 

D6 SD_CS_N1 

SD_CS_N[0..1] 


COM_DB10 

Bus 

R2 

IO-*RXINCLK1n_LVDSIO-M22 

M24 

EBI_CS3 

SD_CS_N1 

E7 SD_CS_N0 


COM_DB11 

FA2 Y26 

IO-M24 M21 

FL_ATTN 

EBA[0..24] Interface 

C22 

SD_CS_N0 J9 

T1 

FA3 Y25 

IO-*LVDSIN01 IO-M21 

L20 

FL_TCK 

EBI_OE_N 

E21 

EB_nOE 

SD_RAS_N 

F8 

nRAS 


COM_DB12 

FL_TDO 

EB_nWE 

nCAS 

T2 

IO-*LVDSIN01A IO-L20 

M19 

EBI_WE_N 

SD_CAS_N 

A5 

See HW Ref Manu al 


COM_DB13 

FA4 AA26 

IO-M19 L19 

FL_TDI 

EBA0 F20 

D22 

SD_WE_N nWE 

FL_Trigger_bar 

FA5 

FL_TMS 

U1 

AA25 

IO-*LVDSIN02p IO-L19 

N25 

EBA1 C21 

EBI_A0 

EBI_BE0 

K18 

F12 

IO-*LVDSOUT10p U2 

IO-*LVDSIN02n IO-N25 M23 

FL_PRE_TRIG 

EBA2 E20 EBI_A1 

EBI_BE1 

SD_DQS0 H11 


COM_TX_SLEEP 

U82A 

FA6 W26 

IO-M23 

N23 

FL_Trigger 

EBA3 H18 

EBI_A2 

C17 EBD0 EBD[0..15] 

SD_DQS1 

J10 

4 FA7 

FL_Trigger_bar 

W1 

W25 

IO-*LVDSIN03p IO-N23 

K24 

EBA4 G19 

EBI_A3 

EBI_DQ0 

G16 EBD1 

SD_DQS2 

K10 

4 

IO-*LVDSOUT11p W2 

FPGA_D0 

E4 

IO-*LVDSIN03n IO-K24 L24 

nFOE 

EBA5 J18 EBI_A4 

EBI_DQ1 D17 EBD2 

SD_DQS3 


FPGA_D1 

A_nB 

FA8 

nFWE 

EBA6 

EBD3 

SD_DQM0 

SD_DQM[0..3] 

I/O Bank 13 

IO-E4_R1 

E3 

V26 

IO-L24 

K22 

J17 

EBI_A5 

EBI_DQ2 

E16 

H12 

V1 

IO-E3_R1 

FPGA_DA 

FA9 V25 IO-*LVDSIN04p IO-K22 L23 

nFLB 

EBA7 G18 EBI_A6 

EBI_DQ3 J15 EBD4 

SD_DQM1 


FPGA_D2 


F3 

SD_DQM0 G11 

V2 

IO-F3_R3 

FPGA_CE 

IO-*LVDSIN04n IO-L23 

L22 

nFUB 

EBA8 D20 

EBI_A7 

EBI_DQ4 

F16 EBD5 

SD_DQM2 


FPGA_D3 

multi-purpo se 

F4 

SD_DQM1 

F9 

IO-F4_R1 

HVD_IN 

FA10 

nFCS3 

EBA9 

EBD6 

A[0..14] 

U26 

IO-L22 

F19 

EBI_A8 

EBI_DQ5 

SD_DQM3 

pins 

G3 

K19 

G15 

SD_DQM2 

C6 

Y1 

IO-G3_R2 G4 

HVD_TxENA 

FA11 U25 IO-*LVDSIN05p IO-K19 K21 

nFCS2 

EBA10 H17 EBI_A9 

EBI_DQ6 F15 EBD7 

SD_DQM3 


FPGA_D4 

HVD_RxENA 

nFCS1 

EBA11 

EBD8 

A0 

D0 

D[0..31] 

Y2 

IO-G4_R2 

H3R399 100 

IO-*LVDSIN05n IO-K21 

K20 

E19 

EBI_A10 

EBI_DQ7 

H15 

K9 

J13 


FPGA_D5 

IO-H3_R2 H4 

HVD_Rx 

FA12 T26 

IO-K20 

nFCS0 

EBA12 C20 EBI_A11 

EBI_DQ8 E15 EBD9 

A1 C5 SD_A0 

SD_DQ0 H13 D1 

AA1 

SingleLED-TRIGGER 

IO-H4_R2 

H5 

COM_AD_OTR 

FA13 T25 

IO-*LVDSIN06p 

EBA13 D19 

EBI_A12 

EBI_DQ9 

J14 EBD10 

A2 E6 

SD_A1 

SD_DQ1 

F13 D2 


COM_AD_D9 

AA2 

IO-H5_R1 

J3 

IO-*LVDSIN06n 

EBA14 F18 

EBI_A13 

EBI_DQ10 

E14 EBD11 

A3 G6 

SD_A2 

SD_DQ2 

G13 D3 


FPGA_D6 

IO-J3_R3 J4 

COM_AD_D8 

FA14 R26 


EBI_DQ11 K14 EBD12 

A4 K8 SD_A3 

SD_DQ3 E13 D4 

IO-J4_R3 

COM_AD_D7 

J5 

FA15 R25 

IO-*LVDSIN07p 

EBA16 G17 

EBI_A15 

EBI_DQ12 

G14 EBD13 

A5 A4 

SD_A4 

SD_DQ4 

D13 D5 

AC2 

IO-J5_R2 K3 

COM_AD_D6 

IO-*LVDSIN07n 

EBA17 K15 EBI_A16 

EBI_DQ13 F14 EBD14 

A6 B4 SD_A5 

SD_DQ5 C13 D6 


FPGA_D7 

IO-K3_R4 

K4 

COM_AD_D5 

FA16 M26 

3.3V 

EBA18 D18 

EBI_A17 

EBI_DQ14 

H14 EBD15 

A7 F5 

SD_A6 

SD_DQ6 

B12 D7 

COM_AD_D4 

AB1 

IO-K4_R3 

K5 

FA17 M25 

IO-*LVDSIN08p 

EBA19 E18 

EBI_A18 

EBI_DQ15 

A8 D5 

SD_A7 

SD_DQ7 

E12 D8 

IO-*LVDSOUT16p AB2 

COINCIDENCE_OUT_UP 

IO-K5_R4 L3 

COM_AD_D3 

IO-*LVDSIN08n 

EBA20 H16 EBI_A19 

D21 

A9 G5 SD_A8 

SD_DQ8 G12 D9 


COINCIDENCE_OUT_DOWN 

IO-L3_R5 

COM_AD_D2 

FD[0..15] FD0 

EB_CLK 

L4 

L26 

EBA21 F17 

EBI_A20 

EBI_CLK 

A10 K11 

SD_A9 

SD_DQ9 

J12 D10 

IO-L4_R4 L5 

COM_AD_D1 

FD1 L25 IO-*LVDSIN09p 


H19 

A11 E5 SD_A10 SD_DQ10 A12 D11 

IO-L5_R4 

COM_AD_D0 

IO-*LVDSIN09n 

EBA23 J16 

EBI_A22 INT_EXT_PIN_N INT_EXT_PIN_N 

A12 

D12 

EPXA1F672I2 

R5 

H8 

SD_A11 SD_DQ11 

C12 

IO-R5_R5 

R6 

FD2 K26 

EBA24 E17 

EBI_A23 

K16 

A13 J8 


B11 D13 

IO-R6_R6 

FPGA_RW 

FD3 K25 IO-*LVDSIN10p 

EBI_A24See Errata- > EBI_ACK 

A14 F6 SD_A13 SD_DQ13 K13 D14 

IO-*LVDSIN10n 


A11 D15 

FD4 J26 

SD_DQ15 A9 D16 

EPXA1F672I2 

FD5 

EPXA1F672I2 

J25 

IO-*LVDSIN11p 

SD_DQ16 

H10 D17 

This is a 2.5V I/O ban k... 

IO-*LVDSIN11n 

SD_DQ17 

B9 D18 

FD6H26 

SD_DQ18 C9 D19 

DO NOT CHANGE PIN 

FD7H25 

IO-*LVDSIN12p 

SD_DQ19 

E9 D20 

IO-*LVDSIN12n 

SD_DQ20 

ASSIGNMENTS OF AC8, AD7, 

K12 D21 

FD8 

AD8, AE7. These pin 

G26 

SD_DQ21 

D9 D22 

FD9 

D23 

assignments chosen to 

G25 

IO-*LVDSIN13p 

SD_DQ22 

G9 

IO-*LVDSIN13n 

SD_DQ23 D8 D24 

optimize speed. gtp 

FD10F26 

SD_DQ24 

H9 D25 

9/11/02 

FD11F25 

IO-*LVDSIN14p 

SD_DQ25 A7 D26 

IO-*LVDSIN14n 

SD_DQ26 

B7 D27 

FD12E26 

SD_DQ27 

E8 D28 

FD13E25 

IO-*LVDSIN15p 

SD_DQ28 G8 D29 

U82C 

IO-*LVDSIN15n 

SD_DQ29 

C7 D30 

FD14D26 

SD_DQ30 D7 D31 

FD15D25 

IO-*LVDSIN16p 

SD_DQ31 

ATWD1VDD-SUP 

If the FE_TEST_PULSE --> 

AB8 IO_Bank 11 

IO-*LVDSIN16n 

G10 

ATWDTrigger_0 

line injec ts 

AC8 IO-AB8_C1 

OneSPE 

R369 10K 1% 

nc-SD_DQ_ECC0 J11 

AD7 

IO-AC8_C2 

nc-SD_DQ_ECC1 

objectionable noise into 

ATWDTrigger_1 

ATWD0VDD-SUP 

EPXA1F672I2 

C10 

AE7 IO-AD7_C2 

nc-SD_DQ_ECC2 C11 

the front, then per haps 

MultiSPE 

AD8 

IO-AE7_C3 

U62E 

R368 10K 1% 

nc-SD_DQ_ECC3 

E10 

MultiSPE-nL 

that could be mitig ated 

AC9 

IO-AD8_C3 

AD22 

R2BUS0 

nc-SD_DQ_ECC4 

D11 

COINC_DOWN_ALATCH 

by making it dr ive 

AE9 IO-AC9_C4 

IO-AD22 AC22 

nc-SD_DQ_ECC5 F11 

COINC_DOWN_ABAR 

FE_TEST_PULSE 

AA10 

IO-AE9_C4 

IO-AC22 

AC25 

nc-SD_DQ_ECC6 

differentiall y. 

COINC_DOWN_A 

AD9 IO-AA10_C5 

IO-AC25 AC26 

F10 

COINC_DOWN_BLATCH 

AB9 

IO-AD9_C5 

IO-AC26 

AB19 

nc-SD_DQS_ECC 

D10 

3 COINC_DOWN_BBAR 

OneSPE-nL 

AC10 

IO-AB9_C6 

IO-AB19 

AB20 

R2BUS2 

nc-SD_DQM_ECC 

3 

COINC_DOWN_B 

AF9 IO-AC10_C6 

R2BUS1 

COINC_UP_ALATCH 

IO_Bank 9 

IO-AB20 AB21 

D12 

AB10 

IO-AF9_C7 

IO-AB21 

COINC_UP_A 


AB22 

DDR_VS0 

E11 

AE10 IO-AB10_C7 

IO-AB22 

COINC_UP_ABAR 

multi_purpo se 

AB23 

DDR_VS1 C8 

AA11 

IO-AE10_C8 

IO-AB23 

AB24 

DDR_VS2 

COINC_UP_BLATCH 

pins 

AF10 

IO-AA11_C8 

IO-AB24 

AA19 

COINC_UP_BBAR 

AD10 IO-AF10_C9 

IO-AA19 AA20 

COINC_UP_B 

R2BUS3 

AB11 

IO-AD10_C9 

IO-AA20 

EPXA1F672I2 

AA21 

R2BUS4 

FLASH_AD_D0 

AC11 IO-AB11_C10 

IO-AA21 AA22 

FLASH_AD_D1 

AD11 

IO-AC11_C10 

IO-AA22 

AA23 

FLASH_AD_D2 

AF11 

IO-AD11_C11 

IO-AA23 

AA24 

FLASH_AD_D3 

AA12 IO-AF11_C11 

IO-AA24 Y19 

FLASH_AD_D4 

AB12 

IO-AA12_C12 

IO-Y19 

Y20 

R2BUS5 

FLASH_AD_D5 

AE11 IO-AB12_C12 

IO-Y20 Y21 

R2BUS6 

FLASH_AD_D6 

AC12 

IO-AE11_C13 

IO-Y21 

Y22 

R2BUS7 

FLASH_AD_D7 

AD12 

IO-AC12_C13 

IO-Y22 

Y23 

FLASH_AD_D8 

AC13 IO-AD12_C14 

IO-Y23 Y24 

FLASH_AD_D9 

IO-Y24 

R2BUS[0..7] 

AB14 

IO-AC13_C14 

W20 

FLASH_NCO 

AA13 IO-AB14_C15 

IO-W20 W21 

U82L 

AB13 

IO-AA13_C15 

IO-W21 

W22 

FLASH_AD_STBY 

IO-AB13_C16 

IO-W22 

W23 FE_PULSER0n 

A2 

A3 

IO-W23 W24 FE_PULSER0p 

A8 GND 

VccInt A24 

1.8V 

IO-W24 

EPXA1F672I2 

V19 

A10 

GND 

VccInt 

B3 

R363 

IO-V19 V20 

A14 GND 

VccInt B8 

IO-V20 

V21 

PLD_FPGA_nOE 

A17 

GND 

VccInt 

B10 

10K 

IO-V21 

PLD_FPGA_nWE 

V22 

A19 

GND 

VccInt 

B17 

IO-V22 V23 FE_PULSER1p 

PLD_FPGA_BUSY 

A25 GND 

VccInt B19 

IO-V23 FE_PULSER1n 

PLD_FPGA[0..7] 

V24 

B1 

GND 

VccInt 

B24 

IO-V24 U20 

PLD_FPGA7 

B2 GND 

VccInt C1 

IO-U20 

U21 

PLD_FPGA6 

B6 

GND 

VccInt 

C2 

IO-U21 

U22 FE_PULSER2p 

PLD_FPGA5 Feb 6, 2003 g tp 

B13 

GND 

VccInt 

C4 

IO-U22 U23 FE_PULSER2n 

PLD_FPGA4 

IO-U23 

Feb 20, 2003 gtp net name 

B21 GND 

VccInt C23 

T20 

PLD_FPGA3 

IO-T20 

changes 

B25 

GND 

VccInt 

C25 

C91 

T21 

PLD_FPGA2 

B26 GND 

VccInt C26 OSCON 6SC47M 

IO-T21 

T22 FE_PULSER3p 

PLD_FPGA1 

C3 

GND 

VccInt 

D3 From Sanyo Vi deo C92 

IO-T22 

T24 FE_PULSER3n 

PLD_FPGA0 

C24 

GND 

VccInt 

D24 

OSCON 6SC47M 

IO-T24 R20 

D4 GND 

VccInt L13 

IO-R20 

D23 

GND 

VccInt 

L15 

L11 GND 

VccInt M13 

EPXA1F672I2 

L16 

GND 

VccInt 

M16 

M12 

GND 

VccInt 

N2 

M15 GND 

gtp 

VccInt N10 

M17 

GND 

LBNL 

VccInt 

N12 

C93 C94 

N1 GND 

9/3/2002 

VccInt P15 

470pF NPO 470pF NPO 

N4 

GND 

VccInt 

P18 

N11 

GND 

VccInt 

P24 

N13 GND 

VccInt P25 

MEMVIO 

N14 

GND 

VccInt 

R10 

10K 1% 10K 1% 10K 1% 10K 1% 10K 1% 10K 1% 10K 1% 

N16 GND 

VccInt R11 

R207 R204 R201 R198 R195 R192 R189 

N18 

GND 

VccInt 

R14 

C95 C101 

2 10K 1% 10K 1% 10K 1% 10K 1% 10K 1% 

Connect all the NO_CONNECT pins 

N26 

GND 

VccInt 

T12 

100nF 100nF 

2 

R206 R203 R200 R194 R191 

to an obstacle on a plane that 

P1 GND 

VccInt T17 

3.3V 

R263 Open Ckt 

10K 1% 10K 1% 10K 1% 10K 1% 10K 1% 10K 1% 

WILL NOT map to a gerber l ayer. 

P2 

GND 

VccInt 

U9 

R205 R202 R196 R193 R190 R187 

P3 GND 

VccInt U14 

This insures that all the pins 

R258 Open CktI/O bank used by SDR AM. 

3.3V 

P13 

GND 

VccInt 

U16 

2.5V 

Support optional I/O volta ges. 

are connected to pads, s o are 

P14 

GND 

VccInt 

AC3 

R259 Jumper 

accessable . 

P16 GND 

VccInt AC24 

1.8V 

P23 

GND 

VccInt 

AD1 

P26 GND 

VccInt AD2 C417 C379 C380 

U82D 

NC 

R12 

GND 

VccInt 

AD4 470pF NPO100nF 

OSCON 6SC47M 

IO_Bank 10 

R15 

GND 

VccInt 

AD23 

3.3V 

not includi ng AA14 

U82M 

R17 GND 

VccInt AD25 

IO-AA14 

TriggerComplete_0 

multi_purpo se W14 

R18051 

R19924.9 

T11 

GND 

VccInt 

AD26 

IO-W14 W15 

OutputEnable_0 

FE_PULSER0p 

D1 

T13 GND 

VccInt AE3 

pins IO-W15 

Y15 

ATWD0_D0 CounterClock_0 

D2 

NC 

U3 

T14 

GND 

VccInt 

AE8 

IO-Y15 

AC14 

R115 

E1 

NC NC 

U4 

T16 

GND 

VccInt 

AE19 

C345 C346 

IO-AC14 V15 

ATWD0_D1 

ShiftClock_0 

12.4 

E2 NC NC U5 

T18 GND 

VccInt AE24 C315 100nF OSCON 6SC47M 

IO-V15 

AD15 

R21651 

R275 24.9 

F1 

NC NC 

U6 

U10 

GND 

VccInt 

AF3 470pF NPO 

IO-AD15 AC15 

ATWD0_D2 

RampSet_0 

FE_PULSER1p 

F2 NC NC U7 

U12 GND 

VccInt AF24 

3.3V 

IO-AC15 

AB15 

G1 

NC NC 

U19 

U17 

GND 

VccInt 

IO-AB15 

ATWD0_D3 

ChannelSelectMSB_0 

AA15 

R117 

G2 

NC NC 

V4 

V9 

GND 

B14 

IO-AA15 AF16 

H1 NC NC V6 

V18 I/O bank used by 

IO-AF16 

ATWD0_D4 

CHannelSelectLSB_0 

12.4 

GND 

VccIO_2 P11 

B8 

AE16 

R21851 

R248 24.9 

H2 

NC NC 

V11 

W8 

GND 

SDRAM memor y. 

VccIO_2 

U15 

C347 C348 C349 

1812K121R Bead 

IO-AE16 AD16 

FE_PULSER2p 

H6 NC NC V12 

W19 GND 

VccIO_2 

470pF NPO100nF 

OSCON 6SC47M 

VddC0 

1 2 

IO-AD16 

AB16 

ATWD0_D5 ReadWrite_0 

H7 

NC NC 

V13 

AC4 

GND 

P17 

1.8V 

IO-AB16 

3.3V 

AC16 

R181 

J1 

NC NC 

V14 

AC23 

GND 

VccIO_3 

R18 

IO-AC16 AA16 

ATWD0_D6 

AnalogReset_0 

12.4 

J2 NC NC W3 

AD3 GND 

VccIO_3 U13 

IO-AA16 

V16 

R18251 

R255 24.9 

R18424.9 T8 

J6 

NC NC 

W4 

AD24 

GND 

VccIO_3 

IO-V16 W16 

ATWD0_D7 

DigitalReset_0 

FE_PULSER3p 

J7 NC NC W9 

AE1 GND 

A6 

C357 

IO-W16 

Mini-Circuit s 

C155 

C369 

Y16 

4 

3 

K1 

NC NC 

W10 

AE2 

GND 

I/O bank used b y 

VccIO_6 

L12 

C370 C299 C300 

10nF 100nF C368 2.2uF 6.3V Tan B11 

IO-Y16 

ATWD0_D8 

DigitalSet_0 

VRef 

AF17 

K6 

NC NC 

W11 

AE6 

GND 

Flash memory . 

VccIO_6 

L14 

470pF 100nF NPO OSCON 6SC47M 

10uF 6.8V Tan 


IO-AF17 AE17 

R249 R185 

K7 NC NC W12 

AE13 GND 

VccIO_6 

VddC1 

1 2 

IO-AE17 

ATWD0_D9 

3.3V 

AD17 

R18851 

R254 24.9 24.9 1 

K23 

NC NC 

W13 

AE21 

GND 

A13 

IO-AD17 AC17 

FE_PULSER3n 

6 

1 

L6 NC NC Y7 

AE25 GND 

VccIO_7 M14 

IO-AC17 

W17 


Inject- 

L7 

NC NC 

Y8 

AE26 

GND 

VccIO_7 

N17 

IO-W17 


ATWD0_D[0..9] 

AB17 

R447 Mini-Circuits TCM1-1 

L8 

NC NC 

Y9 

AF2 

GND 

VccIO_7 

IO-AB17 AA17 

ATWD1_D0 

CounterClock_1 

12.4 

TP8 

L9 NC NC Y10 

AF8 GND 

A21 

C204 C207 C301 

C158 C302 

C304 

IO-AA17 

Y17 

R16251 

R252 24.9 

L10 

NC NC 

Y11 

AF14 

GND 

VccIO_8 

L17 

470pF 100nF NPO OSCON 6SC47M 

10nF 100nF C303 2.2uF 6.3V Tan B12 

IO-Y17 AF18 

ATWD1_D1 

ShiftClock_1 

FE_PULSER2n 

1 

L18 NC NC Y12 

AF19 GND 

VccIO_8 N15 

10uF 6.8V Tan 


IO-AF18 

AE18 

M6 

NC NC 

Y13 

AF25 

GND 

VccIO_8 

N24 

3.3V 

VddC2 

1 2 

IO-AE18 

ATWD1_D2 

RampSet_1 

AB18 

R163 

TP* 

M7 

NC NC 

Y14 

GND 

VccIO_9 

IO-AB18 Y18 

IO-Y18 

ATWD1_D3 


12.4 

M8 NC NC AA4 

R16 

AD18 

R16451 

R251 24.9 

M9 

NC NC 

AA5 

VccIO_9 

U18 

IO-AD18 AD19 

FE_PULSER1n 

M10 NC NC AA6 

VccIO_9 

C213 C214 C305 

IO-AD19 

AC20 

ATWD1_D4 CHannelSelectLSB_1 

M18 

NC NC 

AA7 

T15 

470pF NPO 100nF OSCON 6SC47M 

C159 C307 

C309 

IO-AC20 

AD20 

R165 

N6 

NC NC 

AA8 

VccIO_10 

V17 

10nF 100nF C308 2.2uF 6.3V Tan B14 

IO-AD20 AC19 

ATWD1_D5 

ReadWrite_1 

3.3V 

3.3V 

12.4 

N7 NC NC AA9 

VccIO_10 AE14 

10uF 6.8V Tan 


IO-AC19 

AC18 

R16651 

R250 24.9 

N8 

NC NC 

AB5 

VccIO_10 

AF21 

VddC3 

1 2 

IO-AC18 AE22 

ATWD1_D6 

AnalogReset_1 

FE_PULSER0n 

N9 NC NC AB6 

VccIO_10 

IO-AE22 

W18 

N19 

NC NC 

AB7 

R13 

1 IO-W18 

ATWD1_D7 


AA18 

P4 

NC NC 

AC1 

VccIO_11 

U11 C223 C310 

C226 C297 

1 

IO-AA18 AE23 

P7 NC NC AC5 

VccIO_11 V10 

IO-AE23 

ATWD1_D8 

DigitalSet_1 

C217 100nF OSCON 6SC47M C224 100nF OSCON 6SC47M 

AD21 

P8 

NC NC 

AC6 

VccIO_11 

AF13470pF NPO 

470pF NPO 

C206 C311 

C298 

IO-AD21 AE20 

ATWD1_D9 

P9 NC NC AC7 

VccIO_11 

10nF 100nF C312 2.2uF 6.3V Tan 

IO-AE20 

AF20 

P10 

NC NC 

AD5 

T10 

10uF 6.8V Tan 

B17 

IO-AF20 

3.3V 

AC21 

P19 

NC NC 

AD6 

VccIO_12 

AF6 


IO-AC21 

ATWD1_D[0..9] 

P22 NC NC AE4 

VccIO_12 M11 

VddC4 

1 2 

R3 

NC NC 

AE5 

VccIO_13 

N3 

R4 NC NC AF4 

VccIO_13 P12 

EPXA1F672I2 

R19 

NC NC 

AF5 

VccIO_13 

C237 C263 C296 

T3 

NC NC 

AF7 

R8 

R9 


OSCON 6SC47M 

T4 NC NC AF22 

GND_CKLK4 

Vcc_CKLK4 

VddC0 

C280 C286 

C129 

T5 

NC NC 

AF23 

T9 

T8 VddC1 

JU5 

10nF 100nF C128 2.2uF 6.3V Tan 

T19 NC NC 

GND_CKLK2 

Vcc_CKLK2 

1 2 

10uF 6.8V Tan 

T23 

NC 

F23 

E23 VddC2 

3.3V 1 2 2.5V 

NC 

GND_CKLK6 

Vcc_CKLK6 

4/11/03 GT P Jumper 

F22 

E22 VddC3 

GND_CKLK5 

Vcc_CKLK5 

JU6 

V8 

U8 VddC4 C424 C425 

1 2 Title 

EPXA1F672I2 

GND_CKOUT2 VccCKOUT2 


C426 

1 2 3.3V 

 

EPXA1F672I2 

OSCON 6SC47M Open Ckt 


D 

 

IO_Bank_12 

R209 10K 1% 

R21 0 10K 1% 

R211 10K 1% 

R21 2 10K 1% 

R213 10K 1% 

R277 10K 1% 

R21 4 10K 1% 

R219 10K 1% 

A 

B 

C 

D 

E 


Date: Sheet of 6 15

5 

4 

3 

2 

1 

2 

2 

A 

1 

2 

1 

6 

1 

2 

1 

2 

1 

6 

D 

S 

7 

6 

5 

4 

3 

2 

1 

1 

2 

7 

8 

4 

7 

8 

4 

Vee 

Vee 

1 

2 

8 

5 

2 

1 

2 

1 

2 

D 

S 

7 

6 

5 

4 

3 

2 

1 

1 

2 

EAP 2009-1511-000 or 

2009-1511-000 or equiva lent 

eapconnectors.c om 

Coax_50_ohm_SMB 

AMP 413990-1 or 

AMP 413990-2 or 

1 ICE_LED_PULSER 

AMP 415590-1 o r 

JP16 

AMP 413990-3 or 

AMP 414612-1 or 

AMP 414612- 2 

AMP 414612-1 or 

R362 1K 1% 

C319 

FL_REF 

R177 

100nF 

100 

R178 

C320 

Open Ckt 100nF 

ICE-LED-IN 

Multiplexed Calibration In puts: 

Toyocom Osc for capture rate calibration, and absolute ph ase reference 

CLK Osc 40 MHz system clock 

Flash current waveform for LED on DOM M ain Board 

Flash current waveform for LED daught er board 

Local Coincidence Signal from upper neighbor 

Local Coincidence Signal from lower neighbor 

Communications Signal for relative phase of time ticks 

Communications Signal for relative phase of time ticks 

For best integrity of calibration, mount the two 

MAX4141 chips such that the 20 ohm resisto r outputs 

abut, and pin 11 to the 20 ohm resistor is the same 

length, and leads to inputs are kept short s ince they 

are high frequency carri ers. 

B 

C 

ATWD_IN_2 

5Vanalog 

PMT_LED_PULSER 

ATWD_IN_2 

ATWD_IN_1 

C317 

5Vanalog 

ATWD_IN_1 

ATWD_IN_0 

R123 

PMT-LED-IN 

ATWD_IN_0 

R274 

100nF 

24.9K 1% 

100 

AnalogRef1 

R168 C318 

AnalogRef0 

C266 

4 1K 1% 100nF 

C267 

100nF 

C205 

4 

50mW/15mW 

100nF 

C63 

C288 

5Vanalog 

R401 

100nF 

R124 

100nF 

10uF 6.8V Tan 

4.7K 

U14 

R33 

U17 

4.7K 

U13 

U95A 

Jumper 

1 

8 

C287 

5Vanalog 

TOYOCOM_OSC 

SEL_A0 

ATWD_B_TC 


3 

IN1 A0 

Vdd 

8 

46 

9 

R327 

8 

46 

ATWD_A_TC 2 

54 

9 

Vdd 

Vdd 

45 

10uF 6.8V Tan 

CLKx2 

PMT-LED-IN 5 IN2 A1 10 

SEL_A1 

ATWD_A_TC 



ATWD_B_CC 

ATWD_B0 

ICE-LED-IN 

MUX_EN0 

Jumper 

9 Vdd 

Vdd 45 

10 Trigger Complete 

OE 44 

U95B 

R2 

7 

IN3 EN 

ATWD_A_CC 10 

Trigger Complete 

OE 

44 

ATWD_A0 

ATWD_A0 3 

53 ATWD0_D0 

11 

Counter Clock 

D0 

43 

ATWD_B1 

ATWD_A1 

ShiftClock_1 

100 R257 

IN4 

13 

12 Shift Clock 

For KAMLAN D 

D1 

Vdd 

11 Counter Clock 

D0 43 

42 

ATWD_B2 

ATWD_B_TC 15 

41 

Open Ckt 

OUT 

12 

R365 

ShiftClock_0 

12 

Shift Clock 

For KAMLAN D 

D1 

42 

ATWD_A2 

ATWD_A1 4 

52 ATWD0_D1 

RampSet_1 

13 

Ramp Reset 

D2 

41 

ATWD_B3 


In- 

RampSet_0 

ATWD_A3 


1K 1% 

13 

Ramp Reset 

D2 

41 

14 

Chnl MSB 

D3 

40 

ATWD_B4 

ATWD_B0 16 

40 ATWD1_D0 

nCLKx2 

2 

11 


ATWD_A4 

ATWD_A2 

ATWD0_D2 


MUX_EN0 

B1 LI0805D121R 

14 Chnl MSB 

D3 40 

5 

51 

15 Chnl LSB 

D4 39 


ATWD_B5 

Locate R2 a t 

ATWD_A5 

ReadWrite_1 

C382 

4 

GND1 SD 

14 

15 

Chnl LSB 

D4 

39 

16 

Read-Write 

D5 

38 

ATWD_B6 

ATWD_B1 18 

39 ATWD1_D1 

GND2 Vcc 

ReadWrite_0 

farthest end of 

6 

16 Read-Write 

D5 38 

ATWD_A6 

ATWD_A3 6 

50 ATWD0_D3 

AnalogReset_1 

17 Analog Reset 

D6 37 

ATWD_B7 

Open Ckt 

Vee 

AnalogReset_0 

transmissio n 

C64 

17 

Analog Reset 

D6 

37 

ATWD_A7 


18 

Digital ReSet 

D7 

36 

ATWD_B8 

ATWD_B2 20 

37 ATWD1_D2 


ATWD_A8 

ATWD_A4 

ATWD0_D4 

DigitalSet_1 

ATWD_B_TR 

line. 

AD8174AR 

100nF 

18 

Digital ReSet 

D7 

36 

7 

48 

19 

Digital Set 

D8 

35 

ATWD_B9 

DigitalSet_0 

R257,C382 used to 

ATWD_A_TR 19 Digital Set 

D8 35 

ATWD_A9 

20 Trigger Input 

D9 34 

ATWD_B3 21 

36 ATWD1_D3 

match U17-3 to m ake 

C65 B2 

20 

Trigger Input 

D9 

34 

ATWD_A5 9 

47 ATWD0_D5 

Vdd 

Vdd 

CLKx2 and nCLK x2 

100nF LI0805D121R 

Vdd 

Vdd 

ATWD_B4 22 

35 ATWD1_D4 

ATWD_A6 10 

46 ATWD0_D6 

C268 

ATWD 

symmetric. 

5Vanalog 

C269 

ATWD 

100nF 

B43 

ATWD_B5 23 

34 ATWD1_D5 

-5V 

100nF 

B50 

R197 

ATWD_A7 11 

45 ATWD0_D7 

LI0805D121R 

C208 C209 

LI0805D121R 

C66 C67 

10K 1% 

100nF 100nF 

ATWD_B6 24 

33 ATWD1_D6 

50mW/15mW 

ATWD_A8 

ATWD0_D8 

5Vanalog 

100nF 100nF 

12 

44 

C210 

U19 

C68 

5Vanalog 

100nF 

R208 ATWD_B7 25 

32 ATWD1_D7 

5Vanalog 

1 

8 

100nF 

ATWD_A_TR 

13 

43 

10K 1% 

R335 C381 LOCAL_COINCIDENCE_Upper 

3 IN1 A0 9 

SEL_A0 

ATWDTrigger_0 

ATWD_B8 

ATWD1_D8 

LOCAL_COINCIDENCE_Lower 

SEL_A1 

R329 

R217 R118 

C211 

C212 

26 

31 

1 2 

5 

IN2 A1 

10 

Jumper 

R111 R113 

C69 

C70 

TP61 ATWD_A9 14 

42 ATWD0_D9 

1K 1% 1K 1% 

100nF 

100nF 

COM_IN 

PULSE 7 IN3 EN MUX_EN1 

1K 1% 1K 1% 

100nF 

100nF 

ATWD_B_TR 

27 

30 

249 

IN4 

13 

5.1mW 

ATWD0_D[0..9] 

ATWDTrigger_1 

100nF 

OUT 

12 

1 

__ 

R366 

Q9 Q10 

TP62 ATWD_B9 

ATWD1_D9 

In- 

OE 56 

28 

29 

1K 1% 

Q11 Q12 

MAX4166ESA 

2-Pin Header 

1 

ATWD1_D[0..9] 

2 

11 

B3 LI0805D121R 

1 

FSTD16211MTD 

MUX_EN1 

5Vanalog 

R260 

4 GND1 SD 14 

MMBTH81 

MMBTH81 

1 

__ 

GND2 Vcc 

6 

5Vanalog 

OE 

55 

MMBTH81 

MMBTH81 

U75 

2-Pin Header 

100 1% 

Vee 

C71 Can use 2SB7 09 

3 

R266 

R330 R169 R170 

R331 

FSTD16211MTD 

R256 300 

100nF as current 

R88 R89 

+ 

AD8174AR 

R332 

R333 

6 

AnalogRef0 

1M 100K 1% 100K 1% 1M 

C72 B4 mirror to 

1M 100K 1% 100K 1% 1M 

2 

100nF LI0805D121R 

- 

reduce packa ge 

C215 

C73 

24.9 1% 

100nF 

C377 

count. 

100nF 

C289 

DAC1_A 

100nF 

-5V 

100nF 

C216 

C74 

4.25mW 

Q15 100nF* 

DAC0_A 

4.25mW 

Q16 100nF* 

BCX70K 

2N7002 

2N7002 

U63 

Q3 

G 

U20 

ATWD1VDD-SUP 

Q1 

G 

R267 10K 1% 

8 

3 

8 

3 

BCX70K 

ATWD0VDD-SUP 

SC_nCS1 

10 CS OUTA 2 

SC_nCS0 

Analog_Ref 

SC_SCLK 

R171 

10 

CS OUTA 

2 

9 

SCLK FBA 

1.56K 1% 

SC_SCLK 

9 SCLK FBA 

TP4 

SC_MOSI 

DAC2_B 

R90 1.56K 1% 

DAC-DO4 12 DIN 

4 

TP5 

SC_MOSI 

DAC-DO3 12 

DIN 

4 

DAC0_B 

5.1mW 

DAC-UP4 13 

DOUT OUTB 

5 

3 DAC-UP3 13 

DOUT OUTB 

5 

1 

14 

UPO FBB 

R172 10K 1% 

Q4 

3 

DAC1_C 

1mW 

1 

14 UPO FBB 

R91 10K 1% 

7 PDL 

17 

BCX70K 

DAC0_C 

Q2 

MAX4166ESA 

SC_CL 

7 

PDL 

17 

BCX70K 

TP* 

CL OUTC 

16 

SC_CL 

5Vanalog 

5Vanalog 

TP* 

CL OUTC 16 

FBC 

U21 

FBC 

U76 

18 

PEDESTAL 

3 

TLE2425ID 

18 

3 

R268 

15 

OUTD 

19 

VCC 1 

15 

OUTD 19 

+ 6 

AnalogRef1 

6 REFCD FBD 

R173 10K 1% 

OUT 

6 

REFCD FBD 

R92 10K 1% 

2 

REFAB 

5Vanalog 

REFAB 

5Vanalog 

- 

+ 

11 

11 

24.9 1% 

1 

DGND 

20 

1 

DGND 

20 

C290 

AGND VDD 

AGND VDD 

100nF 

C218 

MAX525BEAP 

C76 

C433 C77 C78 

MAX525BEAP 

100nF 

100nF 

OSCON_6SC6R8M 100nF 100nF 

GND 

5Vana log 

3 2 

3 2 

52 

51 

50 

49 

48 

47 

Gnd 

NC 

In0 

AnaRef0 

AnaRef1 

In1 

AnaRef2 

In2 

In3 

AnaRef3 

Ana Ref 

Op-Amp Ref 

Gnd 

Gnd 

Trigger Bias 

A-Gnd 

A-Gnd 

A-Vdd 

A-Vdd 

Op-Amp Bias Current 

Comparator Bias Current 

Ramp Top Voltage 

Ramp Bias Current 

A-Vdd 

A-Gnd 

Gnd 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

33 

SDWN 

Vcc 

SDWN 

Vcc 

17 

49 

3 2 

3 2 

D 

52 

51 

50 

49 

48 

47 

Gnd 

NC 

In0 

AnaRef0 

In1 

AnaRef1 

AnaRef2 

In2 

In3 

AnaRef3 

Ana Ref 

Op-Amp Ref 

Gnd 

Gnd 

Trigger Bias 

A-Gnd 

A-Gnd 

A-Vdd 

A-Vdd 

Op-Amp Bias Current 

Comparator Bias Current 

Ramp Top Voltage 

Ramp Bias Current 

A-Vdd 

A-Gnd 

Gnd 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

33 

19 

17 

38 

E 

C79 R93 R94 

100nF 10K 1% 10K 1% 

R95 

2K 1% 

R269 10K 1% 

C219 R174 R175 

100nF 10K 1% 10K 1% 

R176 

2K 1% 

VR2.5 

JU25 

1 2 

1 2 

If noise is bei ng 

coupled throug h, 

then put a 

resistor or be ad 

here. 

Jumper 

Power Budg et 

50 + 50 + 1 + 5.1 + 5.1 + 4.25 + 4.25 + 2xATWD mW 

R147 

2K 1% 

5Vanalog 

R276 

R2BUS7 

1 

16 

C278 

100nF 

Could be a lower power part with greater 

delay, like max998, if it is ne cessary 

to save 6mW . 

5Vanalog 

C173 

10nF 

5Vanalog 

C171 

10nF 

R2BUS6 

R2BUS5 

R2BUS4 4 

13 

VR2.5 

C277 

U71 MAX9013EUA 

U72 MAX9013EUA 

-5V 

100nF 

2 

7 ATWD_A_CC 

2 

7 ATWD_B_CC 

CounterClock_0 + CounterClock_1 + R2BUS3 5 

12 

3 

Use a low volta ge 

2 

- 

8 

3 

Latch 5 

- 

8 

Latch 5 

2 

driving standard. Wi red 

R2BUS2 6 

11 to a low voltage I /O 

bank of the FP GA 

1.65V 

C130 

10nF 

C131 

10nF 

R402 

5.11K 1% 

R403 

10K 1% 

R2BUS[0..7] 

R2BUS1 

R2BUS0 

2 

3 

7 

8 9 

R2R-LADDER-16 

15 

14 

10 

U57 

3 

4 

+ 

- 

1 

AD8005RT 

R148 

20 

R150 

Open Ckt 

C279 

1 2 

100nF 

PULSE 

R149 

24.9K 1% 

CTS 766-16-7-10 1-D 

SEMICONWEL L 

2964-2966 Sco tt 

Blvd. Santa Cla ra, 

CA 95054 

Tel:(408)986-8 026 

Fax:(408)-850-19 11, 

or equivalen t. 

1 1 

Title 

Digital Optical Module ATWD 


D 

 

A 

B 

C 

D 

E 


Date: Sheet of 7 15

A 

7 

8 

4 

1 

2 

2 

1 

8 

1 

7 

1 

2 

5 

2 

2 

1 

A 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

5 

8 

1 

2 

1 

4 

B 

C 

D 

E 

14 

Vdd 

Vdd 

Vee 

Vee 

GND 

Vdd 

COM-5 

5Vanalog 

COMM-REF 

R110 

R112 

Jan 30, 2003 

March 28, 2003 gtp , Better Maybe this part should have 22.5m m LS if EF2225-ND 

TP55 

SRF 9MHz 0.7 o hm Rmax 

to suppress comm on mode or 27.5mm LS if E2225-ND (preferred) 

L5 

B5 

Cable+ 

1 2 

C455 

1 

DCIN1 

470nF 250v 

2-Pin Header 

PM54-101K 

1 2 

LI0805D121R 

D3 

+ C81 

C80 

220uF/160V 

TP56 

DL4004MS 

P4664-ND 

L15 

470nF 250v 

B6 

Cable- 

1 2 

1 

DCIN2 

JU9 JU8 

2-Pin Header 

PM54-101K 

C89 

4 5Vanalog 

1 12 

2 

1 2 1 2 3.3V 

4 

2.2uF 160V 

LI0805D121R 

Open Ckt Jumper 

1 2 

5Vanalog 

RS-485 Driver (9 mA * Vdd) 

C431 

TB4 

TB3 

100nF 

B9 

U94 

1 1 

LI0805D121R 

1 

1 

COM+5 

board_to_wire board_to_wire 

HVD_Rx 

1 

R 

C84 

C236 

TP57 

T1 

HVD_RxENA 

2 

1 

10 

100nF 

100nF 

HVD_TxENA 

3 

RE 

R140 

TB2 

TB1 

1 

DE 

Open Ckt 

6 

LINE_A 

2-Pin Header U47 

A 

1 1 

LINE_A 

HVD_IN 

4 

1 

1 

3 

8 

6 

D 

R161 

board_to_wire board_to_wire 

IN+ 

Open Ckt 

13 

7 

LINE_B 

2 

9 

LINE_B 

2 

OUT-SNS 

B 

IN- 

11 

TP58 R215 

OUT 

3 

348 

RG- 

SN65HVD11 

9 

4 

7 

5 

OUT-REF 

Pulse Eng B2105 

1 

Gain=(1+(1.4K /Rg)) 

RG+ 

2-Pin Header 4 

C86 

R410 R409 

SHDN 

470nF 250v 

COM+5 

MAX4145ESD 

Differential line receiver 

P4664-ND 

Jumper Open Ckt 

(110mW) 

Differential line receiver 

C235 

(135mW) 

Either an active ^ 

COM-5 

C378 

100nF 

solution or a 

100nF 

C90 

COM+5 

Feb 19 2003 gtp, I f routing 

transformer will 

100nF 

U96 

works out, then U80 not 

2 1 

3.3V 

B10 

JU24 

needed (sugge sted) 

3 be used, but not 

LI0805D121R 

COM_ADC_REF 1 2 LINE_A 1 v+ 8 

3 

1 2 

both... 

LINE_B 2 

R119 

R301 

7 

C87 

Jumper 

COM_IN 

COM_CLK 

CLK 

7 

PLD_CLK 

2 

470nF 250v 

-5V 

JU23 

3 

6 

8 

P4664-ND 

COMM-REF 

nCLK 

1 2 

4 v- 5 

20* 

U80 

1 2 

Open Ckt 

FIN1018K8X 

Open Ckt 

AD830 

B33 

499 

2K 1% 

LI0805D121R C350 

Line Receiver witho ut any CMR 

(4 mW) 

100nF 

Route COM I N for 

U22 

minimal noise 

3 

T4 

4 

3 AD8005RT* 

coupling from 100 mW 

+ 

1 

R50 

TP59 

digital sou rces. 

2 5 

4 

20* 

- C352 

COM_IN 

This part is located very nea r the FPGA. If 

1 6 

1 

possible return the ground f or this part to 

B35 

R109 

the communications inp ut circuit! 

T1-6-KK81 

-5V 

100nF 

20 

2-Pin Header 

U25 

R346 

9 

17 

R426 100 

LI0805D121R 1K 1% R342 

COM_AD_D0 

100 1% 

VIN+ 

D0 

5Vanalog 

18 

R427 100 

COM_AD_D1 

R906 

A 

C 

3.3V 

C98 10 

D1 

19 

R428 100 

COMM-REF 

COM_AD_D2 

C351 

R341 

VIN- 

D2 

20 

R429 100 

COM_AD_D3 

100nF 

205 

R343 

100 1% 

D3 

21 

R430 100 

CR9 

100pF 

D4 

R431 100 

COM_AD_D4 

22 

249 1% 

D5 

COM_AD_D5 

U77 

25 

R432 100 

COM_AD_D6 

5.2 mW 

BAS70-04 

D6 

26 

R433 100 

R271 

COM_AD_D7 

MAX4166ESA 

D7 

27 

R434 100 

COM_AD_D8 

COM_ADC_REF 

3 

C353 

C104 

D8 

28 

R435 100 

+ 

COM_AD_D9 

COMM-REF 

R311 100 

2 6 

100nF 

10uF 6.8V Tan 

D9 

COM_AD_OTR 

2 

5.11K 1% 2 

C96 

1 

- 

10uF 6.8V Tan 

OTR 

13 

COM_CLK 

CLK 

R270 

10K 0.1% 

SDW N 

Vcc 

Vee 

1 2 

R120 

10K 0.1% 

C115 

1uF X7R 

JP103 2 Pin Header 

R97 

Open Ckt 

R98 

If R125 is present then C104 

and R112 must be there as 

well. If R125 is no t present, 

then C104 may be rep laced with 

a short AND R112 sho uld not be 

present. 

5Vanalog 

JP7 2 Pin Header 

CA 

C444 

100nF 

COM_ADC_REF 

R66 

Ra* 

R67 

Rb* 

Strap SENSE to Gnd fo r 2V Span. 

Strap SENSE to VREF fo r 1V span. 

Strap SENSE to Voltage Div ider for span 

=1.0(1+Ra/ Rb). 

With some switch fets a nd FPGA (or 

PLD) control lines, one could 

cause the span to be controlled 

remotely. 1V span may be good for 

digitizing time ticks . If pins 

are lacking, then, perh aps 1V span 

should be chosen t o reduce 

constraints on th e input 

amplifier. 

Essential to cl ock the 

communications ADC at 

power up in or der to 

communicate a t all. 

R87 200 

B39 

B15 

B16 up to 190 mW 

Replace CR7, CR8 

Jumper 

Open Ckt 

LI0805D121R LI0805D121R 

with 5V zener d iodes 

U27 

Feb 3, 200 3 gtp 

1 

T5 

6 

LINE_A 

R121 

22 

14 

DELETE THESE 

Jumper 

IOUTA 

21 

DB0 

13 

PARTS and OFF 

R818 

R816 

C102 

IOUTB 

2 5 

DB1 

12 

PAGE CONNE CTORS 

133 

10pF NPO* 

DB2 

11 

1M 3 4 

DB3 

10 

LINE_B 

R85 

DB4 

23 

9 

TT1-6-KK81 

Jumper 

COMP2 DB5 

19 

8 

COM_DB6 

D1 D2 

COMP1 DB6 

7 

COM_DB7 

Compliance is 1.25V 

ZMM5227B 

C103 

DB7 

18 

6 

COM_DB8 

Nov 21, 2001 Added other terminati on and resistors 

=> Zout/leg = 62.5 ZMM5227B 

100nF 

FSADJ DB8 

17 

5 

1 REFIO DB9 

COM_DB9 

1 

ohms. So the ideal 

16 

4 

REFLO DB10 

COM_DB10 

load impedance is 125 

3 

DB11 

COM_DB11 

24 

2 

ohms = 250 || 250, 

AVDD DB12 

COM_DB12 

27 

1 

where one of t hose is 

DVDD DB13 

COM_DB13 

the reflected value 

20 

28 COM_CLK 

Give me a good reason to run this D AC from CLKx2... 

ACOM CLK 

from throug h the 

26 

15 

Instead, I think it should be run fr om a line from the 

DCOM SLEEP 

transformer.. 

FPGA, and the line should be monitored by an input of the 

C105 R122 C106 C107 

Since 

atwd if timing precision measureme nts are desired. 

100nF 2K 1% 100nF 100nF C108 AD9708AR 

z1/z2=(n1/n2) ^2, a 

100nF 

2:1 transfo rmer 

COM_TX_SLEEP 

transforms a 2 00 ohm 

Title 

load impedanc e to a 

Digital Optical Module Communication 

140 ohm line. 

Possible upgrade to AD9754AR 


C 

 

A C 

C 

C99 

100nF 

C293 

100nF 

C292 

10uF 6.8V Tan 

C97 

100nF 

Jumper 

JU3 1 2 

1 2 

JU1 1 2 

1 2 

Open Ckt 

5Vanalog 

14 

PDWN 

6 2 

5 

REFT MODE 

REFB 

24 

DVdd 

7 

4 

AVdd 

12 

3 

VREF AVdd 

23 

SENSE DGnd 

8 

AGnd 

11 

AGnd 

NC 

NC 

15 

16 

3.3V 3.3V 

AD9215BRU-65 

R300 

C28 

100nF 

39K 

C100 

100nF 

B13 

LI0805D121R 

3.3V 

JU4 

JU2 

1 2 

1 2 

Jumper 

1 2 

1 2 

Open Ckt 

2.5V 

3.3V 

A 

B 

C 

D 



E

5 

1 

A 

8 

B 

C 

D 

E 

1 GND 

2 CLK 

3 CLK\ 

FL_ON_OFF 

4 GND 

3.3V 

JP9 

5 FL_D0 

C354 

6 FL_D1 

100nF LVDS to LVDS 

1 4 

7 FL_D2 

FL_CLK 2 3 FL_nCLK 

U46 

8 FL_D3 

FL_D0 5 8 FL_D3 

FL_CLK 

FL_D1 

FL_D2 

9 FL_D4 

CLK 

3 

6 

6 7 

FL_D4 

10 FL_D5 

9 12 FL_D7 

FL_nCLK 

FL_D5 

FL_D6 

11 FL_D6 

nCLK 

2 

7 

10 11 

13 16 

12 FL_D7 

FL_nOE 

FL_nWE 

FIN1101M 

14 15 

13 RD\ 

-5V 1.8V 2.5V 3.3V 5Vanalog JP11 

R231 

FL_A0 17 

20 FL_A3 

14 GND 

100 1% 

FL_A1 18 19 FL_A2 

15 GND 

Locate close to JP9 

FL_A4 21 

24 FL_ON_OFF 

1 2 

FL_A5 

16 WR\ 

3 4 

AUX_CTL 

4 22 23 

4 

FL_1.8V 25 

28 FL_3.3V 

17 FL_A0 

5 6 

FL_-5V 26 27 FL_+5V 

18 FL_A1 

7 8 

9 10 

29 

32 

19 FL_A2 

DAC_Out_0 

FL_Trigger 

30 31 

11 12 

FL_Trigger_bar 20 FL_A3 

DAC_Out_1 

FL_D[0..7] 

FL_D0 

FL_UNDEFINED 

33 

36 

13 14 

FL_ATTN 21 FL_A4 

34 35 

FL_D1 

FL_PRE_TRIG 

HEADER 7X2 

22 FL_A5 

FL_D2 

FL_TDI 

37 

40 

FL_TMS 

23 GND 

Mount this connector anyw here that all 

FL_D3 

FL_TDO 

38 39 

FL_TCK 

41 

44 

24 ON /OFF 

power supply voltages ar e available. 

FL_D4 

42 43 

25 1.8V 

FL_D5 

45 

48 

26 +5V 

Can be used to power and control altern ate PMT power supply 

FL_D6 

FL_D7 

90V_Pos 

46 47 

90V_Neg 

27 -5V 

28 3.3V 

29 GND 

FL_A[0..5] 

FL_A0 

12 x 4 SamTec ESQT-112-02-L-Q-078 

30 TRIG 

FL_A1 

31 TRIG\ 

FL_A2 

FL_A3 

32 GND 

FL_A4 

Looking down on the comp onent side of 33 Unde fined 

FL_A5 

the DOM main PCB the pin pattern will 34 GND 

look like the ima ge above 

35 PRE _TRIG 

36 FL_ ATTN 

37 TDI 

38 TDO 

39 TCK 

40 TMS 

41 GND 

42 GND 

43 GND 

B48 

B52 

44 GND 



45 GND 

FL_+5V 

FL_1.8V 

46 90V _Pos 

+5V unfiltered 

1 2 

1.8V 

1 2 

47 90V _Neg 

C255 

C257 + C254 

C314 

C264 + C123 

48 GND 

3 100nF 

100nF 47uF/6.3V Tan 

100nF 


3 

45 GND 

In the 4x10 arrangement, this looks l ike the following: 

-5V 

B49 


1 2 

C256 

C161 

100nF 

100nF 

+ 

FL_-5V 

47uF/6.3V Tan 

C430 

3.3V 

B51 


1 2 

C376 

C231 

100nF 

100nF 

FL_3.3V 

+ C429 

47uF/6.3V Tan 

GND FL_D0 FL_D4 RD\ FL_A0 FL_A4 1.8V GND Undef TDI GND GND 

CLK FL_D1 FL_D5 GND FL_A1 FL_A5 +5V TRIG GND TDO GND 90V Pos 

CLK\ FL_D2 FL_D6 GND FL_A2 GND -5V TRIG\ PRE_TRIG TCK GND 90V_Neg 

GND FL_D3 FL_D7 WR\ FL_A3 ON/OFF 3.3V GND ATTN TMS GND GND 

1 GND 

2 SCK - Serial clock 

3 SCK 

4 MOSI -Serial data in 

5 MOSI 

6 MISO - Serial d ata out 

1 TP12 TEST POINT 

7 MISO 

B44 B45 

JP8 

8 GND 

1812K121R Bead 1812K121R Bead 

BASE_SCLK 

JP101 

9 CS0 (DAC) - Chip sele ct for DAC 

BASE_MOSI 


1 2 1 2 

1 2 

BASE_SCLK 

1 2 

3 4 BASE_MISO 10 CS0 

BASE_MOSI 

3 

NC 

NC 

4 

C247 C248 C249 

5 6 

+ C246 

11 CS1 (ADC) - Chip sel ect for ADC 

NC 

NC 

BASE_MISO 

5 6 

100nF 100nF 100nF 47uF/6.3V Tan 

7 8 

BASE_nCS0 12 CS1 

TEST POINT TP13 1 

BASE_nCS0 

9 10 

TP15 

7 

CLK 

CLK 

8 


BASE_nCS1 

TEST POINT 1 

BASE_nCS1 

13 ON/OFF - Power supply e nable/disable 

9 

PIN 

PIN 

10 


11 12 BASE_ON/OFF 


PIN 

PIN 


14 ON/OFF 

BASE+5V 

BASE_ON/OFF 

BASE+5V 

TEST POINT TP19 

11 12 

C251 C252 C253 + C250 

13 14 

1 

15 +5V - Main power 

13 

PIN 

PIN 

14 


100nF 100nF 100nF 47uF/6.3V Tan 

15 16 


15 

PIN 

PIN 

16 


BASE-5V 

BASE-5V 16 +5V 

1 TP24 

1 2 1 2 

17 18 


17 

PIN 

PIN 

18 

TEST POINT 

-5V unfiltered 

19 20 

17 GND 


PIN 

PIN 


TP27 

19 20 

TP28 

B46 B47 

3M1120 2mm pitch 

18 GND 

TEST POINT 1 

21 

PIN 

PIN 

22 

1 

TEST POINT 

1812K121R Bead 1812K121R Bead EEU-FC1E470 

PMT-Power-S upply 



19 -5V - Main power 


23 

PIN 

PIN 

24 

1 

PIN 

PIN 


P10267-ND 

20 -5V 

25 26 

3M1120-ND from Di gi-Key, 



to match the interface do cument, Jan 


27 

PIN 

PIN 

28 

2 or equival ent 

1 

1 TP36 

29 

PIN 

PIN 

30 

TEST POINT 

02, '03 


PIN 

PIN 


2 


31 32 

1 


33 

PIN 

PIN 

34 


35 

PIN 

PIN 

36 



1 TP44 

37 

PIN 

PIN 

38 

TEST POINT 


PIN 

PIN 


39 

40 

GND 

GND 

MICTOR 38 connector 

41 

42 

43 

GND 

GND 

GND 

10K 1% 10K 1% 10K 1% 10K 1% 

R220 R223 R226 R229 

10K 1% 10K 1% 10K 1% 

R222 R225 R228 

3.3V 10K 1% 10K 1% 10K 1% 10K 1% 

R221 R224 R227 R230 

This connector is meant to be used dur ing pre-production 

debugging. The footpring should be mounted on a part of the board 

that is later broken off and discarded. T he test-points will be 

used to tack down one of wires that bring s ignals out of the main 

board. 

Compatible with model P6434 

probe for Tektronix logic 

analyzer. 

JP100 

39 

40 

41 

42 

43 

1 2 

NC 

NC 

3 4 

5 

NC 

NC 

6 

FPGA_D0 

EX_DCD 

7 

CLK 

CLK 

8 

PIN 

PIN 

FPGA_D0 

FPGA_D1 

EX_DSR 

9 10 

FPGA_D1 

FPGA_D2 

EX_RXD 

11 

PIN 

PIN 

12 

FPGA_D2 

FPGA_D3 

EX_RTS 

13 

PIN 

PIN 

14 

PIN 

PIN 

FPGA_D3 

FPGA_D4 

EX_TXD 

15 16 

PIN 

PIN 

FPGA_D4 

FPGA_D5 

EX_CTS 

17 18 

PIN 

PIN 

FPGA_D5 

FPGA_D6 

EX_DTR 

19 20 

PIN 

PIN 

FPGA_D6 

FPGA_D7 

21 22 

PIN 

PIN 

FPGA_D7 

FPGA_RW 

23 24 

PIN 

PIN 

FPGA_CE 

FPGA_CE 

25 26 

PIN 

PIN 

FPGA_DA 

FPGA_DA 

27 28 

FPGA_RW 

1 PIN 

PIN 

29 30 

1 

PIN 

PIN 

31 32 

PIN 

PIN 

33 34 

PIN 

PIN 

35 36 

PIN 

PIN 

37 38 

PIN 

PIN 

GND 

GND 


GND 

GND 

GND 

Compatible with model P6434 

probe for Tektronix logic 

analyzer. 

Title 

Off-Board Subsystems 


C 

 

A 

B 

C 

D 



E

A 

B 

C 

D 

E 

5Vanalog 

1 2 

Drive this node with Tri-State output of FPGA. 

A pull-up will deliver a positive unit pulse. 

R141 

LI0805D121R 100nF 

A pull-down will deliver a negative unit pulse. 

COINCIDENCE_OUT_UP 

1 2 

3 U40 

R143 

+ 

1 

2 1 

1.1K 

R139 

4 

- 

499 

AD8005RT 

75.0 

4 4 

Balanced output to minimise noise on the board during an event. 

Note to FPGA designer: 

'COINCIDENCE_OUT_Nxx 

lines must 'float' when 

not signaling (ie 

high-Z state of 

tri-state output). 

Both positive and 

negative pulses are 

permitted by pulling up 

or down on the inputs 

to the driver op-amps. 

COINCIDENCE_OUT_DOWN 

A 

B 

Make sure that when the op-amps 

are driven, there is no 

significant bounce on the 

'ground' pins of the power 

splitters. 

Design for 1V output swing of driver=>0.5V at 

port =>0.3535V at sum port. 

0.3535V from neighbor at sum port => 0.175V at 

port B => 0.87V threshold. 

Tune with resistor between bases of Q21, Q22. 

C 

Thresholds should be 

+/- 0.08V or so 

above and below 

COINC_REF. 

R378 

B7 LI0805D121R 

499 

R379 

1 2 

3 3 

1 2 

1K 1% 

U7 

C59 100nF 

MAX4166ESA 

5Vanalog 

2 

7 

R380 1K 1% 

+ 1 2 

1 

3 

R381 

- 

8 

TP50 

U64 

1K 1% 

Latch 5 

R146 2.2K 

2-Pin Header 

COINC_REF 3 

15.0K 1% 

MAX9013EUA 2 1 

+ 

6 

2 

- 

C164 47pF NPO 

C389 

R382 

COINC_UP_BLATCH 

C388 

8.1K 

5Vanalog 

5Vanalog 

R383 

TP47 

B37 LI0805D121R 

U10 

100 

1 

2-Pin Header 

1 2 

I good four quadrent low power 1.65V reverence could 

2 

be used in place of the MAX4166 and associated 

C390100nF 

R356 51 

LOCAL_COINCIDENCE_Upper 

circuitry. A potential problem for this circuit is 

U8 

3 

4 

COINC_DOWN_ABAR 

the stability of the MAX4161 when either or both of 

LOCAL_COINCIDENCE_Lower 

2 

7 

5 

+ R350 51 

the opamps are driven. Varify with first prototype. 

1 

TP48 

3 - 

8 

1 2 

6 

7 

COINC_DOWN_A 

2-Pin Header 

Latch 5 

12 

MAX9013EUA R385 2.2K TP51 

R345 51 

TB5 

Z1A PSC-2-2-75 

1 

2-Pin Header 

11 

10 

sum_up 

COINC_DOWN_B 

board_to_wire 1 

3 

T3 

4 

1 

2 

2 1 

15 

1 

SUM PORT GROUND 

3 

4 

R347 51 

R806 

GROUND GROUND 

2 5 

5 6 

port_2up 

C391 147pF NPO 

14 

13 

COINC_DOWN_BBAR 

TB6 

1M 

PORT 1 PORT 2 

7 8 

R384 

COINC_DOWN_ALATCH 

board_to_wire 

GROUND GROUND 

1 

1 6 

1 

FSTD3125M 

2 1 

CAUTION 

5Vanalog 

T3-1T-K81 

2 2 

A balanced waveform, like AMI, is Gnd of PSC-2-2 operates 

B40 LI0805D121R 

desirable for transmission over this at pedestal potential 

75.0 

1 2 

pathway. 

4 

SDWN 

Vc c 

TB7 

board_to_wire 

1 

1 

1 2 

T3-1T-K81 

Coincidence-REF 2 1 

2 1 

It may be possible to replace 

the PSC-2-2 with a simple 

C392 47pF NPO 

Nov 21, 2001 Bob added 

transformer, but this requires 

C393 C394 C165 C450 

75.0 

COINC_DOWN_BLATCH 

1M resistors to taking into account impedance 

1nF NPO 10nF 100nF 10uF 6.8V Tan 

R125 

transformers. 

150* 

1 1 

R137 150* 

Power = 4*1.3*5 + 2*0.4*5 + 1*1.3*5 = 36 mW 

Vee 

TB8 

board_to_wire 

1 

1 

7 

8 

R374 

1 2 

1.1K 

100nF 

1 2 

1uF X7R 

1 

2 

1 

2 

R807 

1M 

R372 

1K 1% 

5Vanalog 

B20 

1 2 1 2 

1 

2 

R377 

3 

T2 

2 

1 

1 2 

B36 

5 

2 

C160 

LI0805D121R 100nF 

4 

5 

6 

R144 

1K 1% 

3 

4 

5 

+ 

- 

2 

C387 

1 2 

U59 

1 

AD8005RT 

sum_down 

1 2 

matching side-effects. In any 

case, T2, T3 will have to be 

chosen to match the splitter to 

the twisted pair cable. 

2 

R376 

75.0 

1 

1 

2 

port_1down 

port_1up 

1 

2 

1 

2 

COINC_REF 

1 

2 

3.3V 

1 

2 

1 

2 

1 

2 

1 

2 

Z2A PSC-2-2-75 

1 

2 

SUM PORT GROUND 

3 

4 

GROUND GROUND 

5 6 

PORT 1 PORT 2 

7 8 

GROUND GROUND 

R373 

15.0K 1% 

R375 

1K 1% 

sum_down 

port_1down 

R387 

port_2down 

4 

3 

5 

2 

6 

1 

Z2B 

port_2down 

T1-6-KK81* 

U6 

2 

3 

U9 

2 

3 

sum_up 

port_1up 

5Vanalog 

B21 LI0805D121R 

1 2 

1 

1 

6 

1 

6 

1 

C162 

+ 

- 

Latch 

6 

+ 

- 

Latch 

6 

100nF 

7 

8 

5 

MAX9013EUA 

C62 100nF 

7 

8 

5 

MAX9013EUA 

5Vanalog 

4 

3 

5 

2 

D 

1 2 

R145 2.2K 

2 1 

C163 

6 

1 

COINC_UP_ALATCH 

1 2 

R386 2.2K 

port_2up 

Z1B 

47pF NPO 

Title 

TP49 

1 

2-Pin Header 

1 

U11 

2 

3 

5 

6 

12 

11 

15 

14 

TP52 

2-Pin Header 

8 16 

8 16 

5Vanalog 

FSTD3125M 

R360 51 

4 

R359 51 

7 

R357 51 

10 

R358 51 

13 

Digital Optical Module Local Coincidence 

COINC_UP_ABAR 

COINC_UP_A 

COINC_UP_B 

COINC_UP_BBAR 

T1-6-KK81* 


B 0 


Sheet 10 of 15 

E

A 

+ 

B 

C 

D 

E 

JU10 

1 2 

C172 

C144 3.3V C145 

3.3V 1 2 

100nF 

100nF 100nF 

MEMVIO 

Open Ckt 

C166 

JU13 

100nF 

Flash Chip Select routed through PLD 

MEMCORE 

EBD[0..15] 

3.3V 3.3V 

2.5V 

1 2 

C456 

1 2 

FA[0..17] 

FD[0..15] 

OSCON_6SC10M 

U31 

Jumper 

U33 

FA0 1 

7 FD0 

FA1 

A0 D0 

+ + 

FD1 

EBA[0..24] 

U37 

2 

8 

C452 

EBA1 

EBD0 

FA2 

A1 D1 

E3 

25 

29 

3 

9 FD2 

EBA2 

24 

A0 

DQ0 

31 EBD1 

FA3 4 

A2 D2 

E7 

NC 

B2 

C177 

10 FD3 

OSCON_6SC10M 

H3 

NC Vddq 

B7 

100nF 

EBA3 

23 

A1 

DQ1 

33 EBD2 

FA4 5 

A3 D3 

13 FD4 Power: 3.3V * 75mA for S ELECTED chip 

C453 

NC Vddq 

EBA4 

A2 

DQ2 

EBD3 

FA5 

A4 D4 

H7 

C9 

C169 

22 

35 

18 

14 FD5 = 247.5 mW 

OSCON_6SC10M 

NC Vddq 

EBA5 

21 

A3 

DQ3 

38 EBD4 

FA6 19 

A5 D5 

D9 

100nF 

15 FD6 

EBA6 

20 

A4 

DQ4 

40 EBD5 

FA7 20 

A6 D6 

K2 

Vddq 

E1 

C132 

16 FD7 

EBA7 

19 

A5 

DQ5 

42 EBD6 

FA8 21 

A7 D7 

K3 

NC Vddq 

L1 

100nF 

29 FD8 

NC Vddq 

EBA8 

A6 

DQ6 EBD7 

FA9 

A8 D8 

4 M9 

C133 

18 

44 

22 

30 FD9 

4 

EBA9 

EBD8 

FA10 

FD10 

SD_CLK 

J1 

Vddq 

N9 

100nF 

8 

A7 

DQ7 

30 

23 

A9 D9 

31 

J2 

CLK Vddq 

P2 

EBA10 

7 

A8 

DQ8 

32 EBD9 

FA11 24 

A10 D10 

32 FD11 

SD_CLKE 

CKE Vddq 

EBA11 

A9 

DQ9 EBD10 

FA12 

A11 D11 

FD12 

A[0..14] 

P7 

6 

34 

25 

35 

A0 

G8 

Vddq 

EBA12 

EBD11 

FA13 

FD13 

D[0..31] 

5 

A10 

DQ10 

36 

26 

A12 D12 

36 

A1 

G9 

A0 

R8 D0 

EBA13 

4 

A11 

DQ11 

39 EBD12 To provide the 

FA14 27 

A13 D13 

37 FD14 

A2 

A1 D0 

D1 

EBA14 

A12 

DQ12 EBD13 compatibility w ith the 

FA15 

A14 D14 

F7 

N7 

3 

41 

42 

38 FD15 

A3 

F3 

A2 D1 

R9 D2 60mA x 2.5V = 150 mW per memory chip 

EBA15 

2 

A13 

DQ13 

43 EBD14 AMD Am29DL 322D 

FA16 43 

A15 D15 

A4 

G1 

A3 D2 

N8 D3 

EBA16 

1 

A14 

DQ14 

45 EBD15 

FA17 44 

A16 

6 

nFCS0 

A5 

D4 

EBA17 

48 

A15 

DQ15 

A17 CS 

G2 

A4 D3 

P9 

39 

A6 

A5 D4 

D5 

EBA18 

A16 

nFLB 

17 

9 

R340 

LB 

G3 

M8 

NC 

28 

40 

nFUB 

A7 

D6 

EBA19 

16 

A17 

NC 

10K 1% 

NC UB 

H1 

A6 D5 

M7 

3.3V 

A8 

H2 

A7 D6 

L8 D7 

EBA20 

15 

A18 

A9 

A8 D7 

D8 

EBA21 

A19 

J3 

L2 

10 

14 

Flash_nWP 

17 

nFWE 

A10 G7 

A9 D8 

M3 D9 

Flash_nOE 

28 

A20 

WP 

12 

WE 

nRESET 

41 

nFOE 

A11 H9 

A10 D9 

M2 D10 

A13 

D11 

Flash_nWE 

11 

OE 

RP 

OE 

A11 D10 

WE 

J7 

P1 

Flash_nCS0 

26 

K6R4016V1D-E 

A14 

D12 

CE 

Feb 3, 2003 gtp 

SD_CS_N[0..1] 

H8 

BA0 D11 

N2 

BA1 D12 

R1 D13 

R337 

SD_CS_N0 J8 

D13 

N3 D14 

TE28F320C3BC90 

10K 1%* 

CS D14 

D15 

3.3V 

nWE 

K8 

R2 

C149 C148 

WE D15 D16 

3.3V 

E8 

4 Megabyte 

100nF 100nF 

J9 

D16 

D7 D17 

Flash 

Nov 21, 2001 

nRAS 

RAS D17 D18 

nCAS 

K7 

D8 

Memory 

Thorsten.. Pul l up on 

CAS D18 D19 

U32 

SD_DQM[0..3] 

B9 

on nWP and RESET 

SD_DQM0 K9 

D19 

C8 D20 

3.3V 3.3V 

FA0 1 

7 FD0 

SD_DQM1 DQM0 D20 D21 

FA1 

A0 D0 

K1 

A9 

2 

8 FD1 

SD_DQM2 F8 

DQM1 D21 

C7 D22 

U38 

FA2 3 

A1 D1 

9 FD2 

SD_DQM3 F2 

DQM2 D22 

A8 D23 

EBA1 

25 

29 EBD0 

FA3 4 

A2 D2 

10 FD3 

DQM3 D23 D24 

EBA2 

A0 

DQ0 EBD1 

FA4 5 

A3 D3 

A2 

24 

31 

13 FD4 

D24 D25 

EBA3 

A1 

DQ1 

EBD2 

FA5 

A4 D4 

B3 

C3 

23 

33 

18 

14 FD5 

B8 

GNDq D25 

A1 D26 

EBA4 

22 

A2 

DQ2 

35 EBD3 

FA6 19 

A5 D5 

15 FD6 

C1 

GNDq D26 

C2 D27 

EBA5 

21 

A3 

DQ3 

38 EBD4 

FA7 20 

A6 D6 

16 FD7 

GNDq D27 D28 

EBA6 

A4 

DQ4 EBD5 

FA8 

A7 D7 

D1 

B1 

20 

40 

21 

29 FD8 

E9 

GNDq D28 

D2 D29 

EBA7 

19 

A5 

DQ5 

42 EBD6 

FA9 22 

A8 D8 

30 FD9 

L9 

GNDq D29 

D3 D30 

EBA8 

18 

A6 

DQ6 

44 EBD7 

FA10 23 

A9 D9 

31 FD10 

GNDq D30 D31 

EBA9 

A7 

DQ7 EBD8 

FA11 

A10 D10 

M1 

E2 

8 

30 

24 

32 FD11 

N1 

GNDq D31 

EBA10 

7 

A8 

DQ8 

32 EBD9 

FA12 25 

A11 D11 

35 FD12 

3 P3 

GNDq 

EBA11 

6 

A9 

DQ9 

34 EBD10 

FA13 26 

A12 D12 

36 FD13 

3 

P8 

GNDq 

EBA12 

5 

A10 

DQ10 

36 EBD11 

FA14 27 

A13 D13 

37 FD14 

GNDq 

EBA13 

A11 

DQ11 EBD12 

FA15 

A14 D14 

4 

39 

42 

38 FD15 

EBA14 

3 

A12 

DQ12 

41 EBD13 

FA16 43 

A15 D15 

EBA15 

2 

A13 

DQ13 

43 EBD14 

FA17 44 

A16 

6 

EBA16 

A14 

DQ14 EBD15 

A17 CS 

nFCS1 

1 

45 

39 

EBA17 

LB 

48 

A15 

DQ15 

NC 

28 

40 

K4S64323LF-S(D)P-15 

EBA18 

17 

A16 

9 

NC UB 

EBA19 

A17 

NC 

16 

C176 

EBA20 

15 

A18 

17 

100nF 

EBA21 

10 

A19 

14 

WE 

41 

C167 

28 

A20 

WP 

12 

OE 

100nF 

OE 

RP 

11 

K6R4016V1D-E 

MEMCORE 

Flash_nCS1 

26 

WE 

CE 

A7 

F9 

L7 

R7 

Vdd 

Vdd 

Vdd 

Vdd 

8MB SDRAM 

A3 

F1 

L3 

R3 

U36 

MEMVIO 

TE28F320C3BC90 

C152 3.3V C153 

E3 

Flash Memory 

JU15 

100nF 

100nF 

NC 

E7 

B2 

C170 

VPP 

1 2 

3.3V 

H3 

NC Vddq 

B7 

100nF 

1 2 

H7 

NC Vddq 

C9 

C174 

With the PLD using a driv er, I don't 

Jumper 

U34 

NC Vddq 

D9 

100nF 

think these pull-ups a re needed. 

FA0 1 

7 FD0 

Vddq 

K2 

E1 

C175 

FA1 

A0 D0 

2 

8 FD1 

K3 

NC Vddq 

L1 

100nF 

Flash_nCS0 

R328 4.7K 

FA2 3 

A1 D1 

9 FD2 

NC Vddq 

M9 

C168 

FA3 4 

A2 D2 

10 FD3 

Vddq 

Flash_nCS1 

FA4 

FD4 

SD_CLK 

J1 

N9 

100nF 

R321 4.7K 

A3 D3 

3.3V 

5 

13 

FA5 

FD5 

SD_CLKE 

J2 

CLK Vddq 

P2 

18 

A4 D4 

14 

CKE Vddq 

P7 

FA6 19 

A5 D5 

15 FD6 

A0 

Vddq 

FA7 

A6 D6 

G8 

20 

16 FD7 

A1 

G9 

A0 

R8 D0 

FA8 21 

A7 D7 

29 FD8 

A2 

F7 

A1 D0 

N7 D1 

FA9 22 

A8 D8 

30 FD9 

A3 

F3 

A2 D1 

R9 D2 

FA10 23 

A9 D9 

31 FD10 

A4 

A3 D2 

D3 

3.3V 

FA11 

A10 D10 

G1 

N8 

24 

32 FD11 

A5 

G2 

A4 D3 

P9 D4 

FA12 25 

A11 D11 

35 FD12 

A6 

G3 

A5 D4 

M8 D5 Samsung 8 Megab yte 32 

FA13 26 

A12 D12 

36 FD13 

A7 

A6 D5 

D6 bit wide memor y for 

FA14 

A13 D13 

H1 

M7 

27 

37 FD14 

A8 

H2 

A7 D6 

L8 D7 mobile compu ters 

FA15 42 

A14 D14 

38 FD15 

A9 

D8 

FA16 

2 J3 

A8 D7 

L2 

43 

A15 D15 

(laptop) has 

2 

A10 

A9 D8 

G7 

M3 D9 

C134 C135 C136 C137 C138 

FA17 

A16 

44 

6 

A11 

D10 reasonable po wer. 

nFCS2 

H9 

A10 D9 

M2 

100nF 100nF 100nF 100nF 100nF 

A17 CS 

39 

A13 J7 

A11 D10 

P1 D11 Several of t heir 

NC 

28 

LB 

40 

A14 H8 

BA0 D11 

N2 D12 products have th e same 

NC UB 

BA1 D12 

R1 D13 footprint. 

SD_CS_N1 J8 

D13 

N3 D14 

K4S64323LF-S( D)U15 

17 

D15 

nWE 

K8 

CS D14 

R2 

WE 

41 

WE D15 D16 (superlow power -25C) 

OE 

E8 

D17 K4S64323LF-S( D)P15 

nRAS 

J9 

D16 

D7 

K6R4016V1D-E 

D18 (low power - 40C) 

nCAS 

K7 

RAS D17 

D8 

CAS D18 

Jan 19, 2003 Correct swapped power pins on SDRAM 

D19 

SD_DQM[0..3] 

B9 

2.5V core, 1.8V I/O. 

SD_DQM0 K9 

D19 

C8 D20 

1.8V I/O requ ires 

3.3V 

SD_DQM1 K1 

DQM0 D20 

A9 D21 

SD_DQM2 

D22 

special regi ster 

C156 C157 

F8 

DQM1 D21 

C7 

100nF 

100nF 

JP102 

SD_DQM3 DQM2 D22 

F2 

A8 D23 set-up for CPU. 

1 2 

DQM3 D23 

A2 D24 

3 

NC 

NC 

4 

B3 

D24 

C3 D25 

U35 

GNDq D25 D26 

FA0 

FD0 

CLKx2 

5 

NC 

NC 

6 

nWE CLK 

CLK nFOE 

nCLKx2 

B8 

A1 

1 

7 

7 8 

C1 

GNDq D26 

C2 D27 

FA1 2 

A0 D0 

8 FD1 

FA0 9 

PIN 

PIN 

10 FA1 

D1 

GNDq D27 

B1 D28 

FA2 3 

A1 D1 

9 FD2 

FA2 11 

PIN 

PIN 

12 FA3 

GNDq D28 

E9 

D2 D29 

FA3 

A2 D2 

FD3 

FA4 

PIN 

PIN 

4 

10 

13 14 FA5 

L9 

GNDq D29 

D3 D30 

FA4 

A3 D3 

FD4 

FA6 

PIN 

PIN 

5 

13 

15 16 FA7 

M1 

GNDq D30 

E2 D31 

FA5 

A4 D4 

FD5 

FA8 

PIN 

PIN 

18 

14 

17 18 FA9 

N1 

GNDq D31 

FA6 

A5 

FD6 

FA10 

PIN 

PIN 

19 

D5 

15 

19 20 FA11 

GNDq 

P3 

FA7 

A6 D6 

FD7 

FA12 

PIN 

PIN 

20 

16 

21 22 FA13 

P8 

GNDq 

K4S64323LF-S(D)P-15 

FA8 

A7 D7 

FD8 

FA14 

PIN 

PIN 

21 

29 

23 24 FA15 

GNDq 

FA9 

A8 D8 

FD9 

FA16 

PIN 

PIN 

22 

30 

25 26 FA17 

Cross to Mi cron 

FA10 

A9 D9 

FD10 

FD0 

PIN 

PIN 

23 

31 

27 28 FD1 

MT48V4M32LFFC-10T a which 

FA11 

A10 D10 

FD11 

FD2 

PIN 

PIN 

24 

32 

29 30 FD3 

requires address l ine A11 

FA12 

A11 D11 

FD12 

FD4 

PIN 

PIN 

25 

35 

31 32 FD5 

FA13 

A12 D12 

FD13 

FD6 

PIN 

PIN 

26 

36 

33 34 FD7 

FA14 

A13 D13 

FD14 

nFCS0 

PIN 

PIN 

27 

37 

35 36 nFCS1 

FA15 

A14 D14 

FD15 

nFCS2 

PIN 

PIN 

42 

38 

37 38 nFCS3 

FA16 

A15 D15 

PIN 

PIN 

43 

FA17 

A16 

44 

6 


A17 CS 

nFCS3 

39 

LB 

NC 

28 

40 

1 NC UB 

1 

A7 

F9 

L7 

R7 

GND 

GND 

GND 

GND 

Vdd 

Vdd 

Vdd 

Vdd 

8MB SDRAM 

GND 

GND 

GND 

GND 

A3 

F1 

L3 

R3 

37 

VCC 

GND 

46 

37 

VCC 

GND 

46 

47 

27 

VCCQ 

47 

27 

VPP 

13 

VCCQ 

VPP 

13 

11 

33 

Vdd 

Vdd 

GND 

GND 

12 

34 

11 

33 

Vdd 

Vdd 

GND 

GND 

12 

34 

11 

33 

Vdd 

Vdd 

GND 

GND 

12 

34 

11 

33 

Vdd 

Vdd 

39 

40 

GND 

GND 

41 

42 

43 

GND 

GND 

GND 

K6R4016V1D-E 

GND 

GND 

12 

34 

WE 

OE 

17 

41 

Title 

Digital Optical Module Memory 


C 

 

A 

B 

C 

D 



E

8 

5 

4 

1 

4 

A 

1 

4 

5 

3 

1 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

B 

C 

D 

E 

An address space of 16 registers 

R364 10K 1% 

U29 

3.3V 

BASE_MISO 

Require MUX_ENA low a t power up. 

2 

143 

R63 

Require HV power sup ply control 

PLD_TP 

CONF_DONE 

BAROMETER_ENA 

TP53 

B1(GTS2) A3(GSR) 

3 

142 

at power up, and through 

2-Pin Header 

1 

SC_nCS2 

B2(GTS3) *A4 

SC_MOSI 

A_nB 

3.3V 

U82G 

2 

4 

140 

Gnd 

DSR_Local 

FL_D0 

SEL_A0 

100 1% R102 5 

B3 

A6 

139 

100K 1% 

IO_Bank_B7 

reloading the FPGA. 

100 1%R303 

FL_D1 

EX_CTS 

BOOT_FLASH line control Monitor ADC (i2c) A D/DA Page SC_nCS6 

6 

B5(GTS0) *A12 

138 

3.3V 

EX_CTS 

G22 

FL_D2 

EX_DSR 

UART_CTS_N 

MUX_EN0 

7 

B12(GTS1) A13 

137 

JP14 

A_nB 

FL_D3 

EX_DSR 

H22 

B13 *A14 

EX_RXD 

UART_DSR_N 

9 

136 

R811 R812 

EX_RXD 

F21 

B14 

Desire: 

FL_D4 

1 

UART_RXD 

SC_MISO 

10 

C1 

135 

10K 1% 10K 1% 

J22 

B15 

ADC and DAC con trol not 

FL_D5 

2 

UART_DCD_N 

ATWD1 DAC SC_nCS1 

11 

*C2 

134 

J21 

D1 

C3 

FL_D6 

Base_nCS0 

EX_TXD 

UART_RI_N 

depending on FPGA l oad (avoid 

MUX_EN1 

12 

133 

HEADER 2 

PLD_TP 

EX_TXD 

G21 

13 

D2 

C5 

132 FL_D7 

EX_RTS 

glitches) 

Base_nCS1 

EX_RTS 

H21 

UART_TXD 

remember source of po wer failure Clk line for SPI/Micr owire & I2c 

14 

D3 

C14 

131 

EX_DTR J20 

UART_RTS_N 

SC_SCLK 

D4 

C15 

FL_A0 

SC_CL 

EX_DTR 

UART_DTR_N 

SEL_A1 

15 

130 

Flash Memory CSR remapping 

SOFT_RESET 16 

D5 

K16 

129 FL_A1 

D6 

FL_A2 

EX_TXD 

nPOR 

17 

K15 

128 

EPXA1F672I2 

100 1% R127 18 

D12 K14 

126 FL_A3 

EBD0 

*D14 K13 

4 19 

125 FL_A4 

4 

EBD1 

20 

G16 K12 

124 FL_A5 

C11 

EBD2 

21 

*G15 K11 

121 R344 100 1% CTS_Local 

EBD3 

G14 

K6 

1 2 

3.3V 

22 

120 

EBD4 

FL_nOE 

PLD_CLK 

23 

G13 

K5 

119 

EBD5 

FL_nWE 

100nF 

24 

G12 

I15 

118 

R320 4.7K 

U18 

DTE 

If the communications AD C and DAC do 

EBD6 

G11 

I14 

FL_ON_OFF 

RTS_Local 

U78 

25 

117 

not load the near by tr anslator too 

EBD7 

FL_UNDEFINED 

3.3V 

14 

9 

G6 

26 

I13 

116 

Soft 

JP17 

TXD_Local 13 

T1IN T1OUT 

10 

heavily, and if the line to the CPLD 

INIT_DONE 

TXD_Local 

Reset 

CTSin 

DTR_Local 

CLK 

7 

28 

G5 

I12 

115 

12 

T2IN T2OUT 

11 

is short, then U78 may be taken out 

30 

E14 

I6 

R312 100 1% 

CR7 

1 

2 

114 

DSRin 

T3IN T3OUT 

EX_DSR 

E6(GCK0) *I4 

R261 100 1% 

AUX_CTL 

S3 

2 

CPU_SERIN1_RS232 

RXD_Local 

of the design, and the clock line nCLK 

8 

31 

113 

EX_CTS 

SC_nCS5 Monitor ADC (i2c) A D/DA Page 

BAV103-7* 

4 

19 

32 

*E5 

I2 

R281 

Per Lantronix 

3 

112 

routed to the GCLK0 l ine of the 

SC_nCS3 

5 

R1IN R1OUT 

18 DSR_Local 

FIN1018K8X 

RXD_Local 

Server 

CTS_Local 

nRESET 

33 

E4(GCK1) I1 

111 R77 100 1% 

3 1 

TP63 

4 

6 

R2IN R2OUT 

17 

CPLD. 

nSTATUS 

*E2 

J1 

34 

110 R833 100 1% 

1 

Temperature Sensor (i2c) AD/DA Page 

documentation 

CPU_SEROUT1_RS232 

SC_nCS7 

4 2 

2-Pin Header 

5 

R3IN R3OUT 

7 

16 

DTRout 

ATWD0 DAC SC_nCS0 

35 

*F1 

J2 

107 

BASE_SCLK 

Jumper 

C139 

6 

8 

R4IN R4OUT 

15 

38 

F2(CDRST) *J3 

106 

100nF 

7 

RTSout 

R5IN R5OUT 

FL_D7 

EB_CLK 

F4(GCLK2) *J4 

BASE_ON/OFF PMT HV Subsy stem 

B3FS-1002P (Omron) 

8 

FL_D6 

SC_nCS4 

39 

105 

C262 

EBA0 

BASE_nCS1 

28 

21 

SPI/MicroW ire 

40 

F12(DGE) J5 

104 

SOFT_RESET 

Feb 3, 200 3 gtp 

Digi-Key A90 45-ND 

FL_D5 

EBA1 

BASE_nCS0 

100nF 

C1+ R1OUTB 

24 

20 

41 

F13 

J6 

103 

port 

Approved F eb 5 

EBA2 

BASE_MOSI 

RJ45 AMP 555764-1 

C261 

1 

C1- R2OUTB 

FL_D4 

42 

F14 J12 

102 EX_RXD 

100nF 

2 

C2+ 

FL_D3 

EBA3 

*F15 J14 

SER_PWR 

Add CR10, C454, C hg R286 

Wired as DTE 

C2- 

43 

101 

27 

MAX3241CWI 

FL_D2 

EBA4 

44 

F16 J16 

100 DTR_Local 

April 27, 200 3 gtp 

Use 1:1 cabl e to 

3 

V+ 

FL_D1 

EBA5 

45 

*H1 

L2 

98 RTS_Local 

V- 

MODEM 

FL_D0 

H2 

L11 

EX_DTR 

EB_nOE 

46 

97 R253 100 1% 

R286 R406 

23 

FL_A5 

EX_RTS 

FL_D[0..7] 

EB_nWE 

48 

*H3 L12 

96 R126 100 1% 

10K 1% 4.7K 

22 

EN 

3.3V 

FL_A4 

EB_nCS3 49 

*H5 L13 

95 

Feb 3, 200 3 gtp 

SHDN 

FL_A3 

EB_nCS2 H6 

L14 

nURESET 

5VAnalog 

50 

94 

Silk screen shows wrong direction. 

C259 C260 

26 

FL_A2 

EB_nCS1 51 

H11 L15 

92 

TP64 

CR10 

DS2 

100nF 100nF 

VCC 

FL_A1 

EB_nCS0 52 

H12 O16 

91 

2-Pin Header 

1 

BR1111C-TR* 

JP18 

FL_A0 

BOOT_FLASH 53 

H13 O15 

88 

R319 130* EX_TXD 

Feb 3, 2003 gtp 

Output used to uncon figure FPGA nCONFIG 

3.3V 

CR11 

P16 O14 

EBD7 

FL_A[0..5] 

+ 

BAV103-7* 

C258 

1 

54 

87 

EBD6 

EX_RXD 

INT_EXT_PIN_N 

56 

P15 O13 

86 

R318 130* 

100nF 

2 

EBD5 This forces the power 

EB_nCS[0..3] 

EB_nCS3 

PLD_FPGA_nWE 

57 

P13 O12 

85 

3 1 

BAV103-7 2 Pin Header 

P12 O11 

EBD4 supply to cr ash, 

SER_PWR 

EB_nCS2 

PLD_FPGA_nOE 

58 

83 

4 2 

DS3 

R317 1K 1% R306 10K 1% 

PLD_FPGA_BUSY 

59 

P11 

O2 

82 

EBD3 initiating power on reset C454 

BR1111C-TR* 

PLD_FPGA0 60 

P6 

M14 

81 

EBD2 nPOR after a time delay. 47uF/6.3V Tan S2 

Unconfigured 

EB_nCS1 

PLD_FPGA1 

P5 

M13 

61 

80 

EBD1 

B3FS-1002P (Omron) 

R305 1K 1%* INIT_DONE 

EB_nCS0 

PLD_FPGA2 

Flash_nWP 

64 

N16 M12 

79 

EBD0 

3 PLD_FPGA3 

FLASH_nWE 

EBA5 

3 

PLD_FPGA[0..7] 

66 

N14 

M6 

78 

DS4 

FLASH_nOE 

EBD[0..15] 

PLD_FPGA4 68 

*N13 M5 

77 

EBA4 

BR1111C-TR* 

PLD_FPGA0 

PLD_FPGA5 

N6 

M3 FLASH_nCS1 

69 

76 

EBA3 

R37 10K 1% 

PLD_FPGA1 

PLD_FPGA6 

FLASH_nCS0 

70 

N4 

M2 

75 

EBA2 

PLD_FPGA2 Add watchdog_con trol bit PLD_FPGA7 71 

N3 

*M1 

EBA1 

PLD_FPGA3 April 27, 20 03 gtp Debug/nWatchdog N2 

74 

EBA0 

PLD_FPGA4 

N1 

PLD_FPGA5 

PLD_TDI 

EBA[0..24] 

R131 10K 1% 

63 

PLD_FPGA6 R130 10K 1% 

PLD_TMS B15-TDI 

3.3V 

65 

PLD_FPGA7 R129 10K 1% 

PLD_TCK 

U62I 

67 

C15-TMS 

8 C276 C275 C274 

R128 10K 1% 

PLD_TDO 122 

F15-TCK VAux 

10nF 100nF 100nF 

Excalibur 

G15-TDO 

3.3V 

1 

Vdd 

1.8V 

JTAG 

29 

37 

Ports 

36 

GND Vdd 

84 

PROC_TMS 

E24 

47 

GND Vdd 

PROC_TDO 

G23 

PROC_TMS 

GND 

EPC EPC 

PROC_TDI 

PROC_TDO 

62 

27 

H23 

72 

GND Vdd1 

55 

PROC_TCK 

F24 

PROC_TDI 

89 

GND Vdd1 

73 

WideAreaFlashe rBoard BYPASS INLINE 

3.3V 

G24 

PROC_TCK 

GND Vdd1 

PROC_TRST 

90 

93 

JP2 

99 

GND Vdd1 

Verticle Entry Shrow ded header 

D16 

108 

GND 

109 

TDO 

TDO2TDI 

B15 

TRST 

123 

GND Vdd2 

127 

EPCTDO 1 2 

EPCTDI TMS 

AE15 

TDO 

GND Vdd2 

3 4 

TCK 

TMS 

144 

141 C109C110C111C112C113C114C140C141 

C142 

AD14 

GND Vdd2 

100nF 100nF 100nF 10nF OSCON 6SC47M 

HEADER 2X2 

TDI 

P5 

TCK 

100nF 100nF 100nF 10nF 

TDI 

XC2C256_TQ144 

JTAG ROUTING 

EPXA1F672I2 

NC 

For bypassing the EPC2, j umper center 

U82J 

to bridging position, pin 1 to pin 2. 

C143 

To put EPC2 into circuit, jumper pin1 

N22 

1 2 

OneSPE 

to pin3, and pin2 t o pin 4. 

N21 

MSEL0 

MSEL1 

D15 

R294 47pF NPO 

P6 

nCEO 

100 

nSTATUS AE12 

nCE 

nCONFIG 

nSTATUS 

M20 

JU39 

DCLK 

PGM13 

OneSPE-C 

R7 

nCONFIG 

V7 

R295 

CONF_DONE 

PGM14 

2 1 2 

AD13 

DCLK 

CS-IO 

Y4 

C147 

2 

10K 1% 

1 2 

INIT_DONE CONFIG_DONE 

nCS-IO 

A23 

Y3 PGM15 

1 2 

IO-INIT_DONE 

nWS-IO 

MultiSPE 

Open Ckt 

T6 

JU381 2 

C14 

nRS-IO 

A22 

R296 47pF NPO 

1 2 

JSELECT 

RDYnBSY-IO 

3.3V 

B23 

100 

Jumper 

CLKUSR-IO 

J23 

U60 

R78 

EN_SELECT 

If it is found t hat the 

nRESET 

MultiSPE-C 

3.3V 

B16 

27 

23 

nRESET 

Vcc Vpp 

configuration is correct, 

1K 1% 

17 

3 

JU11, and JU12 can be 

nPOR 

J24 

VppSel VccSel 

nPOR 

installed during man ufacture. 

R299 

R302 

BOOT_FLASH C16 

A16 

nCE = pull- down 

JU32 

10K 1% 

10K 1% 

BOOT_FLASH 

FAST_IO1 

A15 

nCEO = open ckt 

TCK 

32 28 

EPCTOD1 2 TDO 

Debug/nWatchdog 

TRST = pul l-up 

TMS 

TCK TDO 

D14 

FAST_IO2 

AF15 

JU33 

1 2 

OneSPE 

25 

JU37 

DEBUG_EN 

FAST_IO3 

TDO2TDI 

EPCTDI 

TMS 

AF12 

nSTATUS 

MultiSPE TDI = pu ll-up 

1 2 

13 

7 

Open Ckt 

FAST_IO4 

1 2 

TDI 

OE 

1 2 

C15 

15 

1 2 

GND-*STDCEL_TEST 

TDO = pull-up 

Open Ckt 

nCASC 

16 nCONFIG 

Open Ckt 

PGM6 

PGM7 

TMS = pull-up 

DCLK 

nINIT_CONF 

T7 

U24 

2 

31 

DATA0 

CPU-CLK is a clock that HAS to be t here at power up. 

PGM5 

IO_DATA7 

*LOCK1-IO 

PGM8 

TCK = pul l-up 

CONF_DONE 

DCLK DATA 

V3 

AB3 

10 

FPGA-CLK must be delivered to the F PGA after the FPGA 

PGM4 

PGM9 

nCS 

A18 

IO_DATA6 

LOCK2-IO 

R24 

nSTATUS = pu ll-up 

PGM3 

PGM10 

is configured (a documented work-a round) or a late 

A20 

IO_DATA5 

*LOCK3-IO 

AB4 

CONFIG_DONE = pull-up 

12 

PGM2 

IO_DATA4 

LOCK4-IO 

GND 

version of Quartus must be us ed to compile. 

B22 

PGM1 

nCONFIG = pu ll-up 

B18 

IO_DATA3 

PGM0 

B20 

IO_DATA2 

EPC2 

DATA0 W7 

IO_DATA1 

C146 100nF 

TP6 

DATA0 

2 1 

3.3V 

V5 

IO-DEV_CLRn 

AA3 

JP3 

U84 1 

2-Pin Header 

IO-DEV_OE 

PLD_TCK 

PLD_TDO 

CLK 

7 

2 1 

2 CPU_CLK 

4 3 

PLD_TMS 

6 5 

nCLK 

8 

JP1 

H24 

PGM0 

PGM1 

8 7 

PLD_TDI 

FIN1018K8X 

CLK_REF 

PGM2 1 2 PGM3 

10 9 

PGM4 3 4 

P20 

PGM5 

AMP 2510-6002UB 

3.3V 

CLK1p 

PGM6 5 6 

N20 

PGM7 

C374 

IO-CLK1n 

PGM8 7 8 PGM9 

2 1 

Global 

PGM10 9 10 

W6 

CLK1n 

JP10 

1 TP73 

CLK2p 

PGM12 11 12 

Y6 Clock 

PGM13 

TCK 

1 

100nF 

2-Pin Header 

IO-CLK2n 

PGM14 13 14 

PGM15 

2 1 

Inputs 

TDO 

U85 

15 16 

4 3 

R23 

TMS 

1 

CLK3p 

17 18 

6 5 

R22 

IO-CLK3n 

19 20 

8 7 

2 

4 

TDI 

In Out 

10 9 

Y5 

2mm pitch SMD HEADER 10X2 

C150 

CLK4p 

W5 

AMP 2510-6002UB 

100nF 

IO-CLK4n 

NC7SZ126M5 

2 1 

Service Connec tor for 

3.3V 

JP12 

U83 

R284 

R21 

the convenie nce of 

PROC_TCK 

3.3V 

1K 1% 

CLKLK_ENA 

2 1 

software progr ammers. 

PROC_TDO 

3.3V 

4 3 

Utilizes multif unction 

PROC_TMS 

CLKx2 

2 

N5 

PGM12 CLKLK_FB2p 

7 

M5 

6 5 

pins. 

Title 

IO-CLKLK_FB2n 

8 7 

PROC_TDI 

nCLKx2 

1 

M4 

Digital Optical Module CPU 

CLK1n CLKLK_OUT2p 

P21 

10 9 

FIN1017K8X 

Might want to add some of 

IO-*CLKLK_OUT1n 

M3 

AMP 2510-6002UB* 


these nets to the NC net. 

IO-CLKLK_OUT2n 

C 

 

DO not mount PRC_JTAG connector 

EPXA1F672I2 



A 

B 

C 

D 

E 

INIT_DONE 

OE 

Bank 1 ->| |

5 

4 

3 

2 

1 

E 

D 

C 

B 

5Vanalog 


Driven by a 10 bit DA C 2 

U70 

MAX4166ESA 

SingleLED-TRIGGER 

B32 

LI0805D121R 

1 

2 

C291 

100nF 

3 

+ 

Z=50 ohm transmission li ne 1 2 

Trigger on 

RISING edge. 

Pulse width 

>20 ns. 

- 

4 

R239 

1 2 

100 

SDWN 

Vcc 

Vee 

7 

8 

6 

5.1 mW 

Charge pump voltage doubler driven by a 

buffer driven by a DAC output . 

R237 10 

1 2 

R245 

1 2 

C232 

1nF NPO 

1K 1% 

2 

5 

3 

1 

2 

C239 

2.2uF 6.3V Tan 

1 

2 

1 

2 

R238 

1 2 

C244 

100 

100nF 

U42 

4 

NC7SZ14M5 

1 2 

SN74AHC1G14DBVR 

C242 

10uF 6.8V Tan 

1 2 

C243 

100nF 

R246 

4.7K 

1 

2 

3 

47pF NPO 

FC 

1 

2 

U69 

CAP+ 

GND 

MAX660ESA 

R243 

1 2 

1K 1% 

1 

C245 

0.6 mW 

8 

V+ 

OSC 

LV 

4 5 

CAP- OUT 

Q6 

MMBTH81 

7 

6 

3 2 

G 

1 2 

1 

2 

R235 

1 

100K 1% 

R244 

4.7K 

2 

D 

S 

R247 

1K 1% 

1 

2 

DS1 

UV LED 

G 

TP11 

1 

2-Pin Header 

C240 

2.2uF 16V Tan 

C241 

22pF NPO 

R236 

1 21 2 

Jumper 

Q18 

2N7002 

3 

D 

1 

S 

1 

R240 

2 

3.3 

Q17 

2N7002 

1 

R241 

2 

3.3 

The resistors should be plac ed 

radially at one end of t he 

charge storage capacitor. T he 

inductances shoul d 

be kept as small as possibl e. 

Resistor values smaller than 1 

ohm are available in 

the 1% set. Resistors shou ld 

be chosen to produce a n 

acceptable signal to the ATW D. 

1 

R242 

2 

3.3 

1 2 

R234 

51 

1 

PMT_LED_PULSER 

TP10 

2-Pin Header 

E 

D 

C 

B 

A 

Title 

Digital Optical Module Single LED 


A 0 

A 

5 

4 

3 



2 

1

A 

1 

2 

S 

6 

8 

1 

2 

1 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

1 

2 

2 

2 

2 

2 

2 

B 

C 

D 

E 

Over-Voltage protection f or the power 

supply. I suppose, th is could as 

easily be balanced, using just the N 

At bob's suggestion, put the power pins in the yet bigger 

and P FETs. If it is dee med that the 

flasher board inte rface... 

power supply input vol tage range 

(and tolerence) is great enough, the 

Current contente rs are: 

protection circuit can be deleted 

April 27, 2003 

90V_Pos 

from the des ign. 

gtp Consol idate 

Polytron LWA19-90-5 (a te n watt part) 

bill of 

Power One 70 IMX4-0505-9 (a 4 watt part) 

materials. Lower 

90V_Neg 

Digi-Key Pana sonic 

series R. 

PK1064-ND ELF- 15N002A 

approved F eb 3, The winner may not be fro m this list. 


C85 

L13 

100mH/leg 

BZX84C6V8DI CT-ND 2.2uF 160V PM54-100M 10uH 

2003 gtp 

B24 

B25 

5Vanalog 

B22 

C178 

B23 

R285 

1812K121R Bead 1812K121R Bead 

EEU-FC1E470 

1812K121R Bead L10 

470nF 250v 


PS1 

+5V 1 2 

1 2 

P10267-ND 

c0 

c1 

4 DCIN1 

1 2 1 2 

1 2 

1 2 

22 

14 

4 

C407 

23 

Vin+ 

+5V 

C180 C181 

C182 + C234 

470nF 250v 

CR4 

Vin+ 

0.100 

100nF 100nF 


c3 

c2 

DCIN2 

1 2 4 

3 

1 2 

1 2 

40-120V 

16 

CMHZ5263B 

COM 

B26 

ELF-15N002A 

L11 

C375 

C179 2 

C183 C184 

C185 + C238 


Vin- 

R151 

!! This part 

PM54-100M 10uH 

470nF 250v 470nF 250v 3 

11 

100nF 100nF 


R315 

C88 

B27 

Vin- 

-5V 

-5V_supply 

1 2 

1 2 

is 8 ohms per 

CR5 

10M 

2.2uF 160V 


70 IMX 4-0505-9 

EEU-FC1E470 

Power-One 

B28 

B29 

P10267-ND 

leg!! 

CMHZ5263B 

NOVAcap 

0.100 1812K121R Bead 1812K121R Bead -5V 

1812Z474M2 51NX 

250V Z5U 

-5V unfiltered 

Ceramic 

JP15 

R55 10K 1% 

c0 

c0 

G 

Capacitor 

c1 

1 2 

c1 

c2 

3 4 

c2 

c3 

5 6 

c3 

R316 

7 8 

Q13 

HEADER 4X2* 

10K 1% 

3 2 

For developm ent: A 

BZX84C6V8DIC T-ND IRF644NS 

daughter card plugged 

CR6 Q19 

into JP15 can be used to 

CMHZ5235B 2N7002 CR2 

CMHZ5235B 

design an appr opriate 

filter net work. 

 

A C A C 

A C 

D 

1 2 

A C 

L9 

PM54-100M 10uH 

C187 

4.7uH 

C186 

B31 

R116 OSCON_6SC6R8M 

U56 

L2 

OSCON_6SC10M 

1812K121R Bead C364 

0.100 +3.3V_IN 

15 

14 

OUT1 

1 2 47uF/6.3V Tan 

U39 

INP1 LX1 

C362 

C189 

3.3V 

C190 + 

20 

+ 

+ 

C196 

-5V unfiltered 8 

5 

3 -5V_supply 

Imon-5V 

100nF 

OUT1 

C366 

100nF 

100nF 

100nF 

1 

+IN OUT 

3 

100nF 

-IN 

Assuming a 500 mW 

25 

4 

INP2 

load on -5V, a gain 

R157 

7 

FIL 

of 100 yield s a 1V 

C195 

30K 

G100 

R283 

signal to t he ADC 

OSCON_6SC6R8M 

17 


5Vanalog 

6 

+1.8V_IN 

COMP1 

+VS 

3 

input. 

34 

C193 

-VS 

0.100 

INP3 

+ 

C191 

3.3nF NPO 

AD626AR 

C198 

100nF 

33pF NPO 

C118 

C221 

100nF 

OSCON_6SC6R8M 

L6 

C398 

+5V unfiltered 10 

L3 

PM54-100M 10uH B34 

C402 C188 

U49 

OSCON_6SC6R8M 

Vdd 

4.7uH 

C194 

1812K121R Bead C365 100nF 100nF 

+2.5V_IN + R389 

24 

OSCON_6SC10M 

1 2 47uF/6.3V Tan 


LX2 

1.8V 

8 

5 

Imon+5V 

R282 

316K 1% 

R159 C367 

+5V 1 

+IN OUT 

0.100 + 

22.1K 1% + 

C363 C197 

-IN 

+ 


3 

28 

100nF 

100nF 100nF 

4 

DBI FB2 

load on +5 V, a 

C403 

7 

FIL 

gain of 100 yields 

100nF 

R160 

G100 

33K 

R388 14.0K 1% 

a 400mV sig nal to 

5Vanalog 

6 

LBI th = 1.00 

+VS 

3 

the ADC in put. 

DBI th = 1 .235 

2 

-VS 

LBI 

21 R152 30K 

COMP2 

AD626AR 

R158 

C404 C201 

C116 

100K 1% 

33pF NPO 1.8nF 

100nF 

L1 

R413 R153 R154 R155 

L4 

PM54-100M 10uH B38 

U50 

Jumper Open Ckt10K 1% Open Ckt 

4.7uH 

C396 

1812K121R Bead C397 

C200 C192 

OUT1 

33 

OSCON_6SC10M 

1 2 47uF/6.3V Tan 100nF 100nF 


5 

LX3 

C399 

C400 

C401 

2.5V 

+3.3V_IN 

+IN OUT 

Imon+3.3V 

1 

29 

+ 

+ 

-IN 


OUT3 

100nF 

100nF 

100nF 

4 

FIL 

load on +3. 3V, a 

7 gain of 100 yields 

36 

G100 

LBO 

a 1`V sign al to 

R156 

2 5Vanalog 

6 


2 

30K 

+VS 

nPOR 

11 

3 

RSO 

30 

-VS 

22 

COMP3 

OUTOK 

AD626AR 

C406 

4 

C199 

10nF NPO 

C117 

nURESET 

16 

ON2 

33pF NPO 

100nF 

5 

MR 

7 R157, R152, R156 could be 

Alternet power down-re set option. 

PGM3 REF 

changed to 33K with a slight 

U51 

C405 reduction in regulat or response 

100nF 


5 

+2.5V_IN 

+IN OUT 

Imon+2.5V 

1 

C191, C404, C199 could be 

-IN 

Assuming a 2 00 mW 

changed to 47uF dep ending on 

4 

load on +2.5 V, a 

The MAX1702 co ntains 

MAX1702BEGX the ESR of the 0.1n F ceramic 

7 

FIL 

G100 gain of 100 y ields 

voltage monit oring 

capacitors on the ou tput nodes. 

a 400mV sign al to 

circuitry, and sta ged start 

5Vanalog 

6 


circuitry 

3 

+VS 

-VS 

GND 

GND 

PG3 

PG2 

PG1 

32 

23 

12 

OSCON_6SC6R8M 

C321 

5Vanalog 

+ 

+ 

-5V 

100nF 

100nF 

C322 

C332 

OSCON_6SC6R8M 

C427 

C333 

C331 

C329 

C327 

C325 

AD626AR 

OSCON_6SC6R8M OSCON_6SC6R8M OSCON_6SC6R8M OSCON_6SC6R8M OSCON_6SC6R8M 

C120 

1 100nF 

1 

Distribute widely around th e PC board to 

improve noise suppression. If noise 

performance is good enough, some of these 

parts may be deleted from the final design. 

The design might benefit b y additional 

bypassing on 3.3V. 

+ 

+ 

100nF 

100nF 

C324 

C334 

OSCON_6SC6R8M 

C339 

+ 

+ 

100nF 

100nF 

C326 

C336 

OSCON_6SC6R8M 

C337 

+ 

+ 

100nF 

100nF 

C328 

C338 

OSCON_6SC6R8M 

C335 

+ 

+ 

100nF 

100nF 

C330 

C340 

5Vanalog 

C119 

100nF 


+1.8V_IN 

JU7 

1 2 

1 2 

Jumper 

8 

1 

4 

7 

6 

3 

U45 

+IN 

-IN 

FIL 

G100 

+VS 

-VS 

AGND 

AGND 

AGND 

AGND 

AGND 

AD626AR 

OUT 

5 

Assuming a one 

Watt load on +1.8V, 

a gain of 10 yields 

a 200mV sig nal to 

the ADC input. 

Imon+1.8V 

Title 

Digital Optical Module Power Supply 


C 

 

A 

B 

C 

D 



E

A 

B 

C 

D 

E 

B41 

T-Section 

Filter/ 

TP54 

5Vanalog 

C225 

C395 

Impedance 

100nF 

Matching 

LI0805D121R 

1 

R293 R334 

2-Pin Header 

3.3V 

210 210 

U65 

100nF 

3 

L7 1uH L8 1uH 

+ 

1 1 2 1 2 

4 TOYOCOM_OSC 

C342 

4 

4 

- 

PM1008-1R0K PM1008-1R0K 

R232 

R304 

22pF NPO 

AD8005RT 

C306 

100 

150 

100pF NPO 

C344 

100nF 

C343 

10pF NPO 

R336 4.7K 

5 

2 

4.7K 

R183 

L7 and L8 must not be 

end-to-end or parallel. 

Mutual coupling must be 

avoided. 

C313 

100nF 

Do I need this sinusoidal 

(more-or-less) signal to feed 

into the ATWD input Maybe 

just square-wave is OK. Sin 

is easy to fit, though. 

C233 

100nF 

U58 

14 

C203 

VCC 

8 

OUT 

7 

GND 

100nF 

20.000 MHz Toyocom Oscillator 

XT-VCC 

C202 

100nF 

R138 

20 

5Vanalog 

3.3V 

1 2 

R167 

10K 1% 

There might be a 

faster or lower 

power comparator, 

but that would add 

another part to the 

BOM 

C316 

100nF 

3 3 

U86 

U5 MAX9013EUA R280 

2 

CLK 

R179 

2 

7 

7 

+ 1 

nCLK 

10K 1% 

3 

2.7K 

R272 

4.7K 

5Vanalog 

- 

8 

Latch 5 

FIN1017K8X 

C222 

cr0805 

R404 

100nF 

10K 1% 

1 

6 

8 

4 

5 

2 2 

1 1 

Title 

Digital Optical Module Crystal 


B 

 

A 

B 

C 

D 



E

Schematic - Glacier - Lawrence Berkeley National Laboratory

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