T04 mos small signal model_simone.pdf - bSpace

EECS 240 

Analog Integrated Circuits 

Topic 4: 

MOS Models for Analog Design 

Bernhard E. Boser and Ali M. Niknejad 

Department of Electrical Engineering and Computer Sciences 

EECS 240 Topic 4: MOS Models for Design 

© 2007 B. Boser & A. Niknejad

MOSFET Models for Design 

• SPICE (BSIM) 

– For verification 

– Device variations 

– Process design () 

• Hand analysis 

– Square law model (good for intuition only) 

– Small-signal model 

• Challenge 

– Complexity / accuracy tradeoff 

– How can we accurately design when large signal models 

suitable for hand analysis are off by 50% and more 



More Square Law Model 

• In saturation: 

• Familiar but inadequate for short channel devices 

do not use! 



µC ox 

• Square law: 

• Extracted values 

strong function of I D 

–Low I D 

weak inversion 

–Large I D 

mobility reduction 

• Do not use µC ox for 

design! 



Threshold Voltage V TH 

• Strong function of L 

• Use long channel for V TH 

matching 

• Process variations 

– Run-to-run ~100mV 

– How characterize 

– Slow/nominal/fast 

– Both worst-case & optimistic 

Good design insensitive to Vth, only depends on mismatch in 

Vth (can be

Device Parameters for Design 

• Focus on metrics that we can directly use in design 

• Region: moderate inversion / saturation 

– Most common region of operation in analog circuits 

– XTR behaves like transconductor: voltage controlled current 

source 

• Key design parameters 

– Large signal 

• Current I D power dissipation 

• Minimum V DS available signal swing 

– Small signal 

• Transconductance g m speed / voltage gain 

• Capacitances C GS , C GD , … speed 

• Output impedance r o voltage gain 



Low Frequency Model 

• A Taylor series expansion of small signal current 

gives (neglect higher order derivatives) 

• How do we determine the values of the derivatives 



Weak Inversion g m 

• In weak inversion we have bipolar behavior 

• Good model if transistor is actually used in 

weak inversion 



Transconductance 

weak 

inversion 

strong inversion 



Transconductance (cont) 

• The transconductance increases linearly with V gs – 

V T but only as the square root of I ds . Compare this to 

a BJT that has transconductance proportional to 

current. 

• In fact, we have very similar forms for g m 

• Since V dsat >> V t , the BJT has larger 

transconductance for equal current. 

• Why canʼt we make V dsat ~ V t 



Transconductor Efficiency 

• A good metric for a transistor is the transconductance 

normalized to the DC current. Since the power dissipation is 

determined by and large by the DC current, weʼd like to get the 

most “bang” for the “buck”. 

• From this perspective, the weak and moderate inversion region 

is the optimal place to operate. 



Efficiency g m /I D 

• High efficiency is 

good for low power 

• Higher g m /I D at low 

V GS 

• Approaches BJT for 

V GS < V TH 

g m /I C = 1/V t ~ 40 V -1 

• NMOS / PMOS 

about same 



Efficiency as a Design Parameter 

• If g m /I D is such a good metric, why not use it 

for design 

• We can always determine its precise value 

(from I D and g m ), independent of short 

channel effects and other complications. 

• The units (V -1 ) and physical interpretation are 

a little unusual, but we can easily fix this 



Efficiency g m /I D 

• Letʼs define 

e.g. V* = 200mV g m /I D = 10 V -1 

• Square-law devices: V* = V GS -V TH = V dsat 



Output Resistance r o 

Hopeless to model this with a simple equation 

(e.g. g ds = λ I D ) 



Open-loop Gain a v0 

• More useful than r o 

• Represents maximum attainable 

gain from a transistor 

• Simulation Notes: 

• Bias current i dc sets V* 

• Use feedback to find the correct 

V GS while sweeping V ds 

• Use relatively small gain (100) 

for fast DC convergence 



Gain, a v0 = g m r o 

L = 0.18µm 

• Strong tradeoff: 

a v0 versus V DS range 

• Create such plots for 

several device 

lengthʼ for design 

reference 



Long Channel Gain 

L = 0.35µm 

L a v0 

like long channel device 



Technology Trend 

Short channel devices suffer from reduced per transistor gain 



Transistor Gain Detail 

45.000 

33.775 

gm×ro 

22.550 

11.325 

0.100 

0.02 0.06 0.1 0.14 0.18 0.22 0.26 0.3 0.34 0.38 0.42 0.46 0.5 

VDS [V] 

For practical V DS the effect the “short-channel” gain penalty is less severe 

(remember: worst case V DS is what matters!) 



Saturation Voltage vs V* 

• Saturation voltage V sat 

– V DS for which channel pinches off at drain 

– Cannot be measured 

– Complex equations 

• V* = 2I D /g m 

– Measure (or simulate) easily 

– Complex equations 

• “Long channel” (square law) devices: 

– V GS – V TH = V dsat = V ov = V* 

– Significance: 

• Channel pinch-off 

• I D ~ V* 2 

• r o “large” for V DS > V* 

• C GS , C GD change 

• V* = 2 I D / g m 

• “Short channel” devices: 

– All interpretations of V* are approximations 

– Except V* = 2 I D / g m (but V* ≠ V dsat ) 



NMOS/PMOS Small-Signal 

AC Model 

gmb vbs 

Bulk usually connected to substrate for NMOS 



SPICE Charge Model 

• Charge conservation 

• MOSFET: 

– 4 terminals: S, G, D, B 

– 4 charges: Q S + Q G + Q D + Q B = 0 (3 free variables) 

– 3 independent voltages: V GS , V DS , V SB 

– 9 derivatives: C ij = dQ i / dV j , e.g. C G,GS ~ C GS 

– C ij != C ji 

Ref: HSPICE manual, “Introduction to Transcapacitance”, pp. 15:42, Metasoft, 1996. 



Small Signal Capacitances 

Weak inversion 

Strong inversion 

linear 

Strong inversion 

saturation 

C GS C ol C GC /2 + C ol 2/3 C GC + C ol 

C GD C ol C GC /2 + C ol C ol 

C GB C GC // C CB 0 0 

C SB C jSB C jsB + C CB /2 C jsB + 2/3 C CB 

C DB C jDB C jDB + C CB /2 C jDB 



MOS Capacitance Example 

W/L=100/0.5 

Cox=ε0εox/tox=15fF/µm 2 

Col=0.5fF/µm->Covlap=50fF 

Cgs,si=2/3CoxWL+Col=550fF 

Cgd,si=Covlap=50fF 

Cgs,triode=1/2CoxWL+Co=425fF 

Cgd,triode=1/2CoxWL+Co=425fF 

Cgs,wi=Covlap=50fF 

Cgd,wi=Covlap=50fF 

Inaccurate, residual Cgs left 



Layout 

HSPICE geo = 0 (default) 

HSPICE geo = 3 



Extrinsic MOS Capacitances 

• Source/drain diffusion junction capacitance: 

• Example: W/L = 100/0.5, V SB = V DB = 0V, L diff = 1µm 

AS = AD = 100µm 2 , PS = PD = 102µm 

C jn = 85fF C jswn = 50fF C bc = 58fF 

Strong Inversion – 

Saturation: C sb = 173fF C db = 135fF 

Linear region: C sb = 164fF C db = 164fF 



High Frequency Figures of Merit 

• Unity current-gain bandwidth 

(Long channel model, C gd =0) 

• For degenerate short channel device 



Efficiency g m /I D versus f T 

Speed-Efficiency 

Tradeoff 

NMOS > PMOS 



Weak Inversion Frequency Response 

• The gate channel capacitance capacitance in 

weak inversion ~0:Cgs ~ Cgsol 

• fT~25Id/Cgsol 

• Expression for channel capacitance and fT 

• I M is the maximum achievable current in weak 

inversion so the factor ( ) < 1 

Ref: Tsividis, Operation and Modeling of the MOS Transistor 



Device Scaling 

Short channel devices are significantly faster! 



Device Figure-of-Merit 

400.00 

300.05 

fT×gm/ID [GHz/V] 

200.10 

100.15 

0.20 

-0.1 -0.06-0.02 0.02 0.06 0.10.13 0.170.20.23 0.270.30.33 0.430000000000001 

VGS-VTH [V] 

Peak performance for low V GS -V TH (implies low V*) 



Design Example 

Example: Common-source amp 

a v0 > 70, f u = 100MHz for C L = 5pF 

• a v0 

 > 70    L =0.5µm 

   

• High gmeff: V* = 100mV 



Device Sizing 

• Pick L 

• Pick V* 

• Determine g m 

0.5µm 

100mV 

3.14mS 

• I D = 0.5 g m V* 157µA 

• W from graph 

(generate with SPICE) 

Current Density=0.8uA/square 

– Corresponds to W/ 

L=157/0.8=196.25 

– W=W/L*L=98um 

– Cgs=600fF,Cgd=50fF 

• Create such graphs for 

several device lengths for 

design reference 



Common Source Verification 

• Amplifier gain > 70 

• Amplifier unity gain frequency is “dead on” 

• Output range limited to 0.12 V – 1.2 V to maintain gain 

(about 1V swing, due to NMOS not limiting gain on high side) 



Common Source Verification 

Vmin=0.12V 

• Amplifier gain > 70 

• Amplifier unity gain frequency is “dead on” 

• Output range limited to 0.12 V – 1.2 V to maintain gain 

(about 1V swing, due to NMOS not limiting gain on high side) 



Small Signal Design Summary 

• Determine g m (from design objectives) 

• Pick L 

– Short channel high f T 

– Long channel high r o , a v0 , better matching 

• Pick V* = 2I D /g m based on qualitative interpretation of V* 

– Small V* large signal swing, high current efficiency 

– High V* high f T 

– Also affects noise (see later) 

• Determine I D (from g m and V*) 

• Determine W (SPICE / plot) this takes care of short channel effects, etc. 

• Accurate for short channel devices key for design 



Device Sizing Chart 

Generate these curves for a variety of Lʼs and device flavors 

(HW1)(NMOS, PMOS, thin oxide, thick oxide, different V TH ) 



Device Parameter Summary 

Device Parameter 

Circuit Implications 

V* • Current efficiency, g m /I D 

• Power dissipation (I D ) 

• Speed (g m ) 

• Cutoff frequency, f T phase margin, noise 

• Headroom, V DS,min 

L 

W 

• Cutoff frequency, f T phase margin, noise 

• Intrinsic transistor gain (a v0 ) 

• Obtain from L, I D (complicated equations!) 

• Self loading (C GS , C DB , …) 



Device Variations 

• Run-to-run parameter variations: 

– E.g. implant doses, layer thickness, dimensions 

– Affect V TH , µ, C ox , R, … 

– How model in SPICE 

• Nominal / slow / fast parameters (tt, ss, ff) 

– E.g. fast: low V TH , high µ, high C ox , low R 

– Combine with supply & temperature extremes 

– Pessimistic but numerically tractable 

improves chances for working Silicon

T04 mos small signal model_simone.pdf - bSpace

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