10 Gigabit to 1 Gigabit Ethernet Converter (XG2G) - Cadence

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10 Gigabit to 1 Gigabit Ethernet Converter (XG2G) ©2004-2011 Cadence Design Systems, Inc. All rights reserved Proprietary Notice In the U.S. and numerous other countries, Cadence and the Cadence logo are registered trademarks and Cadence Design Foundry is a trademark of Cadence Design Systems, Inc. All other products or services mentioned herein may be trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright owner. The product described in this document is subject to continuous developments and improvements and is supplied "AS IS". All warranties implied or expressed including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded. Cadence Design Foundry, Inc shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Cadence Design Foundry products are not authorized for use as critical components in life support devices or systems without the express written approval of an authorised officer of Cadence Design Foundry, Inc. As used herein: 1. Life support devices or systems are devices of systems that are (a) intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Document No: I-IPA01-0213-USR Rev 06, March 2011 © 2004-2011 Cadence Design Systems, Inc. Page ii
XG2G Technical Data Sheet Features • Converts between XGMII and GMII interfaces to allow a 10 Gig Ethernet MAC to operate in a gigabit environment. • Also converts between XGMII and MII interfaces to allow a 10 Gig Ethernet MAC to operate in a 10/100M environment. • Interfaces to demultiplexed IEEE 802.3 XGMII (uses 64 bit wide data sampled on single clock edge rather than 32 bit wide data sampled on both edges of the clock). • Interfaces to standard IEEE 802.3 GMII or IEEE 802.3 MII. • Supports 10, 100 and 1000 Megabit per second speeds of operation. • Also supports 100 Megabit per second SGMII operation (where every GMII data byte is repeated ten times). • Supports transport of 802.3az low power idle indication. Description The XG2G wrapper allows a 10 Gig MAC to operate at 10, 100 and 1000Mb/s data rates in addition to 10 Gb/s. The XG2G can operate in either GMII mode or MII mode. Using the XG2G in GMII mode a 10G Ethernet MAC, clocked at 15.625MHz, can be connected to a 1G Ethernet Physical Layer using GMII clocked at 125MHz. In MII mode connection can be made to a 10/100 PHY using MII. The XG2G performs all the conversions required to map XGMII signalling into GMII/MII signalling and vice versa. The XG2G performs error handling to ensure errors are detected and handled correctly. It also supports a 100Mb/s SGMII mode of operation where the 10G Ethernet MAC is clocked at 1.5625MHz. In this mode each byte on the 125MHz GMII interface is repeated ten times in accordance with the SGMII specification. This increases the number of symbols in each frame by a factor of ten. The XAUI CTC has been shown still to be effective in 100Mb/s mode with a 100 ppm difference between the recovered and local clock. Operation The XG2G operates autonomously. It does not require an external input to restart it in error conditions. The transmit path transfers the data (64 bits) from the MAC clock (tx_slow_clk) to the GMII/MII clock (tx_fast_clk). The data is then serialised (by byte in GMII mode or by a 4-bit nibble in MII mode) and mapped into the GMII/MII packet format (SOP converted to preamble and EOP converted to idle and gmii_tx_en and gmii_tx_er set accordingly). The XG2G also ensures a minimum Inter-Packet Gap (IPG) of 96 bits on the GMII/MII. This requires the buffering of data from the XGMII and a guaranteed average IPG on the XGMII of 12 symbols with a minimum IPG of 8 symbols. If the XGMII IPG does not meet these requirements then the XG2G transmit buffer will overflow and the packet in progress is terminated In GMII mode the ratio between the slow clocks and fast clock is 1:8 while in MII mode it is 1:16. In 100 Megabit per second SGMII mode the ratio is 1:80. The receive path takes the data from the 1G/100M Physical Interface and transforms it into XGMII formatted packets. Any packet which does not start with gmii_rxd == SFD (Start of Document No: I-IPA01-0213-USR Rev 06, March 2011 © 2004-2011 Cadence Design Systems, Inc. Page 3
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10 Gigabit to 1 Gigabit Ethernet Converter (XG2G) - Cadence

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