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10 Gigabit to 1 Gigabit Ethernet Converter (XG2G) - Cadence

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<strong>XG2G</strong> Technical Data Sheet<br />

Receive Datapath<br />

125MHz Receive Clock (GMII),<br />

or<br />

25MHz Receive Clock (MII)<br />

15.625MHz Receive Clock div 8<br />

(GMII), or<br />

1.5625MHz Receive Clock div 16<br />

(MII)<br />

Cyclical<br />

Ordering<br />

Data push<br />

control logic<br />

(every 8th clock<br />

cycle)<br />

Slow Clock<br />

sync genera<strong>to</strong>r<br />

7<br />

-3<br />

GMII or MII<br />

data stream<br />

Preamble reconstruction<br />

SOP/EOP<br />

Detection<br />

and<br />

conversion<br />

6<br />

5<br />

4<br />

3<br />

2<br />

1<br />

-2<br />

-1<br />

0<br />

-3<br />

-2<br />

-1<br />

Data<br />

ordering<br />

control<br />

logic<br />

SOP<br />

64 bit Data<br />

and<br />

8 bit Control<br />

XGMII Data<br />

Stream<br />

0<br />

0<br />

SOP<br />

idle<br />

change<br />

for<br />

reseting<br />

SOP<br />

position<br />

Samples<br />

Data<br />

every<br />

clock<br />

cycle<br />

Document No: I-IPA01-0213-USR Rev 06, March 2011<br />

© 2004-2011 <strong>Cadence</strong> Design Systems, Inc. Page 6

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