10 Gigabit to 1 Gigabit Ethernet Converter (XG2G) - Cadence

Technical 10 Gigabit Data to Sheet 1 Gigabit Ethernet
Converter (XG2G)
Technical Data Sheet
Part Number:
T-CS-ET-0023-100
Document Number: I-IPA01-0213-USR Rev 06
March 2011
i

10 Gigabit to 1 Gigabit Ethernet Converter (XG2G)
©2004-2011 Cadence Design Systems, Inc. All rights reserved
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Document No: I-IPA01-0213-USR Rev 06, March 2011
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XG2G Technical Data Sheet
Features
• Converts between XGMII and GMII interfaces to allow a 10 Gig Ethernet MAC to
operate in a gigabit environment.
• Also converts between XGMII and MII interfaces to allow a 10 Gig Ethernet MAC to
operate in a 10/100M environment.
• Interfaces to demultiplexed IEEE 802.3 XGMII (uses 64 bit wide data sampled on
single clock edge rather than 32 bit wide data sampled on both edges of the clock).
• Interfaces to standard IEEE 802.3 GMII or IEEE 802.3 MII.
• Supports 10, 100 and 1000 Megabit per second speeds of operation.
• Also supports 100 Megabit per second SGMII operation (where every GMII data byte
is repeated ten times).
• Supports transport of 802.3az low power idle indication.
Description
The XG2G wrapper allows a 10 Gig MAC to operate at 10, 100 and 1000Mb/s data rates in
addition to 10 Gb/s. The XG2G can operate in either GMII mode or MII mode. Using the
XG2G in GMII mode a 10G Ethernet MAC, clocked at 15.625MHz, can be connected to a 1G
Ethernet Physical Layer using GMII clocked at 125MHz. In MII mode connection can be
made to a 10/100 PHY using MII. The XG2G performs all the conversions required to map
XGMII signalling into GMII/MII signalling and vice versa. The XG2G performs error handling
to ensure errors are detected and handled correctly.
It also supports a 100Mb/s SGMII mode of operation where the 10G Ethernet MAC is
clocked at 1.5625MHz. In this mode each byte on the 125MHz GMII interface is repeated ten
times in accordance with the SGMII specification. This increases the number of symbols in
each frame by a factor of ten. The XAUI CTC has been shown still to be effective in 100Mb/s
mode with a 100 ppm difference between the recovered and local clock.
Operation
The XG2G operates autonomously. It does not require an external input to restart it in error
conditions.
The transmit path transfers the data (64 bits) from the MAC clock (tx_slow_clk) to the
GMII/MII clock (tx_fast_clk). The data is then serialised (by byte in GMII mode or by a 4-bit
nibble in MII mode) and mapped into the GMII/MII packet format (SOP converted to
preamble and EOP converted to idle and gmii_tx_en and gmii_tx_er set accordingly).
The XG2G also ensures a minimum Inter-Packet Gap (IPG) of 96 bits on the GMII/MII. This
requires the buffering of data from the XGMII and a guaranteed average IPG on the XGMII of
12 symbols with a minimum IPG of 8 symbols. If the XGMII IPG does not meet these
requirements then the XG2G transmit buffer will overflow and the packet in progress is
terminated
In GMII mode the ratio between the slow clocks and fast clock is 1:8 while in MII mode it is
1:16. In 100 Megabit per second SGMII mode the ratio is 1:80.
The receive path takes the data from the 1G/100M Physical Interface and transforms it into
XGMII formatted packets. Any packet which does not start with gmii_rxd == SFD (Start of
Document No: I-IPA01-0213-USR Rev 06, March 2011
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XG2G Technical Data Sheet
Frame Delimiter), gmii_rx_dv == 1 and gmii_rx_er == 0 is not transformed and the data is
dropped. The XG2G internally reconstructs the preamble and ensures that incoming
GMII/MII frames that suffer preamble erosion are not rejected by the receiving 10G MAC.
The reconstruction process prepends preamble symbols (0x55) onto frames that have short
preamble (it also strips any preamble in excess of seven bytes). The process is
non-destructive in GMII mode, so non-standard preamble is preserved.
In MII mode the XG2G performs nibble to byte (RX) and byte to nibble (TX) conversion and
re-uses the GMII data path logic in order to translate MII frames into XGMII and vice versa.
The GMII data path logic in this case is timed to every second fast clock, because it needs
1:8 clock ratio between the slow and the fast clock domain.
The nibble-byte and byte-nibble conversion logic is timed on every fast clock (16 times the
slow clock rate). This logic takes care of SFD recognition and alignment, which is necessary
because the number of nibbles (odd or even) forming the preamble is unknown. The
preamble (if any) in MII mode is effectively lost, and reconstructed fully along the GMII data
path logic within the XG2G.
The XG2G handles an excess nibble condition on the receive path in MII mode in the
following way. If the excess nibble is marked as error (gmii_rx_er is asserted high), the
XG2G rounds the nibble to a full octet and converts it to an error symbol on the XGMII. Thus
the MAC would be notified for a symbol error. If the excess nibble is not marked as error
(gmii_rx_er is not asserted and remains low) the XG2G would truncate the frame, essentially
discarding the excess nibble. The MAC would accept the frame only if its CRC is correct.
The XG2G transports 802.3az LPI indication. XGMII normal idle (any byte of xgmii_txd[63:0]
== 0x07 with the corresponding bit of xgmii_txc[7:0] == 1) is converted to GMII/MII idle
(gmii_txd

XG2G Technical Data Sheet
Block Diagram
Clock Domains
÷ 8 (GMII)
or
÷ 16 (MII)
tx_fast_clk 125MHz - GMII
25MHz - MII
10G MAC TX Path
xg2g
TX Slow
Phase Buffer
TX to
GMII
GMII to MII
(byte to nibble)
10G MAC RX Path
xg2g
RX Slow
Phase Buffer
GMII
to RX
MII to GMII
(nibble to byte,
SFD alignment,
Excess nibble
condition
handling)
÷ 8 (GMII)
or
÷ 16 (MII)
rx_fast_clk 125MHz - GMII
25MHz - MII
Transmit Datapath
15.625MHz Transmit Clock div 8
(GMII), or
1.5625MHz Transmit Clock div 16
(MII)
Slow Clock
sync generator
125MHz Transmit Clock (GMII), or
25MHz Transmit Clodk (MII)
Data pops
control logic
(every 8th
clock cycle)
buffer depth is 3
Cycle through data
and insert sufficient
IPG. As the IPG is
inserted a byte at a
time this is the
mode least likely to
cause buffer
problems
XGMII Data
Stream
64 bit Data
and
8 bit Control
Store only data
as IPG is
inserted later
Data pass through,
SOP/EOP translation,
or IPG Generator
GMII or MII
data stream
IPG counter to ensure
minimum IPG is always
provided
Document No: I-IPA01-0213-USR Rev 06, March 2011
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XG2G Technical Data Sheet
Receive Datapath
125MHz Receive Clock (GMII),
or
25MHz Receive Clock (MII)
15.625MHz Receive Clock div 8
(GMII), or
1.5625MHz Receive Clock div 16
(MII)
Cyclical
Ordering
Data push
control logic
(every 8th clock
cycle)
Slow Clock
sync generator
7
-3
GMII or MII
data stream
Preamble reconstruction
SOP/EOP
Detection
and
conversion
6
5
4
3
2
1
-2
-1
0
-3
-2
-1
Data
ordering
control
logic
SOP
64 bit Data
and
8 bit Control
XGMII Data
Stream
0
0
SOP
idle
change
for
reseting
SOP
position
Samples
Data
every
clock
cycle
Document No: I-IPA01-0213-USR Rev 06, March 2011
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XG2G Technical Data Sheet
Signal Interfaces
The XG2G includes the following signal interfaces:
• XG2G specific clock and reset signals
• XGMII (demultiplexed)
• GMII
• GMII/MII mode select
• 100 Megabit SGMII mode select
Clock Domains
The XG2G contains 4 clock domains. Frequency is shown for GMII/MII mode of operation.
1) Low Speed Transmit Domain tx_slow_clk (15.625MHz 1.5625MHz 0.15625MHz)
2) High Speed transmit Domain tx_fast_clk (125MHz 25MHz 2.5MHz)
3) Low Speed Receive Domain rx_slow_clk (15.625MHz 1.5625MHz 0.15625MHz)
4) High Speed Receive Domain rx_fast_clk (125MHz 25MHz 2.5MHz)
Clock domain (1) must be derived from clock domain (2): via division by 8 (GMII) or 16 (MII).
Clock domain (3) must be derived from clock domain (4): via division by 8 (GMII) or 16 (MII).
Signal Name Direction Function
tx_fast_clk Input High speed GMII/MII transmit clock
(125MHz/25MHz/2.5MHz)
txf_rst_n Input Active low tx_fast_clk domain reset. This signal should
be asserted low asynchronously, and deasserted high
synchronously with tx_fast_clk.
tx_slow_clk Input Slow speed XGMII transmit clock (15.625MHz/1.5625MHz/
0.15625MHz)
txs_rst_n Input Active low tx_slow_clk domain reset. This signal should
be asserted low asynchronously, and deasserted high
synchronously with tx_slow_clk.
rx_fast_clk Input High speed GMII/MII receive clock (125MHz/25MHz/2.5MHz)
rxf_rst_n Input Active low rx_fast_clk domain reset. This signal should
be asserted low asynchronously, and deasserted high
synchronously with rx_fast_clk.
rx_slow_clk Input Slow speed XGMII receive clock (15.625MHz/1.5625MHz/ /
0.15625MHz)
rxs_rst_n Input Active low rx_slow_clk domain reset. This signal should
be asserted low asynchronously, and deasserted high
synchronously with rx_slow_clk.
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XG2G Technical Data Sheet
XGMII (demultiplexed) Signals
The XGMII is non-DDR so 64 bits of data and 8 bits of control are transferred on the rising
edge of the XGMII clock.
Signal Name Direction Function
xgmii_txd[63:0] Input 8 bytes of data to be transmitted over the GMII
xgmii_txc[7:0] Input 8 control bits (one per byte of xgmii_txd) defining data or
control information for the remainder
xgmii_rxd[63:0] Output 8 bytes of data received from the GMII
xgmii_rxc[7:0] Output 8 control bits (one per byte of xgmii_rxd) defining data or
control information for the remainder
GMII/MII Signals
The GMII meets the requirements set in IEEE 802.3. In MII mode only bits 3 downto 0 are
used from the data buses, gmii_rxd[7:4] should not be left unconnected however.
Signal Name Direction Function
gmii_txd[7:0] Output Data to be transmitted by the physical layer
gmii_tx_en Output Flag indicating valid data on gmii_txd.
gmii_tx_er Output Flag indicating an error on gmii_txd
gmii_rxd[7:0] Input Data received from the physical layer
gmii_rx_dv Input Flag indicating valid data on gmii_rxd
gmii_rx_er Input Flag indicating an error on gmii_rxd
GMII/MII Mode Select Signal
This signal sets the mode of operation of the XG2G, i.e. GMII or MII. It is considered a static
control signal and should not be changed during normal operation of the device. The XG2G
relies on a particular clock ratio between the fast and slow clock domains. In GMII mode this
ratio must be 8, whereas in MII mode this ratio must be 16.
Signal Name Direction Function
mii_mode Input 0 – GMII mode of operation; 1 – MII mode of operation
SGMII 100 Megabit Mode Select Signal
This signal sets the 100 Mbps SGMII mode of operation. It is considered a static control
signal and should not be changed during normal operation of the device. The XG2G relies on
a particular clock ratio between the fast and slow clock domains. In SGMII 100M mode this
ratio must be 80. The mii_mode input must be low when sgmii_mode_100m is asserted.
When SGMII 100M mode is selected the GMII clocks run at 125MHz and the XGMII clocks at
1.5625MHz. Each GMII data byte is repeated ten times resulting in an effective frame length
increase of a factor of ten. This puts an extra burden on any clock tolerance correction
circuitry in the receive path.
Signal Name Direction Function
sgmii_mode_100m Input 1 – 100 Meg SGMII operation; 0 – normal operation
Document No: I-IPA01-0213-USR Rev 06, March 2011
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XG2G Technical Data Sheet
Programming Interface
This device does not require programming.
Physical Estimates
Gate count
9,600 Gates – NAND2 equivalents
FF count 880
Pin count 175
Power consumption 1mW typical for TSMC 0.13G
Verification
All our IP modules are verified to one of the following levels:
• Gold IP has been to target silicon.
• Silver IP has been to silicon in FPGA.
• Bronze IP has been verified in simulation with logical timing closure.
• In development IP has not yet been verified.
Please contact the IPGallery (ipgallery@cadence.com) for the latest verification
information.
Deliverables
The full IP package comes complete with:
• Verilog HDL
• Cadence RTL Compiler synthesis scripts with SDC constraints
• Verilog testbench
• XG2G User’s Guide with IP integration and synthesis instructions.
Document No: I-IPA01-0213-USR Rev 06, March 2011
© 2004-2011 Cadence Design Systems, Inc. Page 9