Harnessing inductance for top-down RF IC design

Harnessing inductance for top-down RF IC design
Sotiris Bantas, Helic S.A. s.bantas@helic.com
Inductance challenges
The design of modern RF ICs depends a lot on inductance, either exploiting it in the form of spiral inductors and
transformers, or avoiding it as a parasitic effect. Accurate modeling and efficient top-down design are needed for
harnessing inductance and putting it to good use in the chip. To effectively address the inductance-related
challenges, a top-down methodology should have the following merits:
• Modeling speed: A capability for rapidly and accurately modeling inductance and mutual inductance in its actual
on-chip context means the designer can try out different arrangements, re-simulate and optimize RF circuitry in
short cycles. On the other hand, resorting to generic electromagnetic (EM) solvers or exhaustive RLC extraction
usually leads to extremely long modeling times and/or gigantic netlist sizes, rendering iterations cumbersome and
inefficient.
• Flow integration: Another drawback to using generic EM solvers with little or no IC design flow integration, is
that you end up manipulating layout for the purposes of exporting to the EM tool, and then manually annotating
results from EM simulation to your circuit testbenches. Clearly, this approach is not only time -consuming, it’s also
error-prone. Ideally, inductance modeling should be available within the circuit schematic and simulation
environment. Additionally, the flow should offer a capability to extract inductance and mutual inductance models
from the layout in a seamless manner, along with other circuit devices and RC parasitics, with no manual
annotation from the designer.
• Full-chip scalability: Modern silicon RF transceivers are
rather complex in terms of component count, employing
several inductors and a multitude of on-chip wires that
exhibit parasitic inductance and mutual inductance. Global
extraction of inductance at the chip-level means you can
verify your transceiver as a system, to simulate effects such
as VCO-to-LNA feedthrough and other RF phenomena.
For these purposes, the inductance modeler should provide
good scalability, in other words be able to produce models
with reasonable speed, that simulate well in circuit
simulators.
• Real-estate : Planar spiral inductors are area-consuming,
and a large portion of their footprint is plain white space.
Additionally, the common practice has been to separate
them physically on chip, by several tens of µm, to mitigate
mutual inductance effects. This practice leads to excessive
real estate and increases the production cost of the RF IC,
while it does little to reduce risks since mutual inductances
are still there and cannot be fully avoided. Layout-correct,
distributed mutual inductance modeling empowers the
designer to achieve more compact layouts (Fig. 1), while
predicting mutual inductance consequences on circuit
performance.
• Top-down design: Efficient inductor design should follow
the proven top-down IC design flow (Fig. 2). Spiral
inductors are introduced by means of a synthesis engine
that produces inductor models according to user
Fig. 1: Area-efficient layout with spirals
System Design &
Modeling
Circuit Design
Circuit
Simulation
Layout
LVS
Extraction
Signoff
• Synthesis of spiral
inductors
• Modeling of spiral
inductors
• Automated inductor
layout (Pcells)
• LVS for inductive
components
• Automatic extraction
of inductance
Fig. 2: Top-down flow for inductor design

specifications, optimizing metrics such as quality factor, area and placement of leads. Generated inductors are
encapsulated in Pcell definitions, so that they may be easily manipulated by the designer by editing geometry
parameters. Pcells can de designed to be always DRC-clean, while complying with foundry-specific design-formanufacturability
rules (e.g. metal slotting, current carrying limits). When placed and routed in a layout, all
generated inductor instances should pass LVS. For this purpose, special rules should be added to the verification
deck, so that inductor connectivity and geometry can be correctly identified from the layout; otherwise, all spirals
would be treated as plain metal shorts. Finally, at the chip extraction phase inductor models should be
automatically incorporated in the extracted netlist, including all applicable mutual inductance; by definition, this
process is non-hierarchical and a special interface should be employed that achieves this in conjunction with the
extraction - verification engine.
Top-down inductance design with VeloceRF
VeloceRF is a Virtuoso®-based toolset [1] that introduces rapid inductance modeling, spiral inductor synthesis
and verification for top-down RF IC design flows. It features a spiral inductor synthesis engine, Spiral Wizard
(Fig. 3a), a variety of spiral inductor Pcells (Fig. 3b), and integrated tools for inductor characterization (Fig. 4),
netlist extraction from layout (including mutual inductances), modeling of arbitrary metal lines and LVS with
inductor Pcells. Additionally, it provides an Assura interface so that designed inductors can be extracted with full
connectivity in a unified extracted view along with other layout devices and parasitics.
The VeloceRF flow collectively addresses the challenges set forth previously, by enabling seamless, top-down
design of integrated inductors. Its rapid modeling engine produces distributed RLCk netlists and has adequate
capacity to handle large-scale designs employing tens of inductors and several interconnect lines.
(a)
(b)
Fig. 3: VeloceRF interface in Virtuoso

Fig. 4: Inductor characterization
Showcase: Low-Noise Amplifier (LNA) design
An LNA design testcase is presented. The circuit is tuned in the 2.4-2.5 GHz band and features differential
input/output, inductive source degeneration, LC-tank load and LC impedance matching at the input and output
terminals (Fig. 5). Inductor layout and placement is shown in Fig. 6. Input-matching inductors are optimized for Q
with VeloceRF’s Spiral Wizard, to achieve a low noise figure. Source degeneration needs low-value inductors, so
these are laid out as ‘half-turn’ spirals. Drain load inductor Pcells were trimmed by the designer to an orthogonal
shape, to achieve the required value and center the amplifier’s gain at the desired frequency. Additionally, the
chosen placement minimizes ‘white space’ and achieves a very compact layout (Fig. 7). The final layout was
extracted using VeloceRF’s Assura interface, producing an extracted view with encapsulated VeloceRF model for
the inductors. The results from post-layout simulation are given in Fig. 8. The VeloceRF modeler takes a about ten
seconds to produce the model for all inductors in this layout (including mutual inductances), on a standard P3 Linux
workstation.

V DD
V DD
Bias
L D
OUT P
M 2P
IN P
M 1P
L IN
L S
Source degeneration
paths
Input matching
inductors
Drain Loads/Output
matching inductors
L IN
L S
IN N
M 1N
M 2N
OUT N
Bias
L D
V DD
V DD
Fig. 5: LNA simplified schematic
Fig. 6: Inductor placement
Benefits – discussion
The top-down methodology implemented in VeloceRF provides all the necessary tools for designing standard and
custom spiral inductors, and quickly and efficiently transitioning from schematic to final RF IC layout. The
inductance modeling engine is fast, enabling rapid design iterations for achieving an optimal design. Since mutual
inductance modeling is available throughout the flow, compact layouts can be achieved that minimize silicon area
without compromising design robustness. At the signoff stage of the design, the interface seamlessly encapsulates
inductor models to the extracted view, so that the full circuit can be verified for inductance and mutual inductance
rapidly and accurately.
References
[1] Sotiris Bantas, Yorgos Koutsoyannopoulos and Apostolos Liapis, “An Inductance Modeling Flow Seamlessly Integrated in
the RF IC Design Chain,” in Proc. 2004 Design Automation and Test Europe conference (DATE ’04), Paris, Feb. 2004.

Fig. 7: The finalized layout of the LNA
Fig. 8: Post-layout (extracted view) S-parameter response of the LNA