High Performance Reconfigurable Computing

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Fine-grain Reconfigurable Hardware Devices: FPGAs

Conventional FPGA Tile

K-LUT (typical k=4)

w/ optional

output Flip-Flop

~ 75% of FPGA area

4-LUT

~ 25% of FPGA area

Or configurable Logic Block (CLB)

#12 lec # 9

Fall 2010

10-20-2010

RIT Computer Engineering Cluster SSH Clients

EECC 756 - Spring 2001 Homework Assignment #2, Due May 10

Evolution of the NVIDIA GPU Architecture

FPGAs The FPGA, or Field Programmable Gate Array, lies at the heart of most reconfigurable computing designs An FPGA’s function is determined long after it is manufactured Programmed using a variant of C, or an HDL (often VHDL or Verilog)

Fine-grain Reconfigurable Hardware Devices: FPGAs Conventional FPGA Tile K-LUT (typical k=4) w/ optional output Flip-Flop ~ 75% of FPGA area 4-LUT ~ 25% of FPGA area Or configurable Logic Block (CLB) #12 lec # 9 Fall 2010 10-20-2010

Page 1 and 2: Anthony Agresta & Jeremy Coon
Page 3 and 4: Computing System Element Choices Pr
Page 5 and 6: Intro: von Neumann Architecture Si
Page 7 and 8: Spatial vs. Temporal Computing Spat
Page 9: Approaches for HPRC • “Hybrid-c
Page 13 and 14: Applications of FPGAs and HPRC Pro
Page 15 and 16: Sample Configurable Computing Appli
Page 17: Conclusions Modern processors have

High Performance Reconfigurable Computing

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