High Performance Reconfigurable Computing

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Conclusions

In the future, mainstream computers

might contain a programmable FPGA

coprocessor

This could allow applications to “re-wire”

a part of your computer in order to

perform required number crunching

faster than with a traditional CPU

RIT Computer Engineering Cluster SSH Clients

EECC 756 - Spring 2001 Homework Assignment #2, Due May 10

Evolution of the NVIDIA GPU Architecture

Conclusions In the future, mainstream computers might contain a programmable FPGA coprocessor This could allow applications to “re-wire” a part of your computer in order to perform required number crunching faster than with a traditional CPU

Conclusions Modern processors have hit a physical clock-speed barrier Best way to continue performance gains as dictated by Moore’s Law is increased parallelism FPGAs and RC offer a good method to take advantage of data-level parallelism and increased transistor count.

Page 1 and 2: Anthony Agresta & Jeremy Coon
Page 3 and 4: Computing System Element Choices Pr
Page 5 and 6: Intro: von Neumann Architecture Si
Page 7 and 8: Spatial vs. Temporal Computing Spat
Page 9 and 10: Approaches for HPRC • “Hybrid-c
Page 11 and 12: Fine-grain Reconfigurable Hardware
Page 13 and 14: Applications of FPGAs and HPRC Pro
Page 15: Sample Configurable Computing Appli

High Performance Reconfigurable Computing

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