CX20662 App Note 1 - PCB Layout Guidelines APN ... - Codico

CX20662 PCB Layout Guidelines
Revision 1.0
November 24, 2008
These layout guidelines reference component and net names from the Conexant CX-9Z-NR0340-00-1.X reference
design. It is recommended to have the CX-9Z-NR0340-00-1.X schematic and G600Z-NR0340-00-1.0 Allegro
layout files available while reading this document.
Component Placement
CX20662 Analog
Component placement guidelines are listed below in order of priority. Analog signals have priority over digital
signals. The CX20662 device should be oriented such that the analog signals are as short as possible. Analog and
digital sections should be separated as much as possible.
1. Place microphone circuit (J12, R406, C401, R42, C218) as close to U4 as possible.
2. Place speaker circuit (J10, J405, C25, C34, C36, C200-C201, R200-R201, L20-L21, and R10, R11) as
close to U4 as possible.
3. Place headphone circuit (J404, C49, R44, R432, C216) as close to U4 as possible.
4. Place volume control circuit (R29, R54, C27, C31) close to U4, pin 14.
CX20662 Digital
Component placement guidelines are listed below in order of priority.
1. Current sense resistor, R428, must be placed as close as possible to U4. It is critical that the traces
from R428 to U4 be as short and wide as possible to minimize trace impedance. R428 is used to sense
an overcurrent event and large trace impedances will affect the overcurrent trigger point.
2. Place crystal circuit as close to U4, pins 6 and 7 as possible.
3. Place decoupling caps (C8-C14, C21) as close to the appropriate pins on U4 as possible.
4. Place remaining digital components in such a way as to minimize trace lengths.
DAA
The DAA circuit is shown on page 4 of the schematic. All components to the right of T1 need to be placed inside a
3mm isolation barrier. See G600Z-NR0340-00-1.0 Allegro layout file for an example. Components to the left of T1
should be placed near T1.
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Critical Trace Widths, Lengths, and Clearances
Analog
The following signals should be routed as differential pairs and shielded from other signals by GND. No GND
between the differential pair. Trace width shall be 20 mils, spacing between differential pair signals shall be 10
mils, and spacing to AGND shield shall be 15 mils. Trace lengths shall be as short as possible. These signals are
the most critical in this design.
• SPK+/-, SPK1+/-, SPK2+/-
The following signals should be shielded from other signals by GND. Trace width shall be 20 mils and spacing to
AGND shield shall be 10 mils. Trace lengths shall be as short as possible. These signals are the most critical in this
design.
• MIC_MONO, MIC_MONO2 and MICBIAS
• HP_MONO, HP_MONO2, HP_MONO3
Analog power traces shall be routed as 25-mil wide traces. The analog power nets are listed below.
• +5V_CLASSD
• +3.3VA
• +1.65_VREF
• +2.5_VREFD
Digital
Crystal traces should be 12 mils wide with 12 mil spacing.
Digital power traces shall be routed as 25-mil wide traces. The digital power nets are listed below.
DAA
• +5V
• +5V_REG
• BRICK_IN
• +1.8V_VCORE
• +3.3VD
Traces from J5 to RV1 should be 25 mils thick with 25 mil spacing.
All other DAA traces should be 15 mils thick with 20 mil spacing.
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Power and Ground
There shall be a single ground plane on the board. Try to route most of the signals on layer 1 so that layer 2 can be a
solid ground plane.
Power traces shall be routed as 25-mil wide traces.
Silkscreen
All component reference designators need to be shown in silkscreen. Avoid placing silkscreen on top of vias. It is
recommended to also label the following:
Label SW34: Volume Down
Label SW36: Volume Up
Label SW29: Mic Mute
Label SW35: Spkr Mute
Label J14: UART
Label JP3: NVCLK
Label JP4: NVDATA
Label D2: Power LED
Label D6: Mic Mute LED
Label 17: Spkr Mute LED
Label J10, pin 1: Spkr +
Label J10, pin 2: Spkr –
Label J12, pin 1: GND
Label J12, pin 2: MIC
Label J405: Mono Speaker
Label J404: Headset Jack
Label R29: Analog Volume
Label JP8: Headphone Sense
Label JP9/SW1: Speakerphone Enable
Label JP5/SW2: OFF-HOOK
Label JP3/JP4: DC Loop
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Test Points and Manufacturing Rules
The table below summarizes typical manufacturing recommendations.
Parameter
Value
Test Point Shape
Square
Test Point Minimum size/diameter 35
Minimum spacing between TPs (center-center) 75
Minimum spacing between TP and component pin (center-center) 75
Minimum spacing between TP and board edge (edge-edge) 100
Smallest allowed component size 0603
Minimum trace clearance from edge of board (edge-edge) 40
Minimum thru-hole component body clearance from edge of board
40
(edge-edge)
Minimum surface mount component and thru-hole pad clearance from 115
edge of board (edge-edge)
Minimum spacing between via and pad 8
Minimum spacing between any 2 components (edge-edge) 15
Note 1: All dimensions in mils.
Note 2: All test points should be placed on one side of the board. 100% test point coverage desired.
Fab Notes
See Conexant G600Z-NR0340-00 Allegro .BRD file for fab notes example.
Fiducial Marks
Place 3 fiducial marks on each layer where components are placed.
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