Computer Architecture and Organization Chapter 7 â Memory - IIUSA

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7-36 Chapter 7 - Memory Multi-level Cache Memory (Cont’) H 2 is the ratio of the number of times the accessed word is in the L2 cache to the number of times the L2 cache is accessed, and so: The effective access time is then: = 5.23 ns per access Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
7-37 Chapter 7 - Memory Neat Little LRU Algorithm • A sequence is shown for the Neat Little LRU Algorithm for a cache with four slots. Main memory blocks are accessed in the sequence: 0, 2, 3, 1, 5, 4. Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Computer Architecture and Organization Chapter 7 â Memory - IIUSA