Computer Architecture and Organization Chapter 7 – Memory - IIUSA

7-38 Chapter 7 - Memory
Cache Coherency
• The goal of cache coherence is to ensure that every cache sees the
same value for a referenced location, which means making sure that
any shared operand that is changed is updated throughout the system.
• This brings us to the issue of false sharing, which reduces cache
performance when two operands that are not shared between
processes share the same cache line. The situation is shown below.
The problem is that each process will invalidate the other’s cache line
when writing data without a real need, unless the compiler prevents this.
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring