2004 Issue 3 - Raytheon

High-Performance
Processing
now comes in a tiny
little package
Raytheon has been developing and
deploying systems to meet critical U.S.
Government needs for decades. Many of
these systems support stringent timelines
and require extremely high-performance
processing. The underlying technologies
that support these systems have evolved
over the years, and Raytheon has adapted
to the changing environment to take
advantage of these technologies.
An example that can illustrate the dramatic
shift in the underlying technology base is a
product line in Intelligence and Information
Systems (IIS) that has been building signal
processing systems since the late ‘60s.
These systems are ground-based and
deployed in standard data center environments.
Because of this, they can easily leverage
emerging commercial technologies.
In the early ‘80s, these systems proposed
using digital signal processing techniques
to achieve significant performance
improvements, but the required processing
was more than anyone had ever deployed.
Back then, more than 16 fully configured
Cray computers would have been required
(see Figure 1). Based upon early IRAD prototypes,
Raytheon set out to develop a
cost-effective solution based on custom
hardware designs and Application Specific
Integrated Circuit (ASICs).
Figure 1. First generation processor was a custom
hardware solution employing 24" x 24" boards.
First Generation Processor
Processing 13 GFLOPS RAM 1536 MB
Circuit Cards 227 Power 48 kW
Racks 4 FLOPS in HW 95%
ASIC Types 14 FLOPS in SW 5%
As illustrated in the table above, the performance
may seem trivial compared with
today’s systems, but it was a very challenging
project for its time. It provided critical
strategic information to Raytheon customers
and was in operation until 2003.
Figure 2. Second generation processor used COTS
supercomputer technology.
With DoD demanding increased capacity,
Operation Desert Shield and Desert Storm
showed the importance of this system and,
in response to a congressional mandate,
Raytheon was asked to double the capacity.
Challenges, as well as opportunities,
began to appear a decade after the first
system was built. Component obsolescence
made rebuilding an identical copy unrealistic,
but Moore’s law had made massively
parallel Commercial Off The Shelf (COTS)
computers feasible. Raytheon had been
prototyping algorithms on these machines
and was ready to meet the challenge.
Raytheon purchased one of the first Cray
T3Es, similar to the one shown in Figure 2.
A liquid cooled machine housed 160 central
processing units (CPUs), and this allsoftware
version of the system produced
identical output to the hardware system. It
was delivered on schedule and provided
the increased capacity needed to support
the war fighter. It was taken out of operation
last year at the same time the original
system was de-commissioned.
YESTERDAY…TODAY…TOMORROW
What replaced these systems was made
possible by the inevitable march of CPU
technology. Now, 20 years after the
original contract was signed, processing
capacity of a single CPU chip has increased
more than 8,000 times. This means that
a quad-CPU system with a field programmable
gate array (FPGA) accelerated
peripheral component interface (PCI) card
can do the job. Systems, similar to the Sun
V440 (see Figure 3) have been delivered
and continue to be deployed to meet
increasing demands.
Figure 3. Today’s processor uses inexpensive entry
level servers with embedded FPGA cards.
The future promises dramatic performance
increases. Analog Optical Signal Processing
(AOSP), a DARPA program, illustrates one
possibility. Using optical signal processing,
AOSP hopes to provide 2,500 times the
performance of the original system in a
package the size of a VHS cassette.
Again, Raytheon continues to explore new
technologies to bring down the cost of
these systems which, in turn, allows an
exponential rise in mission effectiveness
over time. •
Duncan Crawford
Duncan_L_Crawford@raytheon.com
2004 ISSUE 3 15
PROCESSING