ACHIEVING MISSION ASSURANCE - Raytheon

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onTechnology Aircraft Self-Protection: Defeating Infrared-Guided Missiles with Lasers Raytheon Missile Systems in Tucson, Ariz., is leading a multi-business team to develop the Scorpion Aircraft Self-Protection system for U.S. Navy and U.S. Air Force customers. The Scorpion system is being designed to autonomously detect the launch and threatening flight of an infrared-guided missile toward the aircraft and then point a modulated laser beam into the seeker of the threat missile, causing it to sharply veer off course. Figure 1 illustrates one-half of the system as it would be installed on the AH-1Z Cobra Assault helicopter. There would be an identical pod on the starboard wing. Poised to Compete in the Market The projected market for self-protection systems in both military and commercial aircraft is in the billions of dollars over the next two decades. Although there are wellestablished vendors currently in the market, Raytheon can be highly competitive since the Scorpion system is based on components already in production for other uses. For instance, the component that points the jam laser beam at the threat missile is a slightly modified AIM-9X sensor, and the component that senses the incoming threat is already flying on F-16 fighter aircraft. The Raytheon system, because of the AIM-9X heritage, will also be much lighter, much less expensive and much more reliable than the competition’s systems. Leading-Edge Technology Figure 1. The AH-1Z Cobra Assault helicopter with the conceptual Scorpion Aircraft Self-Protection System Processor Figure 2 illustrates the various components of an individual Scorpion pod. The function of the two missile-warning sensors is to detect the radiation emitted from the threat missile and provide a pointing direction from the aircraft to the threat. These sensors, built by Raytheon Electronic Warfare Systems, use two-color, mid-infrared focal planes from Raytheon Vision Systems. Onecolor versions of this sensor are currently in production in Goleta, Calif. The images produced by the missile-warning sensors are processed in the processor using missile-warning algorithms from the Naval Research Laboratory. The processor is directly evolved from the AIM-9X Electronics unit, where several cards will be modified and some additional processor cards will be added. E O / L A S E R S Aft missile warning sensor Forward missile warning sensor The pointer has two major functions: (1) to determine the validity of the threat, and (2) to direct a laser beam (co-aligned with the pointer line-of-sight) toward the threat missile. The pointer is a derivative of the AIM-9X sensor, where an additional small telescope has been added next to the existing receive telescope. The laser will be a two-band, mid-infrared, passively-cooled, semiconductor laser built for Raytheon by Aculight in Bothel, Wash. The pod, which holds the components and allows attachment and interface to the aircraft, is being designed and built by Raytheon Technical Services Company in Indianapolis, Ind. Demonstration Plans The Scorpion program is currently executing two contracts (one each for the Navy and Air Force), with a combined value of $14 million. After product development, the plan is to demonstrate the system in the summer of 2006 — first in the Scorpion laboratory and then at the Raytheon Missile Systems outdoor laser range. Follow-on funding is expected to demonstrate the system on a helicopter later in 2006. James Mills jpmills@raytheon.com 22 2006 ISSUE 1 RAYTHEON TECHNOLOGY TODAY YESTERDAY…TODAY…TOMORROW Laser Cryo Engine Figure 2. The components inside the two identical wing-mounted pods Pointer
onTechnology IBM Cell Processor Paves Way for New Multi-threaded Processors An observation was made in 1965 by Gordon Moore, co-founder of Intel, stating that the number of transistors per square inch on an integrated circuit has doubled every year since they were invented. Moore predicted that this trend would continue for the foreseeable future. He was right ... to a point. Instead of doubling every year, the density has doubled every 18 months; this has become the current definition of Moore’s Law. Now the issue that remains is how to effectively utilize all these transistors. Increase in Real Performance Lagging Unfortunately, the increase in real performance is not commensurate with each new device generation. Data indicates that only 40 percent improvement in performance has occurred with each doubling of transistors. This is primarily due to the push to improve single thread performance. Adding architectural complexity to enhance the instruction level parallelism (ILP) — and ultimately overall performance — is hindering the effectiveness of these transistors. Complexity such as dynamic execution (rescheduling a serial stream of instructions in real time so they can execute in parallel), complex branch prediction logic, out-oforder execution (to better utilize processing resources) and large caches are common techniques used in many state-of-theindustry components today. New Breed of Processors A new breed of processors inspired by the IBM Cell processor is changing this trend. The fundamental approach of the Cell processor’s design sacrifices single threaded performance optimizations for additional hardware resources that perform parallel thread computations. Optimizing for thread level parallelism (TLP) rather than ILP represents a significant change in architecture. A critical examination of Cell processor implementation — and therefore TLP optimization — has determined that a much more efficient use of transistors for certain applications can be achieved. The new Cell processor, which is a collaborative effort among IBM, Sony and Toshiba, has been designed primarily for the video game market and will first appear in Sony PlayStation 3 in spring 2006. It’s expected to provide an order of magnitude of computing power far beyond what is currently achievable with today’s processors. While optimizing for TLP works wonders for videorendering applications, it’s also an efficient architecture for real-time embedded sensor processing and many of Raytheon’s system applications. Pursuing System Performance Improvements Multiple teams across Raytheon conducted a critical and detailed examination of the Cell processor during 2005. They determined that significant system performance improvements can be realized. For example, radar modes that were once only dreamed of by system analyst and waveform designers can now be implemented in an embedded real-time airborne application. The Cell processor consists of nine processing cores and support resources: One PowerPC Processing Element (PPE) Eight Synergistic Processing Element (SPE) 512K bytes L2 Cache YESTERDAY…TODAY…TOMORROW PROCESSING Figure 1. A cell processor silicon design and layout of the processing resource Element Interconnect Bus (EIB) Shared Memory Interface Controller (MIC) FlexIO interface In essence, each SPE is an independent processing core connected directly to 256 KB of private memory. The PPE is a dual-threaded PowerPC processor connected to the SPEs through the extremely high bandwidth EIB. The PPE and SPE processing elements access system memory through the MIC, which is connected to two independent channels of Rambus XDR memory, providing 25 GB/s of memory bandwidth. The connection to I/O is done through the FlexIO interface and a Rambus-style interface. Together they provide 35 GB/s of raw outbound bandwidth and 25 GB/s of raw inbound bandwidth, for a total I/O bandwidth of 60 GB/s. IBM has announced that the first implementation of the Cell processor has been tested and can operate at frequencies above 4 GHz. At an operating frequency of 4 GHz, the Cell processor is capable of achieving a peak throughput rate of 256 GFlops from the eight SPEs, not including the PPE’s contribution from its floating point and vector units. For more information on the Cell processor and Raytheon’s application, please contact Steve Kirsch (skirsch@raytheon.com), Joel Mellema (dmellema@raytheon.com) or Ken Grossman )ksgrossman@raytheon.com). Steve Kirsch skirsch@raytheon.com RAYTHEON TECHNOLOGY TODAY 2006 ISSUE 1 23
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