PCI Express* 3.0 Technology: Device Architecture ... - Intel

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Platform Power Savings OpportunityPlatform Power in Watts4035302520151050Average power scenario running MM07 (Office* Productivity suite)On an Intel ® Core2 Duo platform running Windows* Vista*0 10 20 30 40 50 60 70 80 90 100 110Source: Intel CorporationTime in MinutesIdle workload power(~8W – 10W)PMOpportunity• Usage Analysis: Typical mobile platform in S0 state is ~90% idle• When idle, platform components are kept in high power state tomeet the service latency requirements of devices & applicationsPower consumption for idle workload is high14
Optimized Buffer Flush/Fill• Next several foils describe:– Platform activity alignment– PCI Express* (PCIe*) OBFF mechanisms– OBFF within context of platform activityalignment– Device implementation impacts for OBFF15
Page 1 and 2: SF 2009PCI Express* 3.0 Technology:
Page 3 and 4: PCI Express* (PCIe*) 2.1 Protocol E
Page 5 and 6: Device Architecture Considerations
Page 7 and 8: Requirements ChecklistEcosystemPlat
Page 9 and 10: Interrupt Vector ModeST associated
Page 11 and 12: TPH Aware Device ArchitectureClassi
Page 13: System Perspective• Device behavi
Page 17 and 18: 17Optimized Buffer Flush/Fill (OBFF
Page 19 and 20: OBFF Device ImplementationImpactsMa
Page 21 and 22: Power Vs Response Latency(Mobile)Pl
Page 23 and 24: Application State Driven LTRExample
Page 25 and 26: Software Guided LatencySW Guided La
Page 27 and 28: Software EnablingFeatures requiring
Page 29 and 30: Call to Action• Device Architectu
Page 31 and 32: Additional Sources of Informationon
Page 33: Risk FactorsThe above statements an

PCI Express* 3.0 Technology: Device Architecture ... - Intel

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