PCI Express* 3.0 Technology: Device Architecture ... - Intel

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OBFF and Activity AlignmentPlatformPCIePCIePCIeDev ADev BDev CWAKE#Traffic Pattern with No OBFFDevice ADevice BDevice COS TimerTick (intrpt)InterruptsDMAsTraffic Pattern with OBFFTimeIdleWindowActiveWndwIdleOBFFIdleWindowActiveWndwIdleWindowOBFFWndwIdleWindowActiveWindow18PCI Express* (PCIe*) Technology18
OBFF Device ImplementationImpactsMaximize idle windowduration for platformClassify device initiatedtransactions:critical vs. deferrable•Align transactions withother devices in system•Coalesce transactions intogroups where possible– Perform groups oftransactions all atonce, don’t trickle allthe time•Perform criticaltransactions as necessary•Defer other transactionsto align with platformactivity– Decode platform idle/ active / OBFFwindow signalingSelect data buffer depths to tolerate platform activityalignment• 300µs of deferral buffering recommended for Intel mobileplatforms1919
Page 1 and 2: SF 2009PCI Express* 3.0 Technology:
Page 3 and 4: PCI Express* (PCIe*) 2.1 Protocol E
Page 5 and 6: Device Architecture Considerations
Page 7 and 8: Requirements ChecklistEcosystemPlat
Page 9 and 10: Interrupt Vector ModeST associated
Page 11 and 12: TPH Aware Device ArchitectureClassi
Page 13 and 14: System Perspective• Device behavi
Page 15 and 16: Optimized Buffer Flush/Fill• Next
Page 17: 17Optimized Buffer Flush/Fill (OBFF
Page 21 and 22: Power Vs Response Latency(Mobile)Pl
Page 23 and 24: Application State Driven LTRExample
Page 25 and 26: Software Guided LatencySW Guided La
Page 27 and 28: Software EnablingFeatures requiring
Page 29 and 30: Call to Action• Device Architectu
Page 31 and 32: Additional Sources of Informationon
Page 33: Risk FactorsThe above statements an

PCI Express* 3.0 Technology: Device Architecture ... - Intel

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