PCI Express* 3.0 Technology: Device Architecture ... - Intel

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LTR <strong>Device</strong> Implementation ImpactsWhen idle, let platform enter deep power saving states‣ Use MaxLatency (LTR Extended Capabilities field) when idle‣ Require low latencies only when necessary – don’t keepplatform in high power state longer than necessaryDynamic, hardwaredriven LTR‣ Leverage applicationbased opportunities totolerate more latency• E.g. WLAN radio offbetween beacons‣ Implement databuffering mechanismto comprehend LTRSWGuided?Software guidedLTR‣ Implementsimple MMIOregisterinterface• Registerwrites causeLTR messageto be sent2626
Software EnablingFeatures requiring basic software supportCapability Discovery,Identification andManagement8GT/s speed upgradeAtomicsTransaction Ordering RelaxationsInternal Error ReportingTLP PrefixFeatures requiring additional supportAbove and beyondcapability enablementResource Allocation,Enumeration & APITransaction Processing HintsLTR & OBFFResizable BARIO Page FaultsDynamic Power AllocationMulticast27
Page 1 and 2: SF 2009PCI Express* 3.0 Technology:
Page 3 and 4: PCI Express* (PCIe*) 2.1 Protocol E
Page 5 and 6: Device Architecture Considerations
Page 7 and 8: Requirements ChecklistEcosystemPlat
Page 9 and 10: Interrupt Vector ModeST associated
Page 11 and 12: TPH Aware Device ArchitectureClassi
Page 13 and 14: System Perspective• Device behavi
Page 15 and 16: Optimized Buffer Flush/Fill• Next
Page 17 and 18: 17Optimized Buffer Flush/Fill (OBFF
Page 19 and 20: OBFF Device ImplementationImpactsMa
Page 21 and 22: Power Vs Response Latency(Mobile)Pl
Page 23 and 24: Application State Driven LTRExample
Page 25: Software Guided LatencySW Guided La
Page 29 and 30: Call to Action• Device Architectu
Page 31 and 32: Additional Sources of Informationon
Page 33: Risk FactorsThe above statements an

PCI Express* 3.0 Technology: Device Architecture ... - Intel

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