Assertion Based Verification using PSL

AN5Property Specification Language (PSL)• PSL is IEEE 1850, it’s supported by EDA community• Supports Verilog, VHDL but also SystemVerilog andSystemC• Powerful in describing Assertions e.g:Request and fifo empty are never high at same timeassert never { req AND fifo_empty };Request is always acknowledged 1 to 3 cycles after assertedassert always { rose (req) } |-> { [*1:3]; ack};Request is acknowledged eventuallyassert always req -> eventually! ack;Philips Semiconductors Sylvain Boucher 26-06-20064