IO ESD protection - Sofics

Data sheetIO ESD protectionLow capacitive 1.2V IO protection forTSMC 28nm CMOS technologySofics continues to build solutions for the most advanced CMOS nodes.The technology was previously verified on TSMC 40nm CMOS G and LPtechnology and already product proven in more than 25 mass produced40nm products. The cells provide competitive advantage throughimproved yield, reduced silicon footprint and enable advanced multimediaand wireless interfaces like HDMI, USB 3.0, SATA, WIFI, GPS and Bluetooth.The same technology is also ported to TSMC 28nm HP. A comprehensiveESD test chip was taped out in April 2011 – silicon results are expected byAugust 2011.The ESD clamp described in this document protects all kinds of 1.2Vinterfaces (input, output, bidirectional) based on 1.8V transistors in TSMC28nm CMOS technology. It features a low leakage current and a lowparasitic capacitance. Thanks to the small silicon footprint it can be easilyincluded into a broad set of IO’s.

Data sheet: Low capacitive 1.2V IO protection for TSMC 28nm CMOS technologyESD protection clamp for 1.2V IO interfacesClamp type and usageThe Sofics ESD cells cover all types of protection concepts and approaches as detailed in the figure below. The ESDclamp cell described in this document is a combination of ‘Type A’ and ‘Type B’ solution.The ESD cell can be used for the protection of all kinds of 1.2V interfaces (input, output or bidirectional). It is in usefor a 32kHz Xtal oscillator module operated at 1.2V to2V.Core ProtectionInput ProtectionOutput ProtectionIO ProtectionOver Voltage Tolerant IO (OVT)Protection 1.2V CommentsUnder Voltage Tolerant IO (UVT)Diode present between GND and PADInter Domain ProtectionFeatures Efficient ESD protectiono > 2 kV Human Body Model (HBM)o > 200 V Machine Model (MM) Leakage < 50 pA measured at 1.2V Capacitance < 320 fF measured at 0V bias Silicon footprint < 1900um²Sofics Proprietary – ©2011 Page 2

Data sheet: Low capacitive 1.2V IO protection for TSMC 28nm CMOS technologyMaximum ratingsRating Symbol Value UnitMin MaxSupply Voltage Range (DC) V DD -0.3 1.32/1.98 VInput/Output Voltage Range (DC) V IO -0.3 V DD + 0.3 VOperating Temperature T op -40 125 °CBurn-in Voltage (DC @ 125°C) - 2.7 VStresses exceeding these maximum ratings may damage the device. Functional operation above the recommended operatingconditions is not implied. Extended exposure to stresses above the recommended operating conditions may affect devicereliability.The provided golden cell is designed for these maximum ratings/specifications. If the desired specification level differs, thegolden cell has to be scaled up or down by using the Sofics implementation/scaling guidelines to remain a robust andeffective ESD protection for the different specifications.Electrical CharacteristicsT amb = 25°C unless stated otherwisePreliminary values based on equivalent circuitry on 40nm silicon and simulations with foundry approvedmodels.Parameter Symbol Typ. UnitTrigger Voltage V t1 4.05 VHolding Voltage V h 1.15 VLeakage current @ T amb = 25 °, 1V DC I leak 50 pALeakage current @ T amb = 125 °C, 1V DC I leak 10 nATotal Capacitance Load, 0V bias C L 318 fFHBM – Human Body Model 2.1 kVMM – Machine Model 210 VProcess, Area and integration Process: TSMC 28 nm – HP Used Metals: 4 metals Special needed Layer: None Area: 1804.28 um² (38.52um x 46.84um)Sofics Proprietary – ©2011 Page 3

Data sheet: Low capacitive 1.2V IO protection for TSMC 28nm CMOS technologyAbout SoficsSofics (www.sofics.com) is the world leader in on-chip ESD protection. Itspatented technology is proven in more than a thousand IC designs across allmajor foundries and process nodes. IC companies of all sizes rely on Sofics for offthe-shelfor custom-crafted solutions to protect overvoltage I/Os, other nonstandardI/Os, and high-voltage ICs, including those that require system-levelprotection on the chip. Sofics technology produces smaller I/Os than any genericESD configuration. It also permits twice the IC performance in high-frequency andhigh-speed applications. Sofics ESD solutions and service begin where the foundrydesign manual ends.ESD SOLUTIONS AT YOUR FINGERTIPSOur service and supportOur business models include Single-use, multi-use or royalty bearing license for ESD clamps Services to customize ESD protectiono Enable unique requirements for Latch-up, ESD, EOSo Layout, metallization and aspect ratio customizationo Area, capacitance, leakage optimization Transfer of individual clamps to another target technology Develop custom ESD clamps for foundry or proprietary process Debugging and correcting an existing IC or IO ESD testing and analysisNotesAs is the case with many published ESD design solutions, the techniques andprotection solutions described in this data sheet are protected by patents andpatents pending and cannot be copied freely. PowerQubic, TakeCharge, andSofics are trademarks of Sofics BVBA.VersionNovember 2011Sofics BVBAGroendreef 31B-9880 Aalter, Belgium(tel) +32-9-21-68-333(fax) +32-9-37-46-846bd@sofics.comRPR 0472.687.037Sofics Proprietary – ©2011 Page 4