3.3V IO ESD protection - Sofics

Data sheet3.3V IO ESD protectionLow capacitance 3.3V IO protection forTSMC 65nm CMOS technologySofics has verified its TakeCharge ESD protection clamps on TSMC 65nmCMOS technology. The devices are product proven in more than 70 massproduced 65nm products. The cells provide competitive advantagethrough improved yield, reduced silicon footprint and enable advancedmultimedia and wireless interfaces like HDMI, USB 3.0, SATA, WIFI, GPSand Bluetooth.The ESD clamp described in this document protects 3.3V IOs in TSMC65nm CMOS technology. It features a low leakage current, low capacitanceand a small silicon footprint.

Data sheet: Low leakage 3.3V clamp for TSMC 65nm CMOS technologyESD clamp for 3.3V interfacesClamp type and usageThe Sofics ESD cells cover all types of protection concepts and approaches as detailed in the figure below. The ESDclamp cell described in this document is a type C clamp.The ESD cell can be used for the protection of all kinds of 3.3V interfaces.Protection 3.3V CommentsCore ProtectionInput ProtectionOutput ProtectionIO ProtectionOver Voltage Tolerant IO (OVT)Under Voltage Tolerant IO (UVT)Inter Domain ProtectionFeatures Efficient ESD protectiono > 2 kV Human Body Model (HBM)o > 200 V Machine Model (MM) Integrated power clamp Low leakage < 0.1 nA measured at 3.63 V Low junction capacitance of 109fF Silicon footprint < 3300um²Sofics Proprietary – ©2012 Page 2

Data sheet: Low leakage 3.3V clamp for TSMC 65nm CMOS technologyMaximum ratingsRating Symbol Value UnitMin MaxSupply Voltage Range (DC) V DD -0.3 3.63 VInput/Output Voltage Range (DC) V IO -0.3 3.63 VOperating Temperature T op -25 125 °CBurn-in Voltage (DC @ 125°C) 4.95 VStresses exceeding these maximum ratings may damage the device. Functional operation above the recommended operatingconditions is not implied. Extended exposure to stresses above the recommended operating conditions may affect devicereliability.The provided golden cell is designed for these maximum ratings/specifications. If the desired specification level differs, thegolden cell has to be scaled up or down by using the Sofics implementation/scaling guidelines to remain a robust andeffective ESD protection for the different specifications.Electrical CharacteristicsT amb = 25°C unless stated otherwiseParameter Symbol Typ. UnitTrigger Voltage V t1 4.94 VHolding Voltage V h 1.38 VLeakage current @ T amb = 25 °C I leak 50 pALeakage current @ T amb = 120 °C I leak 684 nAParasitic Junction capacitance C junction 109 fFHBM – Human Body Model 2 kVMM – Machine Model 200 VProcess, Area and integration Process: TSMC 65 nm – LP Used Metals: 3 metals Special needed Layer: N/A Area: 3287.219 um² (33.8 um x 97.225 um)Sofics Proprietary – ©2012 Page 3

Data sheet: Low leakage 3.3V clamp for TSMC 65nm CMOS technologyAbout SoficsSofics (www.sofics.com) is the world leader in on-chip ESD protection. Itspatented technology is proven in more than a thousand IC designs across allmajor foundries and process nodes. IC companies of all sizes rely on Sofics for offthe-shelfor custom-crafted solutions to protect overvoltage I/Os, other nonstandardI/Os, and high-voltage ICs, including those that require system-levelprotection on the chip. Sofics technology produces smaller I/Os than any genericESD configuration. It also permits twice the IC performance in high-frequency andhigh-speed applications. Sofics ESD solutions and service begin where the foundrydesign manual ends.ESD SOLUTIONS AT YOUR FINGERTIPSOur service and supportOur business models include Single-use, multi-use or royalty bearing license for ESD clamps Services to customize ESD protectiono Enable unique requirements for Latch-up, ESD, EOSo Layout, metallization and aspect ratio customizationo Area, capacitance, leakage optimization Transfer of individual clamps to another target technology Develop custom ESD clamps for foundry or proprietary process Debugging and correcting an existing IC or IO ESD testing and analysisNotesAs is the case with many published ESD design solutions, the techniques andprotection solutions described in this data sheet are protected by patents andpatents pending and cannot be copied freely. PowerQubic, TakeCharge, andSofics are trademarks of Sofics BVBA.VersionMarch 2012Sofics BVBAGroendreef 31B-9880 Aalter, Belgium(tel) +32-9-21-68-333(fax) +32-9-37-46-846bd@sofics.comRPR 0472.687.037Sofics Proprietary – ©2012 Page 4