ML6554 3A Bus Termination Regulator - Future Electronics

Functional DescriptionThis switching regulator is capable of sinking and sourcing 3A ofcurrent without an external heatsink. The ML6554 uses a powersurface mount package (PSOP) that includes an integrated heatslug which is inherently connected to GND. The heat can bepiped through the bottom of the device and onto the PCB (Figure1).The ML6554 integrates two power MOSFETs that can be usedto source and sink 3A of current while maintaining a tight voltageregulation. Using the external feedback, the output can beregulated well within 3% or less, depending on the externalcomponents chosen. Separate voltage supply inputs have beenadded to accommodate applications with various power suppliesfor the databus and power buses, see Figure 2.OutputsThe output voltage pins (V L1 , V L2 ) are tied to the databus,address, or clock lines via an external inductor. See the Applicationssection for recommendations. Output voltage is determinedby the V CCQ or VREF IN inputs.InputsThe input voltage pins (V CCQ or VREF IN ) determine the outputvoltages (V L1 or V L2 ) . In the default mode, where the VREF INpin is floating, the output voltage is 50% of the V CCQ input.V CCQ can be the reference voltage for the databus.Output voltage can also be selected by forcing a voltage at theVREF IN pin. In this case, the output voltage follows the voltageat the VREF IN input. Simple voltage dividers can be used thiscase to produce a wide variety of output voltages between 0.7Vand V DD –0.7V.VREF Input and OutputThe VREF IN input can be used to force a voltage at the outputs(Inputs section, above). The VREF OUT pin is an output pin thatis driven by a small output buffer to provide the V REF signal toother devices in the system. The output buffer is capable of drivingseveral output loads. The output buffer can handle 3mA.Other Supply VoltagesSeveral inputs are provided for the supply voltages: PV DD1 ,PV DD2 , AV CC , and V DD .The PV DD1 and PV DD2 provide the power supply to the powerMOSFETs. V DD provides the voltage supply to the digital sections,while AV CC supplies the voltage for the analog sections.Again, see the Applications section for recommendations.Feedback InputThe V FB pin is an input that can be used for closed loop compensation.This input is derived from the voltage output. Seeapplication section for recommendation.ML6554 3A Bus Termination RegulatorHEAT SLUGConnect this slug to a GNDPlane for better Thermalconductivity.Figure 1. Cutaway view of PSOP PackageML6554 Rev. 1.1.54 www.fairchildsemi.com

ApplicationsUsing the ML6554 for SSTL Bus TerminationThe circuit schematic in Figure 2 shows a recommendedapproach for constructing a bus terminating solution for anSSTL-2 bus. This circuit can be used in PC memory and Graphicsmemory applications as shown in Figures 4 and 5. Note thatthe ML6554 can provide the voltage reference (V REF ) and terminatingvoltages (V TT ). Using the layout as shown in Figures 6, 7,and 8, and measuring the V TT performance using the test setupas described in Figure 9, the ML6554 delivered a V TT ± 20mVfor 1A to 3A loads (see Figure 10). Table 1 provides a recommendedparts list for the circuit in Figure 2.Power Handling Capability of the PSOPPackageUsing the board layout shown in Figures 6, 7, and 8; solderingthe ML6554 to the board at zero LFPM the temperature aroundthe package measured 55°C for 3A loads. Note that a 1 ouncecopper plane was used in the board construction.Airflow is not likely to be needed in the operation of this device(assuming a board layout similar to that described above). Thepower handling performance of the PSOP package is shown bya study of the package manufacturer for various airflow vs. θ JAconditions in Figure 11.Bus Termination Solutions for Others BusesTable 3 provides a summary of various bus termination V REF &V TT requirements. The ML6554 can be used for those applications.ML6554 3A Bus Termination RegulatorR2 100ΩC8 0.1µF2.5V TO 4VR1 100ΩC9 0.1µFU1ML6554R3100kΩC5 C6330µF 330µFV TTTPITO SDRAMSC1820µFF2VOS-CONL1 3.3µH C3 0.1µFC20.1µFC4 0.1µF12345678V DDPV DD1V L1P GND1P GND2V L2PV DD2D GNDAV CCV CCQVREF OUTAGNDSHDNVREF INV FBV DD161514131211109V CCQVREF OUTSHDNVREF INR4 100kΩR5 1kΩC7 1nFGNDGNDFigure 2. Typical Application CircuitML6554 Rev. 1.1.55 www.fairchildsemi.com

V TTTO SDRAMSC1820µFF2VOS-CONL1 3.3µHC20.1µFC3 10µF12345678V DDPV DD1V L1P GND1P GND2V L2PV DD2D GNDU1ML6554AV CCV CCQVREF OUTAGNDSHDNVREF INV FBV DD161514131211109R3100kΩV CCQVREF OUTSHDNVREF IN2.5V TO 4VC5 C6330µF 330µFML6554 3A Bus Termination RegulatorR1 100kΩR2 1kΩC4 1nFGNDGNDFigure 3. Alternate Application CircuitAn alternate application circuit for the ML6554 is shown in Figure3. The number of external components is reduced comparedto the circuit in Figure 2. This is achieved by replacingfour, 0.1µF bypass capacitors with one, low ESR, 10µF ceramiccapacitor placed right next to U1. Two 100Ω resistors are alsoeliminated. High value, surface-mount MLC capacitors were notavailable when the original application circuit (Figure 2) wasdeveloped. Both application circuits offer the same electricalperformance but that shown in Figure 2 has a reduced bill-ofmaterials.Table 2 shows the recommended parts list for the circuitof Figure 3.ML6554 Rev. 1.1.56 www.fairchildsemi.com

PC CHIP SETNORTHBRIDGEDATA LINE, CLOCK LINES,ADDRESS LINES, CONTROL LINESTERMINATIONRESISTORS168/184/208-PIN DIMM CONNECTORSAND SDRAM/SGRAM MODULESTERMINATIONRESISTORSVTTML6554 3A Bus Termination RegulatorVREFML6554Figure 4. Complete Termination Solution PC Main Memory (PC Motherboard)SO DIMMAND MODULESTERMINATIONRESISTORSSGRAM3DGRAPHIC CHIPDATA LINE, CLOCK LINES,ADDRESS LINES, CONTROL LINESVOLTAGEREGULATORTERMINATIONRESISTORS2.5VVTTVREFML65545V OR 3.3VAGP/PCI BUSFigure 5. Complete Termination Solution Graphics Memory Bus – AGP Graphics CardsML6554 Rev. 1.1.57 www.fairchildsemi.com

Figure 6. Top SilkML6554 3A Bus Termination RegulatorFigure 7. Top LayerFigure 8. Bottom LayerML6554 Rev. 1.1.58 www.fairchildsemi.com

3.3V POWERSUPPLYVV CCQSUPPLYAACTIVECLAMPV CCQV DDML6554EVALGNDV TTI TTCURRENT SOURCE/SINKPOWER SUPPLYML6554 3A Bus Termination RegulatorVAFigure 9. Test Circuit SetupV TT VARIANCE WITH V DD @I TT (V CCQ 2.5V)TESTED WITH EVAL PCBI TT3A SINKING2A SINKING1.29V TT (V)1.281.271A SINKING0A SINKING3A SOURCING2A SOURCING1.262.0 2.5 3.0 3.5 4.0V DD (V)1A SOURCINGFigure 10. VTT Performance for SSTL-2 BusML6554 Rev. 1.1.59 www.fairchildsemi.com

Table 1. Recommend Parts List for SSTL-2 Termination Circuit in Figure 2.Item Qty Description Manufacturer / Part Number DesignatorResistors1 2 100Ω1210 SMD Panasonic/ERJ-8ENF1000V R1, R22 1 1kΩ 1210 SMD Panasonic/ERJ-8ENF1001V R53 2 100kΩ1210 SMD Panasonic/ERJ-8ENF1003V R3, R4CapacitorsICSMagneticsOther4 3 0.1µF 1210 Film SMD Panasonic/ECV3VB1E104KC2, C8, C9Panasonic/ECU-V1H104KBW5 1 820µF 2V Solid Elect. SMD Sanyo/2SV820M Os Con C16 2 330µF Tant 6.3V 100mΩ AVX/TPSE337M006R0100 C5, C67 1 1nF 1210 Film SMD Panasonic/ECU-V1H102KBM C78 2 0.1µF 0805 Film Panasonic/ECJ-2VF1C104Z C3, C49 1 ML6554 Bus TerminatorPower SOP PackageML6554CU or ML6554IU10 1 3.3µH 5A inductor SMD Coilcraft/D03316P-332HCPulse Eng./ P0751.332TGowanda/SMP3316-331MXFMRS inc./XF0046-S411 1 Scope probe socket Tektronics/131-4353-00 TP112 1 12 Pin breakaway strip Sullins/PTC36SAAN (36 PINS) I/O, standoffsU1L1ML6554 3A Bus Termination RegulatorTable 2. Recommend Parts List for Figure 3.Item Qty Description Manufacturer / Part Number DesignatorResistors1 2 100kΩ 0805 SMD Panasonic/ERJ-8ENF1000V R1, R32 1 1kΩ 0805 SMD Panasonic/ERJ-8ENF1000V R2CapacitorsICSMagneticsOther3 1 0.1µF, 1210 Film SMD Panasonic/ECV3VB1E104KC2Panasonic/ECU-V1H104KBW4 1 820µF 2V Solid Elect. SMD Sanyo/2SV820M Os Con C15 2 330µF Tant 6.3V 100mΩ AVX/TPSE337M006R0100 C5, C66 1 1nF 1210 Film SMD Panasonic/ECU-V1H102KBM C47 1 10µF 6.3V Ceramic TDK/C2012X5R0J106M C38 1 ML6554 Bus TerminatorPower SOP PackageML6554CU or ML6554IU9 1 3.3µH 5A inductor SMD Coilcraft/D03316P-332HCPulse Eng./ P0751.332TGowanda/SMP3316-331MXFMRS inc./XF0046-S410 1 Scope probe socket Tektronics/131-4353-00 TP111 1 12 Pin breakaway strip Sullins/PTC36SAAN (36 PINS) I/O, standoffsU1L1ML6554 Rev. 1.1.510 www.fairchildsemi.com

Vendor List1. AVX (207) 282-51112. Sanyo (619) 661-68353. Tektronix (408) 496-08004. Coilcraft (847) 639-64005. Pulse (800) 797-85736. Gowanda (716) 532-22347. Xfmrs Inc. (317) 834-10668. Panasonic (714) 373-73669. Digikey (800) 344-45396060ML6554 3A Bus Termination Regulator4040θ JA (ºC/W)20Θ JA (ºC/W)2000.016Ld PSOP22.3x3.1mm PAD1.9mm DIE0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0POWER (W)NATURAL CONVECTION Θ JA TEST RESULTS1.27mm PITCH PowerSOP 2SLUG SOLDERED016Ld PSOP22.3x3.1mm PAD1.9mm DIE @ 0.8 WATTS0 100 200 300 400 500AIR VELOCITY (LFPM)FORCED CONVECTION Θ JA TEST RESULTS1.27mm PITCH PowerSOP 2SLUG SOLDEREDFigure 11. Graphical Results Summary – 1S2P Test BoardML6554 Rev. 1.1.511 www.fairchildsemi.com

DRAWING NUMBERENG-CB-1007 REV AApplicable Jedec Spec JC 51-X (Note 1)(Proposed Spec)Substrate MaterialFR-4Dimensions (LxW) (Overall)114.3 x 76.2mmDimensions (LxW) (Metallization)55 x 65mmDimensions (LxW) (Inner Planes)73 x 73mmThickness1.6 mmPitch1.27mmStackup (# Signal Layers, # Cu Planes)1S2PCu Trace Coverage (Signal Layer) 12%Cu Coverage (Internal Layer) 100%Trace Width (Spec/Measured)235.5±25.5/288µmTrace Cu Thickness (Spec/Measured)70±14/67µmInner Cu Thickness (Spec/Measured)35±3.5/31µmBuild #C1797ML6554 3A Bus Termination RegulatorNote 1: Proposed Spec "Thermal Test Board with Two Internal Solid Copper Planes for leaded Surface Mount Packages".Figure 12. Test Board Layout for Θ JA vs. AirflowTable 3. Termination Solutions Summary By Buss TypeBusDescriptionDrivingFairchildMethod VDDQ VTT V REF SolutionsIndustrySystemComponentsGTL+GunningTransceiverBus PlusOpen Drain 5v or 3.3VNote 101.5V±10%Note121.0V±2%Note 11ML6554CU;Mode: V REFInput = 1.5V,V CC = 5V300 to 500MHzProcessor;PC Chipsets;GTLP 16xxxBuffers;Fairchild,Texas Instr.SSTL_2Series StubTerminatedLogic for 2VSymmetricDrive, SeriesResistance2.5V±10% 0.5x(V DDQ )±3%2.5V ML6554CUor ML6553CS;Mode: V REFInput = Floatingor Forced,V CC = 3.3VSSTL SDRAM;Hitachi,Fujitsu,NEC, Micro,MitsubishiRAMBUSRAMBUSSignalingLogicOpen DrainNoneSpecified2.5V 2.0V ML6553CS;Mode: V REFInput = Open,V CC = V DDQnDRAM,RAMBUS,Intel, ToshibaLV-TTLLow VoltageTTL Logic orPECL or3.3V VMESymmetricDrive3.3±10% V DDQ /2 3.3V ML6553CS;Mode: V REFInput = Open,VCC = VDDQProcessors orbackplanes;LV-TTLSDRAM,EDO RAMML6554 Rev. 1.1.512 www.fairchildsemi.com

Mechanical Dimensions16-Pin PSOP6.00PIN ONEINDICATOR(0.30)169.90 ± 0.108.891 81.279A0.510.35B3.90 ± 0.100.25 M C B A1.951.753.700.601.277.508.89LAND PATTERN RECOMMENDATION2.50 7.403.50ML6554 3A Bus Termination Regulator1.75 MAX1.45 +0.05–0.20CSEE DETAIL A0.250.19(R0.10)(R0.10)8°0°0.70 ± 0.20(1.04)DETAIL ASCALE: 2:1+0.100.15–0.050.500.25X 45°GAGE PLANE0.36SEATING PLANE0.10 CNOTES: UNLESS OTHERWISE SPECIFIEDA) THIS PACKAGE CONFORMS TO JEDECMS–012, VARIATION AC, ISSUE C,DATED MAY 1990.B) ALL DIMENSIONS ARE IN MILLIMETERS.C) DIMENSIONS DO NOT INCLUDE MOLDFLASH OR BURRS.Ordering InformationPart Number Temperature Range PackageML6554CU 0°C to 70°C 16-Pin PSOP (U16)ML6554IU -40°C to +85°C 16-Pin PSOP (U16)ML6554 Rev. 1.1.513 www.fairchildsemi.com

TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such trademarks.ACExActiveArrayBottomlessCoolFETCROSSVOLTDOMEEcoSPARKE 2 CMOSEnSignaFACTFACT Quiet SeriesDISCLAIMERFAST ®FASTrFPSFRFETGlobalOptoisolatorGTOHiSeCI 2 Ci-LoImpliedDisconnectAcross the board. Around the world.The Power Franchise ®Programmable Active DroopIntelliMAXISOPLANARLittleFETMICROCOUPLERMicroFETMicroPakMICROWIREMSXMSXProOCXOCXProOPTOLOGIC ®OPTOPLANARPACMANPOPPower247PowerEdgePowerSaverPowerTrench ®QFET ®QSQT OptoelectronicsQuiet SeriesRapidConfigureRapidConnectµSerDesSILENT SWITCHER ®SMART STARTSPMStealthSuperFETSuperSOT-3SuperSOT-6SuperSOT-8SyncFETTinyLogic ®TINYOPTOTruTranslationUHCUltraFET ®UniFETVCXML6554 3A Bus Termination RegulatorFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANYPRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES ITCONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in significant injury to theuser.PRODUCT STATUS DEFINITIONSDefinition of Terms2. A critical component is any component of a lifesupport device or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.Datasheet Identification Product Status DefinitionAdvance InformationPreliminaryNo Identification NeededFormative orIn DesignFirst ProductionFull ProductionThis datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice.This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.ObsoleteNot In ProductionThis datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.Rev. I15ML6554 Rev. 1.1.514 www.fairchildsemi.com