Minimum 3: Implementing FSM in VHDL and simulations in Quartus-II

E. T. TELECOMMUNICATIONS Instrumentation and BioengineeringDigital Block 12/04/2007 Prof. Josep Conesa and F. J. Sànchez- Minimum control: April 12 th and 13 th- Grades will be available on April 16 th- Questions about the examination: Monday 11:00 - 13:00; Tuesday 15:00-19:00VERY IMPORTANT: Draw a general schematic or plan, develop the exercise and justify the results alwaysexplaining what are you doingMinimum 3:Implementing FSM in VHDL and simulations in Quartus-IIThe control unit (CU) of the UART transmitter module under development has the entity blockdiagram shown in Fig. 1 and will be designed as a Moore FSM which runs state diagram of Fig. 2.Fig. 1 Control unit for the UART transmitter and the Module-8 divider1. Explain the differences between functional and timed simulations to be run under a PLD designenvironment as Quartus-II or ispLEVER.(2p)(*)2. Using Quartus-II design environment and the standard architecture for a FSM shown in Fig. 4,build a VHDL project (for a MAX7128S or a FLEX10K device) to code the auxiliary Mod-8binary counter which helps the CU to serialize the data byte through the shift register.(2p)3. Using the standard architecture for a FSM shown in Fig. 4, code in VHDL the CU that controlsall the transmitter operations. The CU implements the state diagram represented in Fig. 2.Integrate the CU code and the Mod-8 binary counted code into a single entity named“UART_Transmitter”(2p)4. Prepare a waveform file for simulating the performance of the entity to be designed anddetermine which will be the control unit outputs for each input vector. Use the initiated timingdiagram in Fig. 3 to plot your results (2p) (*)

5. Verify the “UART_Transmitter” entity operation through a functional and a timed simulation.Determine the worse case propagation delay and the maximum frequency of operation for thecircuit attending the results of the “timing analysis”.(2p)6. (For students who want to go further in EX3) Complete the Quartus-II design flow (pinassignment and device programming) to implement your design in the Altera UP2 trainingboard. Integrate the operational unit blocs (multiplexer, parity generator, registers, quartz clockdividers and debouncing circuit) in your “UART_Transmitter” project as stated in EX3.Fig. 2 FSM state diagram

Fig. 3 Sketch of an initial timing diagram to be developed for predicting and simulating theoutput waveforms

Using concurrent assignments orsignal-sensitive processesrCOMBINATIONALSYSTEMCS2mZ (outputs)Xn(inputs)rrCOMBINACIONALSYSTEMCS1future_stateSIGNALSSTATE MEMORYCLKUsually using FF-DCDpresent_staterState_register (Clock and CDsensitive processFig. 4 Example diagram to represent the main blocks in the VHDL code (the number of bits rnecessary to code the internal state will depend on the coding strategy (binary, Gray, oneshot,etc.)