2. 5 Design of a simple frequency counter of 1MHz range and 1Hz ...

2. 5 Design of a simple frequency counter of 1MHz range and 1Hzresolution• An example of how to control an operating unit (OU) by means of a FSMacting as the control unit (CU).• An example of an Application Project which integrates in a singleapplication many concepts distributed in the course and even in courseslike Laboratori d’Electrònica.We want to design a simple frequency counter of 6 digits for measuring frequenciesfrom 1 Hz to 1 MHz. The block diagram with the main building blocks are pictured inFig. 1. A frequency counter is an electronic device capable of counting the number ofcycles in an electrical signal during a preselected time interval, in our case, 1 s, so thatthe count number represents directly the measurement of the frequency of the inputsignal.The main blocks of the circuit are: 1) the input conditioner; 2) the output 6 digitindicator; 3) the time base which generates a CLK signal of a 1 Hz frequency from a10MHz quartz oscillator; 4) the operational unit (UO) for counting the input pulses andregistering the final count; and 5) the control unit (CU) for governing the system bymeans of a state diagram.FinInput signalcoditionerFinOperational Unit or Data SubsystemCLK26-digit decadecounterControlLD_LTCLK= 1 s Unit or24-line parellelFSMregister1Hztime base10MHzquarz 4 4 4 4 4PCD44444446 x BCD-7SEG decoder77777HzFig. 1 Block diagram of the electronic digital frequency counter which has tobe designed in this exercise. Designing the operational unit (OU):

- Implement the counter module 10 6 for having a measurement range of 6 digits.Use a chain of 6 decade counters, which can be, for example, the universalcounters implemented in Problem 2.13 truncated for a BCD count).- Implement the 24 bit parallel register for saving the frequency count. Use, forexample, the parallel load feature of an universal counter which has beenpermanently disabled for counting (CE_L = 1). Designing the output module for the 7-segment displays:- Use and adapt the circuit designed in Problem 1.8 for this task.DCBABI_LLT_LRBI_LSCa_Lb_Lc_Ld_Le_Lf_Lg_LRBO_LDESCODIFICADOR HEX-7SEG Designing the input signal conditioner for adapting many waveforms andvoltages ranges.- In this case, you have to rely on the concepts and circuits implemented in theLaboratori d’Electrònica course. Try for example, an operational amplifierconnected in open loop acting as comparator in order to obtain a digital squarewaveform from a sinusoidal input. Designing the control unita) Specifications: Symbol: Shown in Fig. 1. Example of a timing diagram showing the CLK signal, and the output’sactivity for some periods. State diagramb) Particularize the general architecture of a Moore FSM to the problem as in Fig.2 if FF-JK (use for example the 74112) are selected as the state memory buildingblock.

Q[1..0]SC2PCDLD_LSC14CLKStatememory2Q[1..0]Fig. 2 Example of particularization of the canonical FSM that can be designedstep by step following the general procedure stated in Unit 2.5.c) Codify the states in binary code.d) Draw the state memory schematic.e) Design the SC2, which produces the outputs CD, LD_L, and P.f) Design the SC1, which establishes the next state after each CLK edge transitionfrom low to high.g) (optional) Capture the schematics in Proteus-VSM Lite and perform a circuitsimulation to verify if the design follows the specifications stated in a).h) (optional) Using the MAX-PLUS software from Altera, try to capture theschematics or VHDL files for describing de circuit and program a CPLD likeMAX7128 or FLEX10K to implement the whole circuit in a single chip.