Tutorial 11, Final Review - ECSE 425 â Computer Organization and ...

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Speculative Tomasulo(C) 2003 Elsevier Science (USA). All rights reserved.
Multiple-issue processors●●●A CPU can have parallel pipelinesSuperscalar: schedule instructions whenpossible. More than one can issue at once.●●Static: fetch multiple instructions at once, issue all ifpossible. In-order execution.Dynamic: fetch multiple instructions at once,dynamic scheduling thereafter = o-o-o executionVLIW: (static superscalar, no hw hazarddetection) pack instructions into fixed-size longwords. Statically scheduled by the compiler
Page 1 and 2: Tutorial 11Final Exam Review
Page 3 and 4: Trends in technology●●●Bandwi
Page 5 and 6: Trends in IC cost●Four equations
Page 7 and 8: Locality●A processor spends most
Page 9 and 10: Pipelining●●●Split an instruc
Page 11 and 12: Pipeline hazards●●●Structural
Page 14 and 15: Multicycle operations●The FP pipe
Page 16 and 17: Instruction-level parallelism●●
Page 18 and 19: Loop unrolling●●●●We want t
Page 20 and 21: Dynamic scheduling●Hardware rearr
Page 22 and 23: Tomasulo's algorithm
Page 26 and 27: Memory hierarchy●●●●●Memo
Page 28 and 29: Caches●●●●●Block placemen
Page 30 and 31: Caches●●●●Miss rateMulti-le
Page 32 and 33: Cache coherence protocols●●●
Page 34 and 35: Virtual memory●●●●Each prog
Page 36: Final exam● December 9 th at 9am

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Tutorial 11, Final Review - ECSE 425 â Computer Organization and ...