An FPGA-based SPWM Generator for High-Frequency DC/AC ...

An FPGA-based SPWM Generator forHigh-Frequency DC/AC InvertersMatina Lakka, Eftichios Koutroulis, Apostolos DollasDepartment of Electronic & Computer EngineeringTechnical University of CreteGR-73100, Chania, Greecematinalakka@gmail.com, efkout@electronics.tuc.gr, dollas@ece.tuc.grAbstract—The DC/AC power converters (inverters) constitute themajor unit of the power generation systems implemented inRenewable Energy Sources, AC motor drives andUninterruptible Power Supply applications. The Sinusoidal PulseWidth Modulation (SPWM) principle is widely used to controlthe power switches deployed in DC/AC inverters. In this paper,an FPGA-based SWPM generator is presented, which is capableto operate at switching frequencies up to 1 MHz. Theexperimental results presented in this paper demonstrate thesuperiority of the proposed SWPM architecture over its pastproposedcounterparts in terms of both the maximum operatingswitching frequency and the accuracy of reproducing the desiredSPWM waveform.I. INTRODUCTIONThe DC/AC power converters (inverters) are deployed in gridconnectedPhotoVoltaic (PV) power generation systems inorder to transfer the DC energy which is generated by the PVpower source into the AC electric grid. The DC/AC invertersare also used in AC-motor drive and Uninterruptible PowerSupply (UPS) systems, where the objective is to convert theDC input voltage into a sinusoidal AC output voltage ofadjustable magnitude and/or frequency. A block diagram of aDC/AC inverter is depicted in Fig. 1. The Sinusoidal PulseWidth Modulation (SPWM) principle is widely used in DC/ACinverters in order to control the operating state of the powerswitches constituting the DC/AC inverter structure. In thiscase, the power switches of the converter (e.g. MOSFETs,IGBTs etc.) are set ON or OFF according to the result of thecomparison between a high-frequency, constant-amplitudetriangular wave (carrier) with two low-frequency (e.g. 50 Hz)reference sine-waves of adjustable amplitude [1]. This processis illustrated in Fig. 2. By using the SPWM technique, theFigure 1. A diagram of a DC/AC power converter (inverter).Figure 2. The Sinusoidal Pulse Width Modulation (SPWM) principle.frequency spectrum of the DC/AC inverter output waveform isformatted such that the non-fundamental harmonic componentsare located at relatively high frequencies (typically in the orderof several kHz). The high-frequency harmonics of thegenerated SPWM signal, Vspwm, are then filtered using a lowpassLC- or LCL-type filter, thus producing the high-powerand low-frequency sinusoidal waveform, V , at the DC/ACinverter output terminals (Fig. 2). The amplitude ofcalculated as follows:oVois VcVo= M⋅V d= ⋅ Vd(1)Vwhere Vd(V) is the DC input voltage of the DC/AC inverter,Vc(V) and Vtr(V) are the amplitudes of the reference sine andcarrier waves, respectively and M is the modulation index.Increasing the frequency of the triangular wave (switchingfrequency), fc, results in an increase of the DC/AC inverterpower density due to the reduction of the volume of themagnetic components comprising the output filter.The control unit of the DC/AC inverter is used for theexecution of control and energy management algorithms (e.g.output voltage regulation, Maximum Power Point Tracking-MPPT, SPWM modulation strategies etc.) and it is developedusing microcontroller, DSP and FPGA ICs [2]. Compared totr

the implementation using analog circuits, digital controllersenable the implementation of advanced control algorithms,offer flexibility in case of changes and they are less susceptibleto component and ambient variations [3]. Nowadays, FieldProgrammable Gate Arrays (FPGAs) are extensively used tocontrol power electronic converters, such as DC/DCconverters, matrix converters, resonant converters, convertersfor power factor correction applications and AC/DC converters[4]. In contrast to the microcontroller and DSP devices, FPGAsare able to execute the control operations concurrently, thusperforming high-speed computations in real time. The adventof FPGA technology has enabled rapid prototyping of digitalsystems.Depending on their nominal power rating, the DC/AC inverterstypically operate at switching frequencies, fc, in the range of1-100 kHz [5, 6]. However, operation at higher switchingfrequencies is expected in the near future [7] due to theavailability of modern power semiconductor devices, such asSilicon Carbide (SiC) JFETs, which are able to operate atswitching frequencies up to 3 MHz with low power losses [8].The digital SPWM generation unit implementations havedominated over their counterparts based on analog circuits,since they offer higher noise immunity and less susceptibilityto voltage and temperature variations [9]. In this paper, anFPGA-based SPWM generator is presented, which is capableto operate at switching frequencies up to 1 MHz (requiringFPGA operation at 100-160MHz), thus it is capable to supportthe high switching frequency requirements of modern powerelectronic DC/AC converters. In the following sections of thispaper the architectures of past-proposed SWPM generationunits are analyzed, the proposed FPGA-based SWPMgenerator is presented and the experimental results arediscussed.II.PAST-PROPOSED SPWM GENERATOR ARCHITETCURESIn the FPGA-based SPWM generation units presented in[10-15], the triangular wave is implemented in the form of anup-down counter. The reference sine-wave is sampled, with asampling frequency equal to f , at the time instants whichscorrespond either only to the nadirs or both at the nadirs andthe peaks of the carrier wave (Fig. 3). The correspondingsamples are stored in digital format in a Look-Up Table (LUT)implemented in the FPGA internal memory. The SPWMcontrol signals are produced by comparing the correspondingvalues of the sinusoidal and carrier digital signals.The architecture presented in [12] implements an SPWMgenerator by sampling the sine-wave at the nadir times of thecarrier wave. This architecture was implemented on theXC4000XL Xilinx FPGA device with a 5 kHz switchingfrequency. The sine-wave used as a reference to generate theSPWM output is divided into four symmetric sections, i.e.sections A, B, C and D, respectively, in Fig. 4. Section Bcorresponds to the mirror of A, while sections C and D areequal to the opposites of sections A and B, respectively. Hence,sections B, C and D of the reference sine-wave can bereconstructed by storing data relevant to section A only. In thisway, only a quarter of the sine-wave period is required to bestored. This approach reduces representations to 25% of thetotal data required to re-produce the reference sine-wave. Theoverall block diagram of the SPWM generator proposed in [12]is shown in Fig. 5(a). The system consists of an eight-bit updowncounter which generates a triangular waveform byincreasing its value from 0 to 255 and then subsequentlydecrementing it back to 0 over a period of time equal toTc= 1 / f . The resulting carrier signal is compared with thecoutput of the multiplier, which is obtained from multiplicationof the modulating signal produced using the look-up table data,as analyzed above, with an external modulation index input.The architecture proposed in [15] implements a three-phaseFPGA-based SPWM generator by sampling the sine-wave bothat the nadir and the peak instants of the carrier-wave with a20 kHz switching frequency. The SPWM core has beendesigned using VHDL and implemented in a single FPGAdevice (SPARTAN XC3S400PQ208). The block diagram ofthis architecture is shown in Fig. 5(b). The reference sine-waveis generated by the “sine-wave generator” module using a lookuptable which contains the values of a sine-wave for 180°(half-period). The SPWM output pulses [i.e. signals PWM A,B and C in Fig. 5(b)] are generated by the “PWM Controller”module by comparing the sinusoidal reference and triangularcarrier signals. The QALU subsystem performs the dataFigure 4. The optimization concept of the SPWM generatorpresented in [12].(a)Figure 3. The operating principles of past-proposed SPWM generators.(b)Figure 5. Block diagrams of past-proposed SPWM generation units: (a)the architecture proposed in [12] an (b) the architecture proposed in [15].

epresentation as well as the arithmetic and logic operations ofthe SPWM algorithm in Q-Format representation.In [16, 17], the sampling frequency of the reference sine-wave,fs, is reduced by N in order to give a sampling frequency /carrier frequency relationship expressed by fs= 2 fc/ N . Thisprocedure results in only one sample being taken every N-samples of the conventional cases described above. Thus, thenumber of calculations required to produce the complete PWMwaveform is N times less than in the conventional cases. Thisis a substantial saving in calculation time, which enables todevelop SPWM generation units operating at significantlyhigher switching frequencies, for the same number ofcalculations performed.Another approach that has been proposed is the one thatalthough it uses a look-up table to store the values of thereference sine-wave corresponding to the time instants of thetriangular wave peaks and nadirs, there is no comparisonperformed between the sine and the triangular waves [18, 19].In this case, the width of each pulse of the generated SPWMwaveform is derived by a calculation performed according toan equation based on the similarity of two triangles ABC andADF that are formed between the sine and triangular (carrier)reference waves, as shown in Fig. 3.A common disadvantage of the past-proposed SPWMgenerators described above is that they have been designed tooperate at low switching frequencies (i.e. 1 kHz - 20 kHz),while their operation at higher switching frequencies has notbeen explored.III.THE PROPOSED FPGA-BASED SPWM GENERATORThe architecture of the proposed FPGA-based SPWMgeneration unit is illustrated in Fig. 6. Compared to the pastproposedSPWM generators, in the architecture proposed inthis paper the values of both the reference sine- and triangularwaves are stored in the BRAMs of the FPGA device, thusexploiting their one-clock-cycle access time. In order toproduce the discrete values used for the BRAMs initializationover the corresponding sampling period and simultaneouslyminimize the FPGA resource utilization, the memories areorganized such that both the sinusoidal and triangular wavesare sampled and quantized using the MATLAB software toolwith the same sampling frequency (e.g. 4 MHz, 16 MHz etc.).The proposed SPWM generation unit consists of five majorsubsystems. The input of the SPWM generator is themodulation index in single precision floating point arithmetic,while the system architecture is based on an 8-bit fixed-pointarithmetic. The “Clock Generator” subsystem takes as input thesystem clock and produces a new one that allows the wholesystem to operate in the desired switching frequency, fc. The“Modulation Index Module” accepts as input the modulationindex, which ranges from 0 to 1 and converts it to fixed-pointarithmetic, resulting in a fixed value ranging from 0 to 255.The “Sine-carrier” subsystem consists of the control unit, twoBRAMs, which store the values of the reference sinusoidal andtriangular signals, respectively, and two multiplexers whichproduce the two (positive and negative) reference sine-waves.The “Adjustable amplitude sine” subsystem outputs twosinusoidal digital signals with amplitude adjustable accordingto the value of the modulation index, which is also an input ofthis subsystem. The “Comparison” subsystem implements thecomparison between the high-frequency, constant-amplitudetriangular wave (carrier) with the two low-frequency referencesine-waves of adjustable amplitude, using two comparators.The control signals Ta+, Ta-, Tb+and Tb-of the DC/ACinverter power switches depicted in Fig. 1 are generated fromthe outputs of the corresponding comparators of thissubsystem, thus forming the SPWM pattern, Vspwm, in Fig. 2.IV.EXPERIMENTAL RESULTSThe performance of the proposed SPWM generation systemhas been evaluated on an actual design, which has been fullyimplemented and downloaded to an FPGA board containingthe XC5VLX110T Virtex-5 Xilinx FPGA device. The XilinxISE Design Suite 10.1 tool was used for the design of thereconfigurable architecture. The oscilloscope measurement ofthe generated control signal Ta+( T a-, Tb+and Tb-are similarlyproduced) in case that fc= 1 kHz and M = 0.5 is illustratedin Fig. 7. It is observed that the frequency of the individualpulses is equal to the switching frequency of the SPWM wave.The Fast Fourier Transform (FFT) of the SPWM wave, whichemulates the Vspwmsignal depicted in Fig. 1 and it is producedby subtracting the Ta+and Tb+control signals generated by theproposed system, in case that fc= 1 MHz , fs= 4 MHz andM = 0.5 , is depicted in Fig. 8. It is observed that the unipolarSPWM scheme, where either positive or negative pulses areproduced within each half-period of the SPWM output wave[1], has the advantage of “effectively” doubling the switchingfrequency as far as the harmonics are concerned. Theadvantage of “effectively” doubling the switching frequencyFigure 7. The control signal Ta+in case that fc= 1 kHz and M = 0.5 .Figure 6. The architecture of the proposed FPGA-based SPWM generator.Figure 8. The FFT pattern of the generated SPWM output waveform incase that f = 1 MHz , f = 4 MHz and M = 0.5 .cs

TABLE I. COMPARISON OF THE EXPERIMENTAL RESULTSOBTAINED BY THE PAST-PROPOSED SPWM ARCHITECTURES AND THEPROPOSED SPWM GENERATORMaximum switchingfrequencyModulation indexdeviation from itstheoretical value forf = 10 kHz andcM = 0.1-1Power consumption at themaximum operatingswitching frequencyDeviation of the TotalHarmonic Distortion(THD) of the generatedSPWM waveform fromits theoretical valueProposed SPWMgeneratorPast-proposed SPWMarchitectures1 MHz 0.25 MHzup to 5.6% up to 98.9%0.889 W(at 1MHz)0.887 - 0.932 W(at 10-250 kHz)7.3 % 7.7-26.8 %appears in the harmonic spectrum of the Vspwmoutput voltagewaveform, where the harmonics appear at sidebands which arelocated at multiples of twice the switching frequency, fc.The past-proposed SPWM generators presented in [12, 15-19]were also implemented in the same target Virtex-5 FPGAdevice in order to evaluate their performance and compare itwith that of the proposed SWPM generator. These architectureswere implemented such that they produce a unipolar SPWMfor single-phase full-bridge DC/AC inverters in order to befully compatible with the new SPWM generator introduced inthis paper. A comparison of the experimental results obtainedby the past-proposed SPWM generator architectures and theone proposed in this paper is summarized in Table I. In termsof the FPGA resources required, all architectures occupy asmall fraction (≈ 9 %) of the medium-sized FPGA device used.The BRAMs are the most critical resource that restricts anyfurther increase of the sampling frequency of the proposedSPWM generator architecture, while the next critical resourceis the DSPs that, compared to the past-proposed SWPMgeneration implementations, occupy 3% more space in theFPGA device.V. CONCLUSIONSThe SPWM principle is widely used to control the operation ofpower electronic DC/AC converters. The experimental resultspresented in this paper verify that the maximum operatingswitching frequency of the past-proposed FPGA-based SPWMgenerators does not exceed 250 kHz. In this paper, an FPGAbasedSWPM generator has been presented, which is capable tooperate at switching frequencies up to 1 MHz, thus it is capableto support the high switching frequency requirements ofmodern power electronic DC/AC converters. In order to beable to achieve operation at switching frequencies up to 1 MHzrequires FPGA operation at 100-160 MHz. The successfuloperation of the proposed SWPM generator at high switchingfrequencies has been verified with experimental results onactual hardware, thus validating the design.REFERENCES[1] N. Mohan, T.M. Undeland, W.P. Robbins, “Power Electronics:Converters, Applications and Design”, Wiley, 3 rd Edition, 2002.[2] E. Koutroulis, F. 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