memory products - Al Kossow's Bitsavers

MEMORY PRODUCTSDATABOOK1st EDITIONJUNE 1988

USE IN LIFE SUPPORT MUST BE EXPRESSLY AUTHORIZEDSGS-THOMSON' PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEM WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF SGS-THOMSONMicroelectronics. As used herein:1. Life support devices or systems are devices or systemswhich, are intended for surgical implant into the bodyto support or sustain life, and whose failure to perform,when properly used in accordance with instructions foruse provided in the labeling, can be reasonably expectedto result in a significant injury to the user.2. A critical component is any component of a life supportdevice or system whose failure to perform can bereasonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

TABLE OF CONTENTSGENERAL INDEX Page 5PRODUCT GUIDE 7EPROM DEVICES 23EEPROM DEVICES 197ROM DEVICES 257STATIC RAM DEVICES 2753

GENERAL INDEXPRODUCT GUIDE ............. .GENERAL INFORMATION .................... .SELECTION GUIDE ............................ .CROSS REFERENCE ... .PROCESSES CHARACTERISTICS.Page79.............................. ......... 111721EPROM DEVICESNMOS UV EPROM ....................... 23ET2716 (2K x 8)........ ......................................... 25M2716 (2Kx8)...... ........................................................................................... 25M2732A (4K x 8).. ............. ....................................................... 35M2764A (8K x 8) ........ ................... ........ .. ........ ...................... ..................................... 43M27128A (16K x 8) ........................................ .......................................... 53M27256 (32K x 8) ........ .... ........ ....... ........ ............................................... 63M27512 (64Kx8). ................................................................. ..................................................... 73CMOS UV EPROM ....... ..................................................... ...................................... 89ETC2716 (2K x 8) .................... ................................................................................................................ ........ 91ETC2732 (4Kx8)...... . ..................................................................................................................... 101TS27C64AQ (8K x 8)............................ ............................................................................................................ 111TS27C256Q (32K x 8) ........... .......................... .............................................................................................. 121ST27C1001 (128Kx8) ....................................................................................................................... 131M27C1024 (64K x 16) ....... ........................ ............................................................................. 133NMOS OTP ROM. ............................................................................................................................................ 143ST2764AP (8K x 8).. .................. ............... .................. .......... ............... .... ....... ................................................... 145ST27128AP (16K x 8) ...................................................................................................................... 155ST27256P (32Kx8).... ................. .............. ..................... ........ .............. ..... ......... ................................................ 165CMOS OTP ROM.............................. ....................................................................................... 175TS27C64AFN (8K x 8 - PLCC).. ................................................................................................................ 177TS27C64AP (8K x 8) .................................. ...................................................................................................... 177ST27C256FN (32K x 8 - PLCC)........ . .... ................................. .......................................................... 187ST27C256P 32Kx8 ..................................... ................................................................................................... 187EEPROM DEVICESNMOS EEPROM ................................................................................................................................................. 197M8571 (1 K bit) ......... ....................................................................................................................................... 199M9306 (256 bit) ................................................................................................................................................... 211M9346 (1 K bit) ....................................................................................................................................................... 217CMOS EEPROM ................................................................................................................................................. 227ST24C02 (2K bit) .................... ........................................................................................................................... 229TS59C11 (1 K bit) ................................................................................................................................................. 239TS93C46 (1 K bit) ............................................................................................................................................... 247ST93C56 (2K bit) ......................... ........................................................................................... 255~~~tmg~19~ --------------------5

GENERAL INDEXPageROM DEVICES ............................................................................................................................................. . 257M2316H (2K x 8) ............................................................................................................................................ .M2332 (4Kx8)............................................................ . .................................................................... ..M2333 (4Kx8) ................................................................................................................................................. ..M2364 (8K x 8) ............................. ........................... .. ................................................................... ..M2365 (8K x 8) ........................... ......................... ............................... . ......................................... .STATIC RAM DEVICES259263263267271ZEROPOWER ...................................................................................................................................................... 275MK48Z02 (2K x 8) .............................................. ................................................................................................ 277MK48C02 (2K x 8) .............................................................................................................................................. 289MK48T02 (2K x 8 - Timekeeper) ....... ....................................................................................... 299MK48Z08 (8Kx8).. ........................................ .. .............................................................................. 313MKI48Z02 (2K x 8). .......................................................... ................................................................. 325MK48T08 (8K x 8) ..... ......................................... ............................. ............................................................... 337MK48Z30 (32K x 8)... ......................................... ............................. ..................... .................... 351CACHE TAG RAM ........... ................................ ............................................................................................. 353MK41 H80 (4K x 8)................................................................................................................................................ 355MK4202 (2048 x 8) .............................................................................................................. 365MK48H74 (8Kx8)................................................................................................................................................ 383FIFO ........................................................................................................................................................................... 395MK4501 (512 x 9) ............................................................................................................................................ 397MK4503 (2048 x 9)........... ................................................................... 413MK4511 (512 x 8) ......................................................................................................................................... 429MK4505 (1024 x 5) ...........................................................................................................:................................ 441MK45264 ( 64 x 5).:....................................................................................................................................... 457MK45265 ( 64 x 5) ....................................................................................................................................:....... 457VERY FAST CMOS STATIC RAM ........ ........................................................................................ 475MK41H66 (16Kx 1) ............................................................................................................................................. 477MK41H67 (16Kx 1) ...................................................................................................................................... 477MK41 H68 (4Kx 1) ............................................................................................................................................ 487MK41H69 (4Kx4)......................................................................................................... ,......................... 487MK41H79 (4Kx4)............................................................................................................................................. 497MK41H87 (64Kx 1) ........................................................................................................................................... 507MK48H64 (8Kx8)............................................................................................................................................. 515MK48H65 (8Kx8)..............................................................................................................".......................... 5156

PRODUCT GUIDE

GENERAL INFORMATIONThe SGS-THOMSON Microelectronics Memoriesdata book is a comprehensive collection of informationon advanced, high density, high speed memoryproducts for specific applications.SGS-THOMSON offers 4 groups of memory products:EPROMs and OTP's, EEPROMs, ROMs andStatic RAMs.EPROMs (Electrically Programmable Read OnlyMemory) and OTP's (One Time ProgrammableRead Only Memory) are non volatile memory componentsfor program storage.SGS-THOMSON Microelectronics has one of thelargest product range to meet your requirements:- all densities from 16K to 1 Megabit.- NMOS or CMOS technology.- Jedec approved footprints for easy upgrades.- UV EPROM in Cerdip package.- One Time Programmable in windowless plasticpackage ideally suited for high volume productionenvironment and surface mounting applications.- very fast programming algorithm.EEPROMS (Electrically Erasable ProgrammableRead Only Memories) embody the fOil range ofEPROM functional advantages plus the added featuresof in-circuit erasability and programmability.SGS-THOMSON range comprehends serial accesspr~ucts, with densities ranging from 256 bit to 2Kbit, including 2-wire bus compatible versions.Static RAM products cover high speed memories,biport devices and Zeropower TimekeeperTMRAMS.• High speed memories with a device density rangeof 4Kbits to 64Kbits and performance from20ns to 55ns.Organizational flexibility (4K x 1, 16K x 1, 4K x 4,64K x 1, 8K x 8) covers a vast range of applications,including large mainframes, high speedcontrollers, communications, graphics displayand workstations.• Biport devices consist of a family of FIFO (First­In-First-Out) buffers. These FIFO's provide an interfacebetween digital information paths with widelyvarying speeds. Each information sourcecan thus operate at its own intrinsic speed, whileresults are processed or distributed at speedsfrom 25ns to ~OOns. The Biport family also includesa range of veritable Dual Port Rams enablingapplications in systems with two or moreprocessors, or with distributed processors, whereseparate computing units must exchange dataat speeds approaching real time.• The Zeropower and Timekeeper RAM familycombines the operating simplicity of conventionbyte-wide SRAM's with the excellent data integrityof Zeropower technology. This integrity isachieved thanks to the use of advanced CMOStechnology and long-life lithium cells. With densitiesfrom 2K x 8 to 8K x 8 and access/cycle timesup to 120ns (150ns for 8K x 8), SGS­THOMSON Zeropower RAMs cover the full rangeof non-volatile needs for all microprocessorbased systems. Thanks to the combined featuresof Zeropower technology with an on-chip realtime clock, the 48T02 Timekeeper offers unparallelednon-volatile performance.9

SELECTION GUIDE ..NMOS UV EPROMPart NumberOrga.Access ICC MAX Temp. PinTimeVecAct St.by Range CountET2716Q 2Kx8 450n5 100mA 25mA 5V ± 5% o to +70°C 24ET2716Q-1 2Kx8 350n5 100mA 25mA 5V ± 10% o to + 70°C 24M2716F1 2Kx8 450n5 100mA 25mA 5V ± 5% o to +70°C 24M2716-1F1 2Kx8 350n5 100mA 25mA 5V ± 10% o to +70°C 24M2716F6 2Kx8 450n5 100mA 25mA 5V ± 5% -40 to +85°C 24M2716-1F6 2Kx8 350n5 100mA 25mA 5V ±10% -40 to +85°C 24M2732AF1 4Kx8 250115 125mA 35mA 5V ± 5% o to + 70°C 24M2732A-2F1 4Kx8 200n5 125mA 35mA 5V ± 5% o to + 70°C 24M2732A"3F1 4Kx8 300n5 125mA 35mA 5V ± 5% o to +70°C 24M2732A-4F1 4Kx8 450n5 125mA 35mA .5V ±. 5% o tp + 70°C 24M2732AF6 4Kx8 250n5 125mA :35mA 5V ± 5% -40 to +85°C 24M2732A-4F6 4Kx8 450n5 125mA 35mA 5V ± 5% -40 to +85°C 24M2764AF1 : 8Kx8 250n5 75mA 35mA 5V ± 5% o to +70 0 C 28M2764A-1F1 8Kx8 180n5 75mA 35mA 5V ± 5% o to + 70°C 28M2764A-2F1 8Kx8 200n5 75mA 35mA 5V ± 5% o to +70 0 C 28M2764A-3F1 8Kx8 300n8 75mA 35mA 5V ± 5% o to +70°C 28 ;M2764A"4F1 8Kx8 450n5 75mA 35mA 5V ± 5% o to + 70°C 28M2764A-18F1 8Kx8 180n5 .• 75mA 35mA 5V ± 10% o to +70°C 28M2764A-20F1 8Kx8 200n5 75mA 35mA 5V ± 100/0 o to + 70°C 28M2764A-25F1 8Kx8 250n5 75mA 35mA 5V ± 10% o to +70 0 C 28M2764A-30F1 8Kx8 300n5 75mA 35mA 5V ± 10% o to +70 0 C 28M2764A-45F1 8Kx8 450n5 75mA 35mA 5V ± 10% o to + 70°C 28M2764AF6 8Kx8 250n5 75mA 35mA 5V ± 5% -40 to +85°0 28M2764A-4F6 8Kx8 450n8 75mA 35mA 5V ± 5% -40 to +85°C 28M27128AF1 16Kx8 250n5 85mA 40mA 5V± 5% o to +70°C 28M27128A-1 F1 16Kx8 150n5 85mA 40mA 5V± 5% o to +70°C 28M27128A-2F1 16Kx8 200n5 85mA 40mA 5V ± 5% o to + 70°C 28M27128A-3F1 16Kx8 300n5 85mA 40mA 5V ± 5% o to +70°C 28M27128A-4F1 16Kx8 450n5 85mA 40mA 5V ± 5% o to + 70°C 28M27128A-20F1 16Kx8 200n5 85mA 40mA 5V ± 10% Oto +70°C 28M27128A-25F1 16Kx8 250n5 85mA 40mA 5V ± 10% o to + 70°C 28M27128A-30F1 16KxB 300n5 85mA 40mA 5V ± 10% o to + 70°C 28M27128A-45F1 16Kx8 450n5 85mA 40mA 5V ± 10% o to + 70°C 28M27128AF6 16Kx8 250n5 85mA 40mA 5V ± 5% -40 to +85°C 28M27128A-4F6 16Kx8 450n5 85mA 40mA 5V ± 5% -40 to +85°C 28M27256F1 32Kx8 250n5 100mA 40mA 5V ± 5% o to +70 0 C 28M27256-1F1 32Kx8 170n5 100mA 40mA 5V ± 5% o to + 70°C 28M27256-2F1 32Kx8 200n5 100mA 40mA 5V ± 5% o to +70°C 28M27256-3F1 32Kx8 300n5 100mA 40mA 5V ± 5% o to +70°C 28M27256-4F1 32Kx8 450n5 100mA 40mA 5V ± 5% o to + 70°C 28M27256-20F1 32Kx8 200n5 100mA 40mA 5V ± 10% o to +70 0 C 28M27256-25F1 32Kx8 250n5 100mA 40mA 5V ± 10% o to +70 0 C 28M27256-30F1 32Kx8 300n5 100mA 40mA 5V ± 10% o to +70 0 C 28M27256-45F1 32Kx8 450n5 100mA 40mA 5V ± 10% o to + 70°C 28M27256F6 32Kx8 250n5 100mA 40mA 5V ± 5% -40 to +85°C 28M27256-4F6 32Kx8 450n5 100mA 40mA 5V ± 5% -40 to +85°C 28M27512F1 64Kx8 250n5 125niA 40mA 5V ± 5% o to + 70°C 28M27512-2F1 64Kx8 200n5 125m'A 40mA 5V ± 5% o to + 70°C 28M27512-3F1 64Kx8 300n5 125mA 40mA 5V ± 5% o to +70 0 C 28M27512-25F1 64Kx8 250n5 125mA 40mA 5V ± 10% o to + 70°C 28M27512-30F1 64Kx8 300n5 125mA 40mA 5V ± 10% o to + 70°C 28M27512F6 64Kx8 250n5 125mA 40mA 5V ± 5% -40 to +85°C 2810

SELECTION GUIDECMOS UV EPROMPart NumberOrga.Access lee MAXTime Act St.byVeeTemp.RangePinCountETC2716Q 2Kx8 4S0ns 10mA 1mA SV ± S% o to + 70°C 24ETC2716Q-1 2Kx8 3S0ns 10mA 1mA SV ± S% o to + 70°C 24ETC2716Q-V 2Kx8 4S0n5 10mA 1mA SV ± S% -40 to +8SoC 24ETC2732Q 4Kx8 4S0n5 10mA 1mA SV ± S% o to + 70°C 24ETC2732Q-3 4Kx8 3S0n5 10mA 1mA SV ± S% o to +70°C 24ETC2732Q-4S-V 4Kx8 4S0n5 10mA 1mA SV ± S% -40 to +8SoC 24TS27C64A-1SXCQ 8Kx8 1 SOns 30mA 1mA SV ± S% o to + 70°C 28TS27C64A-20XCQ 8Kx8 200n5 30mA 1mA SV ± S% o to + 70°C 28TS27C64A-2SXCQ 8Kx8 2S0n5 30mA 1mA SV ± S% o to + 70°C 28TS27C64A-30XCQ 8Kx8 300n5 30mA 1mA SV ± S% o to + 70°C 28TS27C64A-1SCQ 8Kx8 1S0n5 30mA 1mA SV ± 10% o to + 70°C 28TS27C64A-20CQ 8Kx8 200ns 30mA 1mA SV ± 10% o to + 70°C 28TS27C64A-2SCQ 8Kx8 2S0n5 30mA 1mA SV ± 10% o to + 70°C 28TS27C64A-30CQ 8Kx8 300n5 30mA 1mA SV ± 10% o to + 70°C 28TS27C64A-1SVQ 8Kx8 1S0n5 30mA 1mA SV ± 10% -40 to +8SoC 28TS27C64A-20VQ 8Kx8 200n5 30mA 1mA SV ± 10% -40 to +8SoC 28TS27C64A-2SVQ 8Kx8 2S0ns 30mA 1mA SV ± 10% -40 to +8SoC 28TS27C64A-30VQ 8Kx8 300n5 30mA 1mA 5V ± 10% -40 to +8SoC 28TS27C2S6-15XCQ 32Kx8 1S0n5 30mA 1mA SV ± S% o to + 70°C 28TS27C2S6-17XCQ 32Kx8 170n5 30mA 1mA SV ± S% o to + 70°C 28TS27C2S6-20XCQ 32Kx8 200n5 30mA 1mA SV ± S% o to + 70°C 28TS27C2S6-2SXCQ 32Kx8 2S0n5 30mA 1mA SV ± S% o to + 70°C 28TS27C2S6-30XCQ 32Kx8 300ns 30mA 1mA SV ± S% o to + 70°C 28TS27C2S6-17CQ 32Kx8 170n5 30mA 1mA SV ± 10% o to + 70°C 28TS27C256-20CQ 32Kx8 200ns 30mA 1mA SV ± 10% o to + 70°C 28TS27C2S6-25CQ 32Kx8 2S0n5 30mA 1mA SV ± 10% o to + 70°C 28TS27C2S6-30CQ 32Kx8 300n5 30mA 1mA SV ± 10% o to + 70°C 28TS27C2S6-1SVQ 32Kx8 1S0ns 30mA 1mA SV ± 5% -40 to +8SoC 28TS27C2S6-17CQ 32Kx8 170n5 30mA 1mA SV ± 10% -40 to +8SoC 28TS27C2S6-20VQ 32Kx8 200n5 30mA 1mA SV ± 10% -40 to +8SoC 28TS27C2S6-2SVQ 32Kx8 2S0ns 30mA 1mA SV ± 10% -40 to +8SoC 28TS27C2S6-30VQ 32Kx8 300n5 30mA 1mA SV ± 10% -40 to +8SoC 28M27C1024-12XF1 64Kx 16 120n5 SOmA 1mA SV ± S% o to + 70°C 40M27C1024-15XF1 64Kx 16 1S0n5 SOmA 1mA SV ± S% o to + 70°C 40M27C1024-20XF1 64Kx 16 200n5 SOmA 1mA SV ± S% o to + 70°C 40M27C1024-2SXF1 64Kx 16 2S0n5 SOmA 1mA SV ± S% o to + 70°C 40M27C1024-12F1 64Kx 16 120n5 SOmA 1mA SV ± 10% o to + 70°C 40M27C 1 024-1SF1 64Kx 16 1S0n5 SOmA 1mA 5V ± 10% o to + 70°C 40M27C1024-20F1 64Kx 16 200ns SOmA 1mA SV ± 10% o to +70°C 40M27C1024-2SF1 64Kx 16 2S0ns SOmA 1mA SV ± 10% o to + 70°C 40M27C1024-1SXF6 64Kx 16 1S0n5 SOmA 1mA SV ± S% -40 to +8SoC 40M27C1024-20XF6 64Kx 16 200n5 SOmA 1mA SV ± S% -40 to +8SoC 40M27C1024-2SXF6 64Kx 16 2S0n5 SOmA 1mA SV ± 5% -40 to +8SoC 4011

SELECTION GUIDENMOS OTP ROMPart NumberOrga.Access lee MAXTemp. PinTimeVeeAct St.by Range CountST2764A·18XCP 8Kx8 180ns 75mA 35mA 5V ± 5% o to + 70°C 28ST2764A-20XCP 8Kx8 200ns 75mA 35mA 5V ± 5% o to + 70°C 28ST2764A-18CP 8Kx8 180ns 75mA 35mA 5V ± 10% o to + 70°C 28ST2764A·20CP 8Kx8 200ns 75mA 35mA 5V ± 10% o to + 70°C 28ST2764A·25CP 8Kx8 250ns 75mA 35mA 5V ± 10% o to + 70°C 28ST2764A-30CP 8Kx8 300ns 75mA 35mA 5V ± 10% o to + 70°C 28ST27128A·15XCP 16Kx8 150ns 85mA 40mA· 5V ± 5% o to + 70°C 28ST27128A·20XCP 16Kx8 200ns 85mA 40mA 5V ± 5% o to +70°C 28ST27128A·20CP 16Kx8 200ns 85mA 40mA 5V ± 10% o to + 70°C 28ST27128A·25CP 16Kx8 250ns 85mA 40mA 5V ±10% o to + 70°C 28ST27128A·30CP 16Kx8 300ns 85mA 40mA 5V ± 10% o to + 70°C 28ST27256·17XCP 32Kx8 170ns 100mA 40mA 5V ± 5% o to +70oC 28ST27256·20XCP 32Kx8 200ns 100mA 40mA 5V ± 5% o to + 70°C 28ST27256·20CP 32Kx8 200ns 100mA 40mA 5V ± 10% o to +70°C 28ST27256-25CP 32Kx8 250ns 100mA 40mA 5V ± 10% o to + 70°C· 28ST27256·30CP 32Kx8 300ns 100mA 40mA 5V ± 10% o to + 70°C 2812

SELECTION GUIDECMOS OTP ROMPart NumberOrga.AccessTimelee MAXAct St.byVeeTemp.RangePinCountTS27C64A-15CFN 8Kx8 150n5 30mA 1mA 5V ± 10% to x 70°C 32TS27C64A-20CFN 8Kx8 200n5 30mA 1mA 5V ± 10% to + 70°C 32TS27C64A-25CFN 8Kx8 250n5 30mA 1mA 5V ± 10% to + 70°C 32TS27C64A-30CFN 8Kx8 300n5 30mA 1mA 5V ± 10% o to + 70°C 32TS27C64A-15VFN 8Kx8 150n5 30mA 1mA 5V ± 10% -40 to + 85°C 32TS27C64A-20VFN 8Kx8 200n5 30mA 1mA 5V ± 10% -40 to + 85°C 32TS27C64A-25VFN 8Kx8 250n5 30mA 1mA 5V ± 10% -40 to + 85°C 32TS27C64A-30VFN 8Kx8 300n5 30mA 1mA 5V ± 10% -40 to + 85°C 32TS27C64A-15TFN 8Kx8 150n5 30mA 1mA 5V ± 10% -40 to + 105°C 32TS27C64A-20TFN 8Kx8 200n5 30mA 1mA 5V ± 10% - 40 to + 105°C 32TS27C64A-25TFN 8Kx8 250n5 30mA 1mA 5V ± 10% -40 to + 105°C 32TS27C64A-30TFN 8Kx8 300n5 30mA 1mA 5V ± 10% - 40 to + 105°C 32TS27C64A-15CP 8Kx8 150n5 30mA 1mA 5V ± 10% to + 70°C 28TS27C64A-20CP 8Kx8 200n5 30mA 1mA 5V ± 10% to + 70°C 28TS27C64A-25CP 8Kx8 250n5 30mA 1mA 5V ± 10% to + 70°C 28TS27C64A-30CP 8Kx8 300n5 30mA 1mA 5V ± 10% o to + 70°C 28TS27C64A-15VP 8Kx8 150n5 30mA 1mA 5V ± 10% -40 to + 85°C 28TS27C64A-20VP 8Kx8 200n5 30mA 1mA 5V ± 10% -40 to + 85°C 28TS27C64A-25VP 8Kx8 250n5 30mA 1mA 5V ± 10% -40 to + 85°C 28TS27C64A-30VP 8Kx8 300n5 30mA 1mA 5V ± 10% -40 to + 85°C 28TS27C64A-15TP 8Kx8 150n5 30mA 1mA 5V ± 10% -40 to +105°C 28TS27C64A-20TP 8Kx8 200n5 30mA 1mA 5V ± 10% -40 to +105°C 28TS27C64A-25TP 8Kx8 250n5 30mA 1mA 5V ± 10% -40 to +105°C 28TS27C64A-30TP 8Kx8 300n5 30mA 1mA 5V ± 10% -40 to +105°C 28ST27C256-17CFN 32Kx8 170n5 30mA 1mA 5V ± 10% to + 70°C 32ST27C256-20CFN 32Kx8 200n5 30mA 1mA 5V ± 10% to + 70°C 32ST27C256-25CFN 32Kx8 250n5 30mA 1mA 5V ± 10% to + 70°C 32ST27C256-30CFN 32Kx8 300n5 30mA 1mA 5V ± 10% o to + 70°C 32ST27C256-17VFN 32Kx8 170n5 30mA 1mA 5V ± 10% -40 to + 85°C 32ST27C256-20VFN 32Kx8 200n5 30mA 1mA 5V ± 10% -40 to + 85°C 32ST27C256-25VFN 32Kx8 250n5 30mA 1mA 5V ± 10% -40 to + 85°C 32ST27C256-30VFN 32Kx8 300n5 30mA 1mA 5V ± 10% -40 to + 85°C 32ST27C256-17TFN 32Kx8 170n5 30mA 1mA 5V ± 10% -40 to + 105°C 32ST27C256-20TFN 32Kx8 200n5 30mA 1mA 5V ± 10% -40 to + 105°C 32ST27C256-25TFN 32Kx8 250n5 30mA 1mA 5V ± 10% - 40 to + 105°C 32ST27C256-30TFN 32Kx8 300n5 30mA 1mA 5V ± 10% -40 to + 105°C 32ST27C256-17CP 32Kx8 170n5 30mA 1mA 5V ± 10% to + 70°C 28ST27C256-20CP 32Kx8 200n5 30mA 1mA 5V ± 10% to + 70°C 28ST27C256-25CP 32Kx8 250n5 30mA 1mA 5V ± 10% to + 70°C 28ST27C256-30CP 32Kx8 300n5 30mA 1mA 5V ± 10% o to + 70°C 28ST27C256-17VP 32Kx8 170n5 30mA 1mA 5V ± 10% -40 to + 85°C 28ST27C256-20VP 32Kx8 200n5 30mA 1mA 5V ± 10% -40 to + 85°C 28ST27C256-25VP 32Kx8 250n5 30mA 1mA 5V ± 10% -40 to + 85°C 28ST27C256-30VP 32Kx8 300n5 30mA 1mA 5V ± 10% -40 to + 85°C 28ST27C256-17TP 32Kx8 170n5 30mA 1mA 5V ± 10% -40 to + 105°C 28ST27C256-20TP 32Kx8 200n5 30mA 1mA 5V ± 10% -40 to + 105°C 28ST27C256-25TP 32Kx8 250n5 30mA 1mA 5V ± 10% -40 to + 105°C 28ST27C256-30TP 32Kx8 300n5 30mA 1mA 5V ± 10% -40 to + 105°C 2813

SELECTION GUIDENMOS EEPROMPart Number Orga. Frequency lee MAXAct St.byVeeTemp.RangePinCountM8571B1 1 K·bit 125KHz 20mA - 5V ± 10% o to + 70°C 8M8571B6 1 K·bit 125KHz 20mA - 5V ± 10% -40 to +85°C 8M9306B1 256-bit 250KHz 6mA 3mA 5V ± 10% o to +70o·C 8M9306B6 256·bit 250KHz 6mA 3mA 5V ± 10% -40 to +85°C 8M9306M1 256-bit 250KHz 6mA 3mA 5V ± 10% o to + 70°C 8M9306M6 256-bit 250KHz 6mA 3mA 5V ± 10% -40 to +85°C 8M9346B1 1-Kbit 250KHz 6mA 3mA 5V ± 10% o to + 70°C 8M9346B6 1-Kbit 250KHz 6mA 3mA 5V ± 10% -40 to +85°C 8M9346M1 1·Kbit 250KHz 6mA 3mA 5V ± 10% o to + 70°C 14M9346M6 1-Kbit 250KHz 6mA 3mA 5V ± 10% -40 to +85°C 14CMOS EEPROMPart Number Orga. Frequency lee MAXTemp. PinVeeAct St.by Range CountST24C02CP 2-KBIT 100KHz 3mA 0.1mA 5V ± 10% o to + 70°C 8ST24C02VP 2-KBIT 100KHz 3mA 0.1mA 5V ± 10% -40 to +85°C 8TS59C11CP 1-KBIT 250KHz 3mA 0.1mA 5V ± 10% o to + 70°C 8TS59C11VP 1-KBIT 250KHz 3mA 0.1mA 5V ± 10% ~40 to +85°C 8TS93C46CP 1-KBIT 250KHz 3mA 0.1mA 5V ± 10% o to + 70°C 8TS93C46VP 1-KBIT 250KHz 3mA 0.1mA 5V ± 10% -40 to +85°C 8ST93C56 2-KBIT 1MHz 3mA 0.1mA 5V. ± 10% o to + 70°C 8NMOS ROMPart NumberOrga.AccessTimelee MAXAct St.byVeeTemp.RangePinCountM2316H 2Kx8 300ns 70mA - 5V ± 10% o to + 70°C 24M2332/M2333 4Kx8 250ns 70mA - 5V ± 10% o to + 70°C 24M2364 8Kx8 250ns 80mA - 5V ± 10% o to +70°C 24M2365 8Kx8 250ns 70mA - 5V ± 10% o to +70°C 2814

SELECTION GUIDEZEROPOWERPart NumberOrga.Access Icc MaxTime Act St.byVccTemp.RangePinCountBA TTERV BACK-UPMK4Be02AN15 2KxB 150n5 BOmA 3mA 5V o to + 70 0 e 24MK4Be02AN20 2KxB 200n5 BOmA 3mA 5V o to + 70 0 e 24MK4Be02AN25 2KxB 250n5 BOmA 3mA 5V +10% o to +70oe 24MK4Be02AK15 2KxB 150n5 BOmA 3mA 5V -5% o to + 70 0 e 24MK4Be02AK20 2KxB 200n5 BOmA 3mA 5V o to + 70 0 e 24MK4Be02AK25 2KxB 250n5 BOmA 3mA 5V o to + 70 0 e 24TIMEKEEPERMK4BT02B12 2KxB 120n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT02B15 2KxB 150n5 BOmA 3mA 5V o to +70oe 24MK4BT02B20 2KxB 200n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT02B25 2KxB 250n5 BOmA 3mA 5V +10% o to + 70 0 e 24MK4BT02BU12 2KxB 120n5 BOmA 3mA 5V -5% o to + 70 0 e 24MK4BT02BU15 2KxB 150n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT02BU20 2KxB 200n5 BOmA 3mA 5V o to +70oe 24MK4BT02BU25 2KxB 250n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT12B12 2KxB 120n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT12B15 2KxB 150n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT12B20 2KxB 200n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT12B25 2KxB 250n5 BOmA 3mA 5V +10% o to + 70 0 e 24MK4BT12BU12 2KxB 120n5 BOmA 3mA 5V -10% o to + 70 0 e 24MK4BT12BU15 2KxB 150n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT12BU20 2KxB 200n5 BOmA 3mA 5V o to + 70 0 e 24MK4BT12BU25 2KxB 250n5 BOmA 3mA 5V o to + 70 0 e 24ZEROPOWERMK48Z02B12 2KxB 120n5 BOmA 3mA 5V to + 70 0 e 24MK4BZ02B15 2KxB 150n5 BOmA 3mA 5V to +70o e 24MK4BZ02B20 2KxB 200n5 BOmA 3mA 5V to + 70 0 e 24MK4BZ02B25 2KxB 250n5 BOmA 3mA 5V +10% o to +70oe 24MK4BZ02BU12 2KxB 120n5 BOmA 3mA 5V -5% to + 70 0 e 24MK4BZ02BU15 2KxB 150n5 BOmA 3mA 5V o to +70oe 24MK4BZ02BU20 2KxB 200n5 BOmA 3mA 5V to + 70 0 e 24MK4BZ02BU25 2KxB 250n5 BOmA 3mA 5V o to +70o e 24MK4BZ12B12 2KxB 120n5 BOmA 3mA 5V o to + 70 0 e 24MK4BZ12B15 2KxB 150n5 BOmA 3mA 5V to + 70 0 e 24MK4BZ12B20 2KxB 200n5 BOmA 3mA 5V o to +70oe 24MK4BZ12B25 2KxB 250n5 BOmA 3mA 5V +10% o to + 70 0 e 24MK4BZ12BU12 2KxB 120n5 BOmA 3mA 5V -10% o to +70o e 24MK4BZ12BU15 2KxB 150n5 BOmA 3mA 5V to + 70 0 e 24MK4BZ12BU20 2KxB 200n5 BOmA 3mA 5V o to + 70 0 e 24MK4BZ12BU25 2KxB 250n5 BOmA 3mA 5V o to +70o e 24MKI4BZ02B12 2KxB 120n5 BOmA 3mA 5V -40 to +B5°e 24MKI4BZ02B15 2KxB 150n5 BOmA 3mA 5V -40 to +B5°e 24MKI4BZ02B20 2KxB 200n5 BOmA 3mA 5V -40 to +B5°e 24MKI4BZ02B25 2KxB 250n5 BOmA 3mA 5V +10% -40 to +B5°e 24MKI4BZ02BU12 2KxB 120n5 BOmA 3mA 5V -5% -40 to +B5°e 24MKI4BZ02BU15 2KxB 150n5 BOmA 3mA 5V -40 to +B5°e 24MKI4BZ02BU20 2KxB 200n5 BOmA 3mA 5V -40 to +B5°e 24MKI4BZ02BU25 2KxB 250n5 BOmA 3mA 5V -40 to +B5°e 24Note: 1. Letter "U" Inserted In sales type indicates "Underwriters' Laboratories" branding.15

SELECTION GUIDEZERO POWERPart NumberOrga.Access ICC MaxTimeVeeAct St.byTemp.RangePinCountMKI4SZ12B12 2KxS 120n5 SOmA 3mA 5V -40 to +S5°C 24MKI4SZ12B15 2KxS 150n5 SOmA 3mA 5V -40 to +S5°C 24MKI4SZ12B20 2KxS 200n5 SOmA 3mA 5V -40 to +S5°C 24MKI4SZ12B25 2KxS 250n5 SOmA 3mA 5V +10% -40 to +S5°C 24MKI4SZ12BU12 2KxS 120n5 SOmA 3mA 5V -10% -40 to +S5°C 24MKI4SZ12BU15 2KxS 150n5 SOmA 3mA 5V -40 to +S5°C 24MKI4SZ12BU20 2KxS 200n5 SOmA 3mA 5V -40 to +S5°C 24MKI4SZ12BU25 ~KxS 250n5 SOmA 3mA 5V -40 to +S5°C 24MK4SZ0SB15 SKxS 150n5 50mA 3mA 5V o to + 70°C 2SMK4SZ0SB20 SKxS 200n5 50mA 3mA 5V o to + 70°C 2SMK4SZ0SB25 SKxS 250n5 50mA 3mA 5V +10% o to + 70°C 2SMK4SZ0SBU15 SKxS 150n5 50mA 3mA 5V -5% o to + 70°C 2SMK4SZ0SBU20 SKxS 200n5 50mA 3mA 5V o to + 70°C 2SMK4SZ0SBU25 SKxS 250n5 50mA 3mA 5V o to + 70°C 2SMK4SZ1SB15 SKxS 150n5 50mA 3mA 5V o to + 70°C 2SMK4SZ1SB20 SKxS 200n5 50mA 3mA 5V o to + 70°C 2SMK4SZ1SB25 SKxS 250n5 50mA 3mA 5V +10% o to + 70°C 2SMK4SZ1SBU15 SKxS 150n5 50mA 3mA 5V -10% o to + 70°C 2SMK4SZ1SBU20 SKxS 200n5 50mA 3mA 5V o to +70°C 2SMK4SZ1SBU25 SKxS 250n5 50mA 3mA 5V o to + 70°C 2SMK4SZ09B15 SKxS 150n5 50mA 3mA 5V o to + 70°C 2SMK4SZ09B20 SKxS 200n5 50mA 3mA 5V o to + 70°C 2SMK4SZ09B25 SKxS 250n5 50mA 3mA 5V +10% o to + 70°C 2SMK4SZ09BU15 SKx8 150n5 50mA 3mA 5V -5% o to +70°C 2SMK4SZ09BU20 SKxS 200n5 50mA 3mA 5V o to + 70°C 2SMK4SZ09BU25 SKxS 250n5 50mA 3mA 5V o to + 70°C 2SMK4SZ19B15 SKxS 150n5 50mA 3mA 5V o to + 70°C 2SMK4SZ19B20 SKxS 200n5 50mA 3mA 5V o to + 70°C 2SMK4SZ19B25 SKxS 250n5 50mA 3mA 5V +10% o to + 70°C 2SMK4SZ19BU15 SKxS 150n5 50mA 3mA 5V -10% o to + 70°C 2SMK4SZ19BU20 SKxS 200n5 50mA 3mA 5V o to + 70°C 2SMK4SZ19BU25 SKxS 250n5 50mA 3mA 5V o to + 70°C 2SNote: 1. Letter "U" inserted in sales type indicates "Underwriters' Laboratories" branding.16

SELECTION GUIDEFAST STATIC RAMPart NumberOrga.Access Icc MaxTime Act St.byVeeTemp.RangePinCountMK41H66N20 16Kx 1 20ns 120mA - 5V:I: 10% o to +70°0. 20MK41H66N25 16Kx1 25n8 120mA - 5V:I: 10% o to +70°0 20MK41H66N35 16Kx1 35n8 120mA - 5V:I: 10% o to +70°0 20MK41H67N20 16Kx 1 20n8 120mA 10mA 5V:I: 10% o to +70°0 20MK41H67N25 16Kx 1 25n8 120mA 10mA 5V:I: 10% o to +70°0 20MK41H67N35 16Kx1 35n8 120mA 10mA 5V:I: 10% o to +70°0 20MK41H6SN20 4Kx4 20n8 120mA SmA 5V:I: 10% o to +70°0 20MK41H6SN25 4Kx4 25n8 120mA SmA 5V:I: 10% o to +70°0 20MK41H6SN35 4Kx4 35n8 120mA SmA 5V:I: 10% o to +70°0 20MK41H69N2O 4Kx4 20n8 120mA - 5V:I: 10% o to +70°0 20MK41H69N25 4Kx4 25n8 120mA - 5V:I: 10% o to +70°0 20MK41H69N35 4Kx4 35n8 120mA - 5V:I: 10% o to +70°0 20MK41H79N20 4Kx4 ·20n8 120mA 16mA 5V :I: 10% o to +70°0 22MK41H79N25 4Kx4 25n8 120mA 16mA 5V:I: 10% o to +70°0 22MK41H79N35 4Kx4 35n8 120mA 16mA 5V:I: 10% o to + 70°0 22TAGRAMMK41 HSON20 4Kx4 20n8 120mA - 5V:I: 10% o to +7QoO 22MK41 HSON25 4Kx4 25n8 120mA - 5V :I: 10°til o to + 70°0 22MK41 HSON35 4Kx4 35n8 120mA - 5V:I: 10% o to +70°0 22Note: 1. Letter "U" inserted in sales type indicates "Underwiters' Laboratories" branding.17

SELECTION GUIDEBIPORT (DUAL PORT)Part NumberOrga.AccessTimeIcc MAXAct St.byVceTemp.RangePinCountMK4S11N12 S12x9 120n5 SOmA SmA SV ± 10% o to + 70 0 e 28MK4S11N1S S12x9 1S0n5 SOmA SmA SV ± 10% o to + 70 0 e 28MK4S11N20 S12x9 200n5 SOmA SmA SV ± 10% o to + 70 0 e 28FIFOPart NumberOrga.AccessTimelee MaxAct St.byVeeTemp.RangePinCountMK4S01K10 S12x9 100n5 80mA 8mA SV ± 10% o to + 70 0 e 32MK4S01K12 S12x9 120n5 80mA 8mA SV ± 10% o to + 700 e 32MK4S01K1S S12x9 1S0n5 80mA 8mA SV ± 10% o to + 70 0 e 32MK4S01K20 S12x9 200n5 80mA 8mA SV ± 10% o to + 70 0 e 32MK4S01K6S S12x9 6Sn5 80mA 8mA SV ± 10% o to + 70 0 e 32MK4S01K80 S12x9 80n5 80mA 8mA SV ± 10% o to + 70 0 e 32MK4S01N10 S12x9 100n8 80mA 8mA SV ± 10% o to + 70 0 e 28MK4S01N12 S12x9 120n5 80mA 8mA SV ± 10% o to + 70 0 e 28MK4S01N1S S12x9 1S0n8 80mA 8mA SV ± 10% o to + 70 0 e 28MK4S01N20 S12x9 200n8 80mA 8mA SV ± 10% o to + 70 0 e 28MK4S01N6S S12x9 6Sn5 80mA 8mA SV ± 10% o to + 70 0 e 28MK4S01N80 S12x9 80n8 80mA 8mA SV ± 10% o to + 70 0 e 28MK4S03N10 2048x9 100n5 120mA 12mA SV ± 10% o to + 70 0 e 28MK4S03N12 2048x9 120n5 120mA 12mA SV ± 10% o to + 70 0 e 28MK4S03N1S 2048x9 1S0n5 120mA 12mA SV ± 10% o to + 70 0 e 28MK4S03N20 2048x9 200n5 120mA 12mA SV ± 10% o to + 70 0 e 28MK4S03N6S 2048x9 6Sn5 120mA 12mA SV ± 10% o to + 70 0 e 28MK4S03N80 2048x9 80n5 120mA 12mA SV ± 10% o to + 70 0 e 28MK4S0SMN2S 1024xS 1Sn5 100mA - SV ± 10% o to + 70 0 e 24MK4S0SMN33 1024xS 20n8 100mA - SV ± 10% o to +70oe 24MK4S0SMNSO 1024xS 2Sn5 100mA - SV ± 10% o to + 70 0 e 24MK4S0SSN2S 1024xS 1Sn5 100mA - SV ± 10% o to + 70 0 e 20MK4S0SSN33 1024xS 20n5 100mA - SV ± 10% o to + 70 0 e 20MK4S0SSNSO 1024xS 2Sn8 100mA - SV ± 10% o to +70oe 20Note: 1. Letter "U" inserted in sales type indicates "Underwriters' Laboratories" branding.18

12 32Kx8 NMOS M27256FUV EPROMPRODUCTSGS-THOMSONDESCRIPTION2Kx8 NMOSET27160M2716F2Kx8 CMOS ETC271604Kx8NMOS M2732A4Kx8 CMOS ETC2732Q~ 8Kx8 NMOS M2764AF8Kx8CMOS TS27C64AQ16Klt8 NMOS M27128AF16Kx8CMOS -II~i32Kx8CMOS64Kx8 NMOSTS27C256QM27512FAMD FUJITSU HITACHI INTELAM2716AM27322732AAM2764 MBM2764 2764AMBM27C64 HN27C64G 27C64AM27128A MBM27128 HN27128AG 27128A27C128AM27256 MBM27256 HN27256G 27256AM27C256MBM27C256 HN27C256G 27C256AM27512 MBM27512 HN27512G 27512FIIICROatIPTECHNOL. MITSUBISHI NSC NEC(GI)27C6427C128NMC2716BQNMC27C32BQNMC27C640NMC27Cl28QPPD27128D27256 MSM27256K ~PD27256D27C256 M5M27C256K NMC27C256Q PPD27C256M5M27512KOKI SIGNETICS TITMS2516TMS2732ATMS2764TOSHIBATMM2764AD27C64ATMS27128 TMM27128ADTMS27C128MSM27256TMS27256 TMM27256AD27C256FA TMS27C256TMM27512D64Kx8 CMOSAM27C51227C512 M5M27C512AK NMC27C512Q ~PD27C512DTMS27C512.....

~OTP ROMPRODUCTDESCRIPTION8Kx8 NMOS8Kx8 CMOS16Kx8NMOS32Kx8 NMOSMICROCHIPSGS· THOMSON HITACHI INTEL TECHNOL. MITSUBISHI NSC NEC OKI(GI)ST2764AP P2764A M5M2764P pPD2764C MSM2764AZBTS27C64AP/FN P27C64 P27C64 NMC27C64N pPD27C64CST27128AP HN27128AP P27128A pPD27128C MSM27128AZBST27256P HN27256P P27256 P27256 M5M27256P MSM27256AZBSIGNETICS TI TOSHIBA27C64A·NTMS27P64TMM2764APTMS27P128 TMM27128APTMS27P256 TMM27256AP(')::Doenen::Dm" m::DmZ~32Kx8 CMOSST27C256P/FN P27C256 P27C256 M5M27C256 pPD27C256AC- - ---- -- -- -_ .. -_.. -27C256·N TMS27PC256TC54256AP~~tII

VFSRAMPRODUCTDESCRIPTIONSGS-THOMSONCYPRESSMATRAINMOSlOTMOTOROLA NEC FUJITSU(16KX1) MK41H67 CY7C167HM65767IM81403IDT6167AMCM6167 "PD4311 MB81C67(4KX4) MK41H68 CY7C168HM65768IM81423IDT6168AMCM6168 "PD4314 MB81C68(64KX1) MK41H87 CY7C187HM65787IM81600IDT7187MCM6187 "PD4361 MB81C71(8KX8) MK48H64 CYC185HM65641IM81630IDT7164MCM6164 "PD4364 MB81C78~O1ltn~fA© ,!i!~O'":IlIS~ZFIFOPRODUCTDESCRIPTION(512x9)(2KX9)SGS-THOMSONMK4501MK4503lOTIDT7201IDT7202/3CYPRESSDALLASCY7C412D82009CY7C424/9 D82010/1AMD/MMIVTI67C201 -67C202/3 VT2F9~ZERO POWERPRODUCTDESCRIPTION(2KX8)(8KX8)SGS-THOMSONMK48Z02MK48Z08DALLASD81210D81225GREENWICHNCR2NVR8o::tJoenen::tJm"'1'1m::tJmZom

PROCESSES CHARACTERISTICSNMOS EPROMProcess Channel Max.Name Length SpeedVpp(external)MainProductsE1 4 I'm 350 nsE3 1.5 I'm 200 nsE3 1.5 I'm 150 ns25 V21 V12.5 VM2716M2732AM2764AM27128AM27256M27512CMOS EPROMP2 5 I'm 350 ns3E 1.4 I'm 150 nsE4 1.0 I'm 120 ns25 V12.5 V.12.5 V. ETC2716ETC2732TS27C64ATS27C256M27C1024NMOS EEPROMF1 3.5 I'm 250 KHz5VM8571M9306M9346CMOS EEPROM2E2 2.0 I'm 250 KHzF3 1.5 I'm 1 MHz5V5VTS59C11TS93C46ST24C02ST93C56STATIC RAMSTechncilogyChannelLengthMax.SpeedMetal LevelslMemory CellMainproductsCMOS 2.0 I'm 65 nsCMOS 2.0 I'm 20 nsCMOS 2.0 I'm 120 nsCMOS 1.2 I'm 20 nsCMOS 1.2 I'm 150 nsCMOS 1.2 I'm 25 ns1/8T1/8T1/6T2/6T2/6T2/8T.FIFOMK4501MK4503DUAL PORTMK4511ZEROPOWERITIMEKEEPERMK48Z02MK48T02VERY FASTMK41H67MK41H68MK41H80MK48H64'ZEROPOWERMK48Z08FIFOMK4505.22

EPROM DEVICESNMOS UV EPROM23

ET2716M271616K (2K x 8) NMOS UV ERASABLE PROM• 2048 x 8 ORGANIZATION• 525 MW MAX ACTIVE POWER, 132 MW MAXSTANDBY POWER• LOW POWER DURING PROGRAMMING• ACCESS TIME M/ET2716-1, 350ns; M/ET2716,450ns• SINGLE 5V POWER SUPPLY• STATIC-NO CLOCKS REQUIRED• INPUTS AND OUTPUTS TTL COMPATIBLEDURING BOTH READ AND PROGRAMMODES• THREE-STATE OUTPUT WITH OR-TIECAPABILITY• EXTENDED TEMPERATURE RANGE (F6)~~N~U"1Q/FDIP-24(Ceramic Buli's Eye)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe M/ET2716 is high speed 16K UV erasable andelectrically reprogram mabie EPROM ideally suitedfor applications where fast turn around and patternexperimentation are important requirements.The M/ET2716 is packaged in a 24-pin dual-in-linepackage with transparent lid. The transparent lidallows the user to expose the chip to ultraviolet lightto erase the bit pattern. A new pattern can then bewritten into the device by following the programmingprocedure.This EPROM is fabricated with the reliable, highvolume, time proven, N-channel silicon gate technologyX-MOS.A7'veeA6A8A5A9A4vppA3A2AIAOOE(G)00 (Od) °6(06)Al0CE/PGM (E/P)A7 (Q7)0, (01) 05 (05)PIN NAMESAO-A10ADDRESS INPUTS00-07 (00-07) DATA OUTPUTSCElPGM (E/P) CHIP ENABLEIPROGRAMOE(G)OUTPUT ENABLEVppREAD5V, PROGRAM 25VVeePOWER (5V)Vss...GROUNDNote: Symbols in parentheses are proposed JEDEe standard°2(02) 04(04)vss 03(03)June 19881/925

ET2716/M2716BLOCK DIAGRAM~ VPP'5V+-- VCC.5V+-- VSS GNOOATA OUTPUTS (PROGRAM INPUTS)00-0) 100-071.Y GATING16.3B4BIT MATRIXPIN CONNECTION DURING READ OR PROGRAMPIN NAME/NUMBERMODECE/PGMOE(E/P) (a) Vpp Vee OUTPUTS18 20 21 24 9-11,13·17READ VIL VIL 5 5 DOUTPROGRAM Pulsed VIL to VIH VIH 25 5 DIN* Symbols In parentheses are proposed JEOEC standard.ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitTamb Temperature Under B.ias -10to +80 ·C(Extended Temperature Range) (-50 to +95) ·CTstQ Storage Temperature -B!'; to. +,125 ·CVpp Vpp Supply Voltage with Respect to Vss . '. 2B.5V to - 0.3 VYin All Input or Output Voltages with Respect to V ss BVto -0.3 VPo Power Dissipation 1.5 WLead Temperature (Soldering 10 seconds) +300 ·C..Note 1. "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed. Except for "OperatingTemperature Range" they are, not meant to imply that the devices should be operated atthese limits. The table of "ElectricalCharacteristics" provides conditions for actual device operation.2/926

ET2716/M2716~EAD OPERATION)C CHARACTERISTICS(1) TA=O°C to + 70 0 C(S), VCC=5V±5% for M/ET2716, VCC=5V±10% foriII/ET2716-1 Vpp = Vcd3), Vss = OV, (Unless otherwise specified)ValuesSymbol Parameter Test Conditions UnitMin. Typ. Max.ILl Input Current VIN = 5.25V ORVIN = VIL - - 10 p.AILO Output leakage Current VOUT=5.25V, CE/PGM=5V - - 10 p.AIpP1 Vpp Supply Current Vpp=5.25V - - 5 mAICC1 VCC Supply Current (Standby) CE/PGM = VIH, OE = VIL - 10 25 mAICC2 VCC Supply Current (Active) CE/PGM = OE = VIL - 57 100 mAVIL Input low Voltage -0.1 - 0.8 VVIH Input High Voltage 2.0 - VCC+1 VVOH Output High Voltage IOH= -400 p.A 2.4 - - VVOL Output low Voltage IOL=2.1 mA - - 0.45 VAC CHARACTERISTICS TA=O°C to+70oC C(S), VCc=5V±5% for M/ET2716, Vcc=5V±10% forM/ET2716-1 Vpp = Vcd3) , VSS=OV, (Unless otherwise specified).Symbol M/ET2716-1 M/ET2716ParameterTest ConditionsStandard JedecMin. Max. Min. Max.tACC TAVQV Address to Output Delay CE/PGM = OE = Vil - 350 - 450tCE TElQV CE to Output Delay OE=VIL - 350 - 450tOE TGlQV Output Enable to CE/PGM=VIL - 120 - 120Output DelaytOF TGHQZ OE or CE High to CE/PGM=VIL 0 100 0 100(Note 5)Output Hi-ZtOH TAXQX Address to Output Hold CE/PGM = C5E = VIL 0 - 0 -too TEHQZ CE to Output Hi-Z OE=VIL 0 100 0 100UnitnsnsnsnsnsnsCAPACITANCE (4)TA=25°C, f=1 MHzSymbol Parameter Test Conditions Min. Typ. Max.CIN Input Capacitance VIN=OV 4 6COUT Output Capacitance VOUT=OV 8 12Notes 1. VCC must be applied at the same time or before VPP and removed after or at the same time as VPP2. Typical conditions are for operation at: TA = 2SoC, VCC = SV, VPP' = VCC, and VSS = OV3. VPP may be connected to VCC except during program.4. Capacitance is guaranteed bneriodic testing. T A = 2SoC, f = 1 MHz.S. tOF is specified from OE or CE wich ever occurs first. This parameter as only sampled and not 100% tested.S. TA = - 40°C To + 8SoC for the FS version (extended To range).UnitspFpF3/927

ET2716/M2716AC TEST CONDITIONSOutput Load: 1 TIL gate and CL= 100 pFInput Rise and FEllI Times, s20 nsInput pulse. levels: 0045\1 to 2.4VTiming Measurement Reference LevelInputs, Outputs.0.8V arid 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUITI1N9143,3Kn~:~ 1J------1>-----Qf> OUTTEST I :.r: CL=IOOpF.J..HI02AC WAVEFORMS\!rHADORE SSE S )V1lADDRESS VALID. ....,--'I'CE......HIGH Z, .I 'OE(3)'ACC(3)IIIIII\\\\\--' ~2.4)~~-~\ HIGHZV ALiO 0 UTPUT~/I5-6109Not ..:1. Typical values are for T aTllb= 25°C and nominal supply voltage2. This parameter is only sampled and not 1000A> tested.3. OE may be delayed Yl!..to tACe • toE after the falling. edge CE wjthout impaCt on tACC4. toFis specified form OE orCE-whichever occurs first.41928

ET2716/M2716DEVICE OPERATIONThe M/ET2716. has 3 modes of operation in the normalsystem environment. These are shown in Table1.READ MODEThe M/ET2716 read operation requires that OE =VIL, CE/PCM = VIL and that addresses AO-A10have been stabilized. Valid data will appear on theoutput pins after tACC, tOE or tCE times (see SwithchingTime Waveforms) depending on wich is limiting.DESELECT MODEThe M/ET2716 is deselectedllmaking OE = VIH.This mode is independent of CE/PGM and the conditionof the adresses. The outputs are Hi-Z whenOE = VIH. This allows OR-tying 2 or moreM/ET2716's for memory expansion.STANDBY MODE (Power Down)The M/ET2716 may ~owered down to the standbymode by' making CE/PGM = VIH. This is independentof OE and automatically puts the outputsin their Hi-Z state. The power is reduced to 25%(132 mW max) of the normal operating power. VCCand VPP must be maintened at 5V. Access timeat power up remains either tACC or tCE (see SwitchingTime Waveforms).PROGRAMMINGThe M/ET2716 is shipped from SGS-THOMSONcompletelyerased. All bits will be at "1" level (outputhigh) in this initial state and after any full erasure.Table II shows the 3 programming modes.PROGRAM MODEThe M/ET2716 is programmed by introducing "0"s into the desidered locations. This is done 8 bits(a byte) at a time. Any individual address, a sequenceof addresses, or addresses chosen at randommay be programmed. Any or all of the 8 bits associatedwith an address location may be programmedwith a single program pulse applied to the chipenable pin. All input voltage levels including theprogram pulse on chip enable are TTL compatible.The programming sequence is:TABLE I. OPERATING MODES (Vcc=Vpp=5V)MODEPIN NAME/NUMBERCE/PGM OEOUTPUTS(E/P) (G)18 20 9-11,13-17READ VIL VIL DourDESELECT Don'! Care VIH Hi-ZSTANDBY VIH Don'! Care Hi-ZWith Vpp = 25V, VCC = 5V, OE = VIH andCE/PGM = VIL, an address is selected and thedesired data word is applied to the output pins.(VIL = "0" and VIL = "1" for both address anddata). After the address and data signals are stablethe program pin is pulsed from VIL to VIHwith a pulse width between 45 ms and 55 ms.Multiple pulses are not needed but will not causedevice damage. No pins should be left open. A highlevel (VIH or higher) must not be maintained longerthan tpW(MAX) on the program pin during programming.M/ET2716's may be programmed inparallel with the same data in this mode.PROGRAM VERIFY MODEThe programming of the M/ET2716 may be verifiedeither 1 word at a time during the programming(as shown in the timing diagram) or by readin.9 allof the words out at the end of the programming sequence.This can be done with Vpp = 25V (or 5V)in either case. Vpp must be at 5V for all operatingmodes and can be maintained at 25V for all programmingmodes.PROGRAM INHIBIT MODEThe program inhibit mode allows programming severalM/ET2716's simultaneously with different datafor each one by controlling wich ones receive theprogram pulse. All similar inputs of the M/ET2716may be paralleled. Pulsing the program pin (fromVIL to VIH) will program a unit while inhibiting theprogram pulse to a unit will keep it from being programmedand keeping OE = VIH will put its outputsin the Hi-Z state.TABLE II. PROGRAMMING MODES (VCC= 5V)MODEPROGRAMPROGRAM VERIFYPROGRAM INHIBITCE/PGM(E/P)18Pulsed VIL !o VIHVILVILPIN NAME/NUMBEROE Vpp OUTPUTS(G)20 21 9-11,13-17VIH 25 DINVIL 25(5) DourVIH 25 Hi-Z5/929

ET2716/M2716ERASINGThe M/ET2716 is erased by exposure to high intensityultraviolet light through the transparent window.This exposure discharges the floating gateto its initial state through induced photo current.It is recommended that the M/ET2716 be kept outof direct sunlight. The UV content of sunlight maycause a partial erasure of some bits in a relativelyshort period of time.An ultraviolet source of 2537 A yelding a total integrateddosage of 15 watt-seconds/cm2 power ratingis used. The M/ET2716 to be erased shouldbe placed 1 inch away from the lamp and no filtersshould be used. .An eraSure system should be calibrated periodically.The distance from lamp to unit should be maintainedat 1 inch. The erasure time is increased bythe square of the distance (if the distance is doubledthe erasure time goes up by a factor of 4).Lamps lose intensity as they age. When a lamp ischanged, the distance is changed, or the lamp isaged, the system should be checked to make certainfull erasure is occuring. Incomplete erasure willcause symptoms that can be misleading. Programmers,components, and system designs have beenerroneously suspected when incomplete erasurewas the basic: problem.TIMING DIAGRAMPROGRAM MODEADDRESSES VIH ====\-r-:-------'-+------~VIL ==T1"-:----..,....-+--~:__--~ 'fo----VIH===~G VIH ----Jr--t-rtin;:;-:t---1r:-,VIL_ VIH ~-----'---+T2~n.E/p·VIL ======;1fNote: Symbols in parentheses are proposed JEDEC standard6/930

ET2716/M2716PROGRAMMING OPERATIONDC AND OPERATING CHARACTERISTICS (T A = 25°C ± 5°C) (V CC = 5V ± 5%, Vpp = 25V ± 1V)Notes 1 and 2Symbol Parameter Min. Max. UnitsIII Input Leakage Current (Note 3) - 10 p.AVIL Input Low Level -0.1 0.8 VVIH Input High Level 2.0 Vee+ 1 VIcc Vee Power Supply Current - 100 rnAIpPl Vpp Supply Current - 5 rnAIpP2 Vpp Supply Current During - 30 rnAProgramming Pulse (Note 5)AC CHARACTERISTICS (TA=25°C±5°C) (VCC=5V±5%, Vpp=25V±1V) Notes 1, 2 and 6StandardSymbolJedecParameter Min. Typ. Max. UnitstAS TAVPH Address Setup Time 2 - - p'stos TGHPH OE Setup Time 2 - - p'stos TDVPH Data Setup Time 2 - - p'stAH TPLAX Address Hold Time 2 p'stOH TPLGX OE Hold Time 2 - - p'stOH TPLDX Data Hold Time 2 - - p'stOF TGHQZ Chip Disable to Output Float Delay 0 - 100 ns(Note 4)tOE TGLQV Output Enable to Output Delay - - 120 ns(Note 4)tpw TPHPL Program Pulse Width 45 50 55 mstpR TPH1PH2 Program Pulse Rise Time 5 - - nstpF TPL2PL1 Program Pulse Fall Time 5 - - nsNotes 1. vee must be applied at the same time of before VPP and removed after or at the same time as VPP. To prevent damage tothe device it must not be insereted into a board with power applied.2. Care must be taken to prevent overshoot of the VPP supply when switching + 25V3. Q.!I5V " VIN < 5.25V4. eE/PGM = VIL, VPP = vee5. VPP = 26 V6. Transition times ~ 20 ns unless otherwise noted7/931

ET2716/M2716SWITCHING TIME WAVEFORMSADDRESSESRead Cycle (CE/PGM = VILIVIH ~~~~~r-----------\: ,-------VALIDVIL ~~~~fF~ ___________~OUTPUT ENABLEOUTPUTVIH =====:j===~VIL -----t----;.--~~-----'tOEITGLQVI--1T'fJ8v,­VOH-----~H~i.Z~~~~~~~---------\VALIDVOL------------~ _________ IHi·ZRead Cycle (DE = VI L)VIH ~~~~~_r-----------"""\ADDRESSESVALIDVIL :i::i:::a:i:i::i:::a:i~~___________ ~VALIDCHIP ENABLEVIH =====::j::===~VIL -----I-----} __ ~_:_------.J_lTm'"V..,-----f--;HLQV,VOH---------~~--~~~---¥---------~OUTPUT Hi·Z VALID )-.....:H::;i;:;.Z __VOL------------~ ______________ IVIHADDRESSESVILVIHCHIP ENABLEVILVOHOUTPUTVOLVALIDVALID FORCURRENT ADDRESSStandby Power Down Mode (DE = VI L)STANDBYtooITEHQZIHi·Z~VALIDVALID FORCURRENT ADDRESSSTANDBYHi·ZSymbols in parentheses are proposed JEDEC standard8/932

ET2716/M2716ORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageET271SQET271S-Q1M271SF1M271S-1F1M271SFSM271S-1FS450 ns350 ns450 ns350 ns450 ns350 ns5V± 5%5V±10%5V± 5%5V±10%5V± 5%5V±10%to + 70°C DIP-24to + 70°C DIP-24to + 70°C DIP-24o to + 70°C DIP-24-40 to +85°C DIP-24-40 to +85°C DIP-24PACKAGE MECHANICAL DATA24-PIN CERAMIC DIP BULL'S EYEnI'~ ffr1f~4l1.. I- J... I-9.1-_rf- I-.3I' ~ '\FC:fgEjPOSS-B/S010pI: i i :1H I~NOPTIONAL-j.J..~,Dim.mmInchesMin Typ Max Min Typ MaxA 32.30 1.272B 13.05 13.36 0.514 0.526C 3.90 5.08 0.154 0.2000 3.00 0.11801

M2732A32K (4K x 8) NMOS UV ERASABLE PROM• FAST ACCESS TIME:200ns MAX M2732A-2F1250ns MAX M2732AF1/M2732AF6300ns MAX M2732A-3F1450ns MAX M2732A-4F1/M2732A-4F6• 0 TO + 70°C STANDARD TEMPERATURERANGE• -40TO +85°CEXTENDEDTEMPERATURERANGE• SINGLE + 5V POWER SUPPLY• LOW STANDBY CURRENT (35mA MAX)• INPUTS AND OUTPUTS TTL COMPATIBLEDURING READ AND PROGRAM• COMPLETELY STATICFDIP-24(Ceramic Buli's Eye)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe M2732A is a 32,768-bits ultraviolet erasableand electrically programmable read-only memory(EPROM). It is organized as 4,096 words by 8 bitsand manufactured using SGS-THOMSON' N­channel Si-Gate MOS process. The M2732A withits single + 5V power supply and with an accesstime of 200ns, is ideal for use with the high performance+ 5V microprocessors such as the Z8 * ,Z80 * and Z8000 * .The M2732A has an important feature which is theseparate output control, Q!m>ut Enable (OE) fromthe Chip Enable control (CE). The OE control elimitatesbus contention in multiple bus microprocessorsystems.The M2732A also features a standby mode whichreduces the power dissipation without increasingaccess time. The active current is 125 mA whilethe maximum standby current is only 35 mA a 70%saving. The standby modeJ.§.achieved by applyinga TTL-high signal to the CE input.The M2732A is available in a 24-lead dual in-lineceramic package glass lens (frit-seal).A7veeA6A6ASA9A4AllA3A2Al0AlCEAO 0700 0601 0502 0403PIN NAMESAO-Al1 ADDRESS INPUTCECHIP ENABLE INPUTOEOUTPUT ENABLE INPUT00-07 DATA INPUT/OUTPUTJune 1988 1/735

M2732ABLOCK DIAGRAMVcc~GNOc-.­Vpp 0----+-GAIA OUTPUTJO- C7DEOUTPUTBUFFERSyDECODERGATINGAO-A11ADDRESSINPUTSDECODER32768 BtlCELL MATRIX5-6706ABSOLUTE MAXIMUM RATINGSSymbolParameterValueVIAll Input or Output voltages with respect to ground + 6to -0.6Vpp Supply voltage with respect to ground during program +22 to -0.6TambAmbient temperature under bias F1/-2FlI-3F1/-4F1 -10to+80F6/4F6-50to+95Tstg Storage temperature range -65 to + 125UnitVV°C°C°CStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.OPERATING MODES~ - -CE OElVpp Vee OUTPUTSMODE (18) (20) (24) (9-11, 13-17)READ VIL VIL +5 DOUTSTANDBY VIH Don't Care +5 High ZPROGRAM VIL Vpp +5 DINPROGRAM VERIFY VIL VIL +5 DOUTPROGRAM INHIBIT VIH Vpp +5 High Z21736

M2732AREAD OPERATIONDC AND AC CONDITIONSSelection Code F1/- 2F1/-3FlI- 4F1 F6/-4F6Operating Temperature Range o to 70°C -40 to 85°CVee Power Supply (1,2) 5V ±5% 5V ±5%Vpp Voltage (2) Vpp = Vee Vpp = VeeDC AND OPERATING CHARACTERISTICSValuesSymbol Parameter Test ConditionsMin, Typ.(3) Max.UnitIII Input Load Current VIN=5.5V 10 ,..AILO Output Leakage Current VOUT=5.5V 10 ,..Alee1(2) Vee Current Standby CE=VIH OE=VIL 35 rnAlee2(2) Vee Current Active CE=OE=VII 70 125 rnAVIL Input Low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 Vee+ 1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VVOH Output High Voltage IOH= -400,..A 2.4 VAC CHARACTERISTICSSymbolParameterTest M2732A-2 M2732A M2732A-3 M2732A-4ConditionsMin Max Min Max Min Max Min MaxtAee Address to Output Delay CE=OE=VIL 200 250 300 450 nsteE CE to Output Delay OE=VIL 200 250 300 450 nstOE OE to Output Delay CE=VIL 100 100 150 150 nstOF(4) OE High to Output Float CE=VIL 0 60 0 60 0 130 0 130 nstoH Output Hold from Addresses CE=OE= \(IL 0 0 0 0 nsCE or OE WhicheverOccurred FirstUnitCAPACITANCE (4)(T amb = 25°C, f = 1 MHz)Symbol Parameter Test Conditions Min. Typ. Max.Notes:CINI Input Capacltance·excepet OEIVpp VIN=O 4 6 pFCIN2 OENpp Input capacitance VIN=O 20 pFCOUTOutput capacitance.VOUT=O 8 12 pF1. Vec must be applied simultaneously with or before Vpp and removed simultaneously or alter Vpp.2. Vpp may be connected directly to Vcc except during programming. The supply current would then be the sum of Iccand Ipr1'3. Typica values .are for Tamb = 25°C and nominal supply voltages.4. ThiS parameter is only sampled and is not 100% tested31737

M2732AREAD OPERATION (Continued)AC TEST CONDITIONSOutput Load: 100pF + HTL GateInput Rise and Fall Times: ~20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC WAVEFORMSADDRESSES)

M2732APROGRAMMING OPERATION(l) (T amb=25°C ±5°C, Vee(2)=5V ±5%, V pp(2,3)=21V ±O.5V)DC AND OPERATING CHARACTERISTIC:ValuesSymbol Parameter Test ConditionsMin. Typ. Max.UnitILl Input Current (All Inputs) VIN = VIL or VIH 10 p.AVIL Input Low Level -0.1 0.8 VVIH Input High Level 2.0 Vee+ 1 VVOL Output Low Voltage During Verify IOL=2.1 rnA 0.45 VVOH Output High Voltage During Verify IOH= -400 p.A 2.4 Vlee2 Vee Supply Current (Active) 70 125 rnAIpp Vpp Supply Current CE = VIL,OE = Vpp 30 rnAAC CHARACTERISTICSValuesSymbol Parameter Test Conditions UnitMin. Typ. Max.tAS Address Set Up Time 2 p'stOES OE Set Up Time 2 p'stos Data Set Up Time 2 p'stAH Address Hold Time 0 p.StOH Data Hold Time 2 p.StOF Chip Enable to Output Float Delay 0 130 nstov Data valid from CE CE = VIL, OE = VIL 1 p'stpw CE Pulse Width During Programming 45 50 55 mstpRT OE Pulse rise time During Programming 50 nstVR Vpp recovery time 2 p.SNoles:1. SGS guarantees the product only if it is programmed to specifications described herein.2. Vee must be applied simultaneously with or before Vpp and removed simultaneously with or after Vpp. The M2732Amust not be inserted into or removed from a board with Vpp at 21.±.O.5V or damage may occur to the device.3. The maximum allowable voltage which may be applied to the Vpp pin during programming is + 22V. Care mustbe taken when switching the Vpp supply to prevent overshoot exceeding this 22V maximum specification.51739

M2732APROGRAMMING OPERATION (Continued)PROGRAMMING WAVEFORMSPROGRAMPROGRAMVERI FYADDRESSESDATA-~Yt--tDF (o.I3)maxVppOE/VppVILCEVIHVIL5- 670 1NOles: I. All times shown in ( ) are minimum and in psec unless otherwise specified.2. The input liming reference level is IV for VIL and 2V for VIH.3. tOE and tOF are characteristics of the device but must be accomodated by the programmer.PROGRAMMINGCaution: Exceeding 22V on pin (Vpp) will damagethe M2732A.When delivered, and after each erasure, all bits ofthe M2732A are in the "1" state. Data is introducedby selectively programming "D's" into the desiredbit locations. Although only "D's" will beprogrammed, both "1's" and "D's" can be presentedin the data word. The only way to change a "0"to a "1" is by ultraviolet light erasure.The M2732A is in the programming mode when theOElVpp input is at 21V. It is required that a 0.1 /tFcapacitor be placed across OElVpp and ground tosuppress spurious voltage transients which may damagethe device .. The data to be programmed isapplied 8 bits in parallel to the data output pins.The levels required for the address and data inputsare TIl.When the address and data are stable, a 50 ms~active low, TIL program pulse is applied to the CEinput. A program pulse must be applied at eachaddress location to be programmed. You can pro-gram any location at any time - either individually,sequentially, or at random. The program pulsehas a maximum width of 55 msec. The 2732A mustnot be programmed with a DC signal applied to theCE input.Programming of multiple 2732As in parallel withthe same data can be easily accomplished due tothe simplicity of the programming requirements. likeinputs of the paralleled M2732As may be connectedtogether when they are programmed withthe same data. A low level TIL pulse applied tothe CE input programs the paralleled 2732As.PROGRAM INHIBITProgramming of multiple 2732As in parallel withdifferent data is also easily accommLshed. Exceptfor CE, all like inputs (including OElVpp) of theparallel 2732As may be common. A TIL level pro-9.@m pulse applied to a 2732A's CE input withOE£Ypp at 21V will program that 2732A. A high levelCE input inhibits the other 2732As from beingprogrammed.6/740

M2732APROGRAMMING OPERATION (Continued)PROGRAM VERIFYA verify should be performed on the programmedbits to determine that they were correctlyQ!1>grammed.-.Ihe verify is accomplished withOENpp and CE at VIL.ERASURE OPERATIONThe erasure characteristics of the M2732A are suchthat erasure begins when the cels are exposed tolight with wavelengths shorter than approximately4000 Angstroms (A). It should be noted that sunlightand certain types of fluorescent lamps havewavelengths in the 3000-4000 A range. Data showsthat constant exposure to room level fluorescentlighting could erase a typical M2732A in approximately3 years, while it would take approximately1 week to cause erasure when exposed to the directsunlight. If the M2732A is to be exposed to thesetypes of lighting conditions for extended periodsof time, it is suggested that opaque labels be putover the M2732A window to prevent unintentionalerasure.The recommended erasure procedure for theM2732A is exposure to shortwave ultraviolet lightwhich has a wavelength of 2537 Angstroms (A). Theintegrated dose (i.e. UV intensity x exposure time)for erasure should be a minimum of 15 W-sec/cm 2.The erasure time with this dosage is approximately15 to 20 minutes using an ultraviolet lamp with12000 pW/cm 2 power rating. The M2732A shouldbe placed within 2.5 cm of the lamp tubes duringerasure. Some lamps have a filter on their tubeswhich should be removed before erasure.ORDERING INFORMATIONPart Number Access Time Supply Voltage Temp. Range PackageM2732AF1M2732A2F1M2732A3F1M2732A4F1M2732AF6M2732A-4F6250 ns200 ns300 ns450 ns250 ns450 ns5V±5%5V±5%5V±5%5V±5%5V±5%5V±5%to +70°C DIP-24o to +70°C DIP-24o to +70°C DIP-24o to +70°C DIP-24-40 to +85°C DIP-24-40 to +85OC DIP-24PACKAGE MECHANICAL DATA24-PIN CERAMIC DIP BULL:S EYEnr--~fYVYYY Pf~QP-J:!,~.!.,.. 1--"-I--rL-.3C ~ "Ia:IID:3IPOSS·B/SIf0toPI~ II ;1n I~NOPTIONAL-k~,mmInchesDim.Min Typ Max Min l'jp MaxA 32.30 1.Z72B 13.05 13.36 0514 0.526C 390 5D8 0.154 0.2000 3.00 0.11801 (1) l40 0.134E 050 1.78 0.020 0.070a3 27B4 1.100F 2.29 2.79 0.090 0.110G 0.40 055 0.G16 0022I 1.17 1.42 0.046 0.05611 (1) 1.27 152 0.050 0.050l 0.22 0.31 0,009 0.012M 1.52 2.49 0.050 0.098N 1651 la.oo 0.650 0.709P 15.40 15.80 0.806 0.622Q 5.71 0.2250 6.86 736 0.270 0.290Note: 1. Optional see drawing71741

M2764A64K (8K x 8) NMOS UV ERASABLE PROM• FAST ACCESS TIME:180ns MAX M2764A-1FlIM2764A-18F1200ns MAX M2764A-2F1/M2764A-20F1250ns MAX M2764AF1/M2764AF6/M2764A-25F1300ns MAX M2764A-3F1/M2764A-30F1450ns MAX M2764A-4F1/M2764A-4F6/M2764A-45F1• 0 to + 70°C STANDARD TEMPERATURERANGE• -40 to + 85°C EXTENDED TEMPERATURERANGE• SINGLE + 5V POWER SUPPLY• ±10% VCC TOLERANCE AVAILABLE• LOW STANDBY CURRENT (35mA MAX)• TTL COMPATIBLE DURING READ ANDPROGRAM• FAST PROGRAMMING ALGORITHM• ELECTRONIC SIGNATUREDESCRIPTIONThe M2764A is a 65,536-bit ultraviolet erasable andelectrically programmable read only memory(EPROM). It is organized as 8,192 words by 8 bitsand manufactured using SGS-THOMSON' NMOS­E3 process.The M2764A with its single + 5V power supply andwith an access time of 200ns, is ideal for use withhigh performance + 5V microprocessor such as za,zao and Z8000. The M2764A has an important featurewhich is to separate the output control, Q!&ltutEnable(OE) from the Chip Enable control (CE).The DE control eliminates bus contention in mUltiplebus microprocessor systems.The M2764A also features a standby mode whichreduces the power dissipation without increasingaccess time. The active current is 75mA while themaximum standby current is only 35 mA, a 53%saving. The standby mode is achieved by applyinga TTL~high signal to the ~ input. The M2764A hasan "Electronic Signature" that allows programmersto automatically identify device type and pinout.The M2764A is available in a 28-lead dual in-lineceramic package (frit-seal) glass lens.DIP-28(Ceramic Bull's Eye)(Ordering Information at the end of the datasheet)PIN NAMESAO-A12- CEOEPGMN.C.00-07PIN CONNECTIONSVpp ~b VeeAU 2 27 PC'iiA7 26 "c.A6 2sh A8AS 2. ASA4 23 AllA3 22 OEA2 21 AIDAI 20 CEAO 10 19 07001" ••0601 I .2 17 0502 I .3 16 04GND I 14 15 035-6321ADDRESS INPUTCHIP ENABLE INPUTOUTPUT ENABLE INPUTPROGRAMNO CONNECTIONDATA INPUT/OUTPUTJune 1988 111043

M2764ABLOCK DIAGRAMDATA OUTPUT00- 07OUTPUT ENABLECHIP ENABLE ANDPROG. LOGICOUTPUTBUFFERSyDECODERGATINGAO-A12ADDRESSINPUTSDECODER6553681TCELL MATRIX5-6361ABSOLUTE MAXIMUM RATINGSSymbolParameterValuesVI All Input or Output voltages with respect to ground +6.5 to -0.6Vpp Supply voltage with respect to ground +14 to -0.6TambAmbient temperature under bias IF1 -10 to +80IF6-50to+95Tsta Storage temperature range - 65 to +125Voltage on pin 24 with respect to ground + 13.5 to -0.6UnitVV°C°C°CVStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only,and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.OPERATING MODES==--------=SMODE- -PGMVpp Vee OUTPUTSCE OE A9 (11-13,(20) (22) (24) (27) (1) (28) 15-19)READ VIL VIL X VIH Vee Vee DOUTOUTPUT DISABLE VIL VIH X VIH Vee Vee HIGH ZSTANDBY VIH X X X Vee Vee HIGH ZFAST PROGRAMMING VIL VIH X VIL Vpp Vee DINVERIFY VIL VIL X VIH Vpp Vee DOUTPROGRAM INHIBIT VIH X X X Vpp Vee HIGH ZELECTRONIC SIGNATURE VIL VIL VH VIH Vee Vee CODESNOTE: X can be V 1H or V1L2/1044

M2764AREAD OPERATIONDC AND AC CONDITIONSSelection CodeFlI-1FlI- 2F1- 1 BFlI-20F1/- 25F1-3FlI-4F1-30F1/-45FlF6/-4F6Operating Temperature Range o to 70°C o to 70°C -40 to 85°CVee Power Supply (1,2) 5V ±5% 5V ±10% 5V ±5%Vpp Vohage (2) Vpp = Vee Vpp = Vee vpp = VeeDC AND OPERATING CHARACTERISTICSSymbol 'Parameter Test ConditionsValuesMin. Typ.l3) Max.III Input Load Current VIN=5.5V 10 "AILO Output Leakage Current VOUT=5.5V 10 "AIpp1(2) Vpp Current Read Vpp=5.5V 5 mAleel(2) Vee Current Standby CE=VIH 35 rnAlee2(2) Vee Current Active CE=OE=VIL 75 rnAVIL Input Low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 Vee+ 1 VVOL Output Low Voltage IOL=2.1 rnA 0.45 VVOH Output High Voltage IOH = - 400 "A 2.4 VVPP(2) Vpp Read Voltage Vee=5V±0.25V 3.8 Vee VUnitAC CHARACTERISTICSVcc± 5% 2764A·1 2764A·2 2764A 2764A·3 2764A·4Symbol Parameter Vcc±10% 2764A·1B 2764A·20 2764A·25 2764A·30 2764A·45 UnitTest Conditions Min Max Min Max Min Max Min Max Min MaxtAee Address to Output Delay CE=OE=VIL 180 200 250 300 450 nsteE CE to Output Delay OE=VIL 180 200 250 300 450 nstOE OE to Output Delay CE=VIL 65 75 100 120 150 nstOF(4) OE High to Output Float CE=VIL 55 0 55 0 60 0 105 0 130 nstoH Output Hold from Address CE=OE= VIL 0 0 0 0 0 nsCE or OE WhicheverOccurred FirstCAPACITANCE(5)(T am b=25°C, f=1 MHz)Symbol Parameter Test Conditions Min. Typ. Max. UnitCIN Input Capacitance VIN=OV 4 6 pFCOUT Output Capacitance VOUT=OV 8 12 pFNotes:1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or aiter Vpp.2. Vpp may be connected directly to Vce except during programming.The supply current would then be the sum of Icc and IpP1 '3. Typical values are for T 8mb = 25°C and nominal supply voltages.4. This parameter is only sampled and not 100% tested. Output Float is defined as the point where data is no longer driven-seetiming diagram.5. This parameter is only sampled and is not 100% tested.3/1045

M2764AREAD OPERATION (Continued)AC TEST CONDITIONSOutput Load: 100pF + 1TTL GateInput Rise and Fall Times: s 20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUITlN914I 3.3KnDEVICE II UNDER t---t---~o OUTTE5T I =I!:: CL"OOpFs.-S102CL INCLUDES JIG CAPACITANCEAC WAVEFORMSVIHADDRESS E5 ADDRESS VALID)VILaVIHVILI'CEDEVIHV,LI t OE (3)' ACC (3)VIHOUTPUTVILHlGH ZIIII/.\\\\\\vHIGH Z5_6809Notes:1. Typical values are for T amb = 25°C and nominal supply voltage.2. This parameter is only sampled and not 100% tested.3. DE may be delayed up to tACC - tOE after the falling edge CE without impact on tACC'4. tOF is specified from rn= or CE whichever occurs first.4/1046

M2764ADEVICE OPERATIONThe seven modes of operations of the M2764A arelisted in the Operating Modes. A single 5V powersupply is required in the read mode. All inputs areTTL levels except for Vpp and 12V on A9 for ElectronicSignature.READ MODEThe M2764A has two control functions, both ofwhich must be logically satisfied in order to obtaindata at the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection.Assuming that addresses are stable, address accesstime (tAce) is equal to delay from CE to outpu~(tCE). Data ~available at the Q!!!puts after thefailing edge of OE, assuming that CE has been lowand addresses have been stable for at leasttACC-tOE·STANDBY MODEThe M2764A has a standby mode which reducesthe maximum active power current from 75 mA to35 mA. The M2764A is placed in the stan.QQy modeby applying a TTL high signal to the CE input.When in the standby mode, the outputs are in ahigh impedance state, independent of the OE input.OUTPUT OR-TIEINGBecause EPROMs are usually used in largermemory arrays, the product features a 2 line controlfunction which accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus.This assures that all deselected memory devicesare in their low power standby mode and that theoutput pins are only active when data is desiredfrom a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and tran-sient current peaks that are produced by the failingand rising edges of CE. The magnitude of thistransient current peaks is dependent on the outputcapacitive and inductive loading of the device.The associated transient voltage peaks can be suppressedby complying with the two line output controland by properly selected decoupling capacitors.It is recommended that a 1 /LF ceramic capacitorbe used on every device between Vcc and GND.This should be a high frequency capacitor of lowinherent inductance and should be placed as closeto the device as possible. In addition, a 4.7 /LF bulkelectrolytic capacitors should be used betweenVcc and GND for every eight devices. The bulkcapacitor should be located near where the powersupply is connected to the array. The purposeof the bulk capacitor is to overcome the voltagedrop caused by the inductive effects of PCB traces.PROGRAMMINGCaution: exceeding 14V on pin 1 (Vpp) willdamage the M2764A.When delivered, and after each erasure, all bits ofthe M2764A are in the "1" state. Data is introducedby selectively programming "Os" into the desiredbit locations. Although only "Os" will beprogrammed, both "1s" and "Os" can be presentin the data word. The only way to change a "0"to a "1" is by ultraviolet light erasure.The M2764A is in the prQ9!ammin~ mode whenVpp input is at 12.5V and C~ and P M are at TTLlow. The data to be programmed is applied 8 bitsin parallel to the data output pins. The levels requiredfor the address and data inputs are TTL.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsM2764A EPROMs using an efficient and reliablemethod suited to the production programming environment.Programming reliability is also ensuredas the incremental program margin of each byteis continually monitored to determine when it hasbeen successfully programmed. A flowchart of theM2764A Fast Programming Algorithm is shown onthe last page. The Fast Programming Algorithm utilizestwo different pulse types: initial and overprogram.The duration of the initial PGM pulse (s) is one millisecond,which will then be followed by a longeroverprogram pulse of length 3Xmsec. (X is an iterationcounter and is equal to the number of the initialone millisecond pulses applied to a particularM2764A location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte are providedfor before the over program pulse is applied.5/1047

M2764ADEVICE OPERATION (Continued)The,entire seque~ce of program pulses and byteverificatipns is performed at Vcc = 6V andVpp=12.5V. When the Fast Programming cyclehas been completed, all bytes should be comparedto the original datawith Vcc=Vpp=5V. ' .PROGRAM INHIBIT,Programming of multiple M2764~s in parallel withdifferent data is also easily acc~lished. Exceptfor rn:, all like inputs (including OE) of the, parallelM2764A may be common. A TTL low pulse appliedto a M2764A's rn: input, with Vpdt 12.5V, willprogram that M2764A. A high level CE input inhibitsthe other M2764A from being programmed.PROGRAM VERIFYA verify should be performed on the programmedbits to determine that they were correC!!Jyprogrammed. The vrlfy is accomplished with OEat V'L, rn: at V'L, P M at V'H and Vpp at 12.5V.ELECTRONIC., SIGNATUREThe Electronic Signature mode allows the readingout of a binary code from an EPROM that will iden~tify its manUfacturer and type. This mode is intendedfor use by programming equipment for the purposeof automatically matching the device to beprogrammed with its corresponding programmingalgorithm. This mope is functional in the 25°C:l:.5 d C ambient ternperature,Jange that is requiredwhen programming the M2764A. To activate thismode, the programming equipment must force11 ,5V to 12.5V on address line A9 (pin 24) of theM2764A. Two identifier bytes may than be sequen-ced from the device outputs by toggling addressline AO (pin 10) from V'L to V'H' AU other addresslines must be held at V'L during Electronic Signaturemode. Byte 0 (AO = V,J represents the manufacturercode and byte 1 (AO = V,w the device identifiercode. For the SGS-THOMSON M2764A, thesetwo identifier bytes are given below. All identifiersfor manufacturer and device codes will possess oddparity, with the MSB (07) defined as the parity bit.ERASURE OPERATIONThe erasure characteristiC of the M2764A is suchthat erasure begins when the cells are exposed tolight with wavelengths shorter than approximately4000 Angstrom A. It should be noted that sunlightand some type of fluorescent lamps havewavelengths in the 3QOO.4O()() A range. Data showsthat constant exposure to room level fluorescentlighting could erase a typical M2764A in about 3years, while it would take approximately 1 week tocause erasure when expose to direct sunlight. Ifthe M2764A is to be exposed to these type of lightingconditions for extended periods of time, it issuggested that opaque labels be put over theM2764A window to prevent unintentional erasure.The recommended erasure procedure for theM2764A is exposure to short wave ultraviolet lightwhich has wavelength 2537 A. The integrated dose(Le. UV intensity x exposure time) for, erasureshould be a minimum of 15 W-sec/cm2. Theerasure time with this dosage is approximately 15to 20 minutes using an ultraviolet lamp with 12000uW/cm2 power rating. The M2764A should beplaced within 2.5 cm (1 inch) of the lamp tubes duringthe erasure. Some lamps have a filter on theirtubes which should be removed before erasure.ELECTRONIC SIGNATURE MODE~sIDENTIFIER, 'AO, 07 06(10) .. (19) .. (18)MANUFACTURER CODE V'L 0 0OEVICE CODE V'H' 0 0,05 04 03 02 01 00 Hex(17) (16) (15) (13) . , (12) (11) Da ..1 0 0 0 0 0 200 0 1 ,0 0 0 086/1048

M2764APROGRAMMING OPERATION (Tamb=25°C :±5°C, Vee(I)=6V :±O.25V, Vpp(l) = 12.5V :±O.3V)DC AND OPERATING CHARACTERISTICValuesSymbol Parameter Test ConditionsMin. Typ. Max.ILl Input Current (All Inputs) VIN=VIL or VIH 10VIL Input Low Level (All Inputs) -0.1 0.8VIH Input High Level 2.0 VeeVOL Output Low Voltage During Verify IOL=2.1 mA 0.45VOH Output High Voltage During Verify IOH = - 400 p.A 2.4lee2 Vee Supply Current (Program & Verify) 75IpP2 Vpp Supply Current (Program) CE=VIL 50VIO A9 Electronic Signature Voltage 11.5 12.5Unit/LAVVVVmAmAVAC CHARACTERISTICSValuesSymbol Parameter Test ConditionsMin. Typ. Max.tAS Address Setup Time 2toES OE Setup Time 2tos Data Setup Time 2tAH Address Hold Time 0tOH Data Hold Time 2Unitp.S/LS/LSI'Sp.StOFP(4) Output Enable Output Float Delay 0 130tvps Vpp Setup Time 2tves Vee Setup Time 2teES CE Setup Time 2tpw PGM Initial Program Pulse Width (see Note 3) 0.95 1.0 1.05topw PGM Overprogram Pulse Width (see Note 2) 2.85 78.75toE Data Valid from OE 150Notes:I. Vee must be applied simultaneously or before Vpp and removed simultaneously or alter Vpp.2. The length of the overprogram pulse may vary from 2.85msec to 78.75msec as a function of the iteration counter value X.3. In~ial Program Pulse width tolerance Is I msec '" 5%.4. This parameter is only sampled and not I 00% tested.Output Float is defined as the point where data is no longer driven (see timing diagram).nsp.Sp.Sp.Smsmsns7/1049

M2764APROGRAMMING WAVEFORMSV1HADDRESSES;~V1LV1HDATAV 1LVpplAS'os12.5 V5V --.I 'VPSPROGRAMADDRESS STABLEDATA IN STABLEIIrc-~H,LVERIFYC.1 'AHDATA OUT ~ALID ~'DFP6VVee5V-.-I tvesCEV1H1\V1L'CESV1HPGMDEV1LV1HV1Lf-:--'~topw\ ~~ ~5-754 312Notes:1. The input timing reference level is a.BV for a V IL and 2V for a V 1H•2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.3. When programming the M2764A a a.1~F capaCitor is required across Vpp and GROUND to suppress spurious voltage transients whichcan damage the device.8/1050

M2764AFAST PROGRAMMING FLOWCHARTFAilDEVICEFAilEDS·6~819/1051

M2764AORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageM2764A-1FlM2764A-2FlM2764AFlM2764A-3FlM2764A-4FlM2764A-18FlM2764A-20FlM2764A-25FlM2764A-30FlM2764A-45FlM2764AF6M2764A-4F6180 ns200 ns250 ns300 ns450 ns180 ns200 ns250 ns300 ns450 ns250 ns450 ns5V± 5%5V± 5%5V± 50k5V± 5%5V± 5%5V±10%5V±10%5V±10%5V±10%5V±10%5V± 5%5V± 5%to +70·C DIP-28to +70·C DIP-28o to +70·C DIP-28to +70·C DIP-28o to +70·C DIP-28to +70·C DIP-28to- +70·C DIP-28to +70·C DIP-28o to +70·C DIP-28o to +70·C DIP-28-40 to +85·C DIP-28-40 to +85·C DIP-28PACKAGE MECHANICAL DATA28-PIN CERAMIC DIP BULL'S EYEI.~.0M , G F.3mmInchesDim.Min Typ Max Min Typ MaxA 38.10 1.500B 13.05 13.36 0.514 0.526C 3.90 5.08 0.154 0.200D 3.00 0.118E 0.50 1.78 0.020 0.07083 33.02 1.300F 2.29 2.79 0.090 0.110G 0.40 0.55 0.016 0.022I 1.17 1.42 0.046 0.058L 0.22 0.31 0.009 0.012M 1.52 2.49 0.060 0.098N 16.51 18.00 0.650 0.709P 15.40 15.80 0.806 0.622Q 5.71 0.2250 6.86 7.36 0.270 0.2901011052

M27128A128K (16K x 8) NMOS UV ERASABLE PROM• FAST ACCESS TIME:150n8 MAX M27128A-1Fl200n8 MAX M27128A-2Fl/M27128A-20Fl250n8 MAX M27128AF1/M27128AF6/M27128A-25Fl30008 MAX M27128A-3Fl/M27128A-30Fl450n8 MAX M27128A-4Fl/M27128A-4F6/M27128A-45Fl• 0 to + 70°C STANDARD TEMPERATURERANGE• -40 to +85°C EXTENDED TEMPERATURERANGE• SINGLE + 5V POWER SUPPLY• ±10% VCC TOLERANCE AVAILABLE• LOW STANDBY CURRENT (40mA MAX)• TTL COMPATIBLE DURING READ ANDPROGRAM• FAST PROGRAMMING ALGORITHM• ELECTRONIC SIGNATURE... '>/'/}".........,~...... " ...".', .... ..'..... ...,...... ...'...........,.'........'.'.....'~,'............'..........'.·.',..'...·,.,.·.i.i.>;:;·;.28,~':- .... ,::::":,:~,:,',;"-::':::,,::::,';::":;:.i-,:ii'::i:::>':i:':/':::";,FDIP-28(Ceramic Bull's Eye)(Ordering Information at the end of the datasheet)VppPIN CONNECTIONS[~P VeeA12 [2 27 P PGMA 7 [3 26 ~ A 13A6 2SO ASDESCRIPTIONThe M27128A is a 131 ,072-bit ultraviolet erasableand electrically programmable read only memory(EPROM). It is organized as 16,384 words by 8 bitsand mam.lfactured using SGS-THOMSON' NMOS­E3 process.The M27128A with its single + 5V power supplyand with an access time of 200ns, is ideal for usewith high performance + 5V microprocessor suchas Z8, Z80 and Z8000. The M27128A has an importantfeature which is to separate the output control,Ou~ Enable (OE) from the Chip Enablecontrol (CE). The OE control eliminates bus contentionin multiple bus microprocessor systems.The M27128A also features a standby mode whichreduces the power dissipation without increasingaccess time. The active current is 85mA while themaximum standby current is only 40 mA, a 53%saving. The standby mode is achieved by applyinga TTL-high signal to the CE input. The M27128Ahas an "Electronic Signature" that allows programmersto automatically identify device type and pinout.The M27128A is available in a 28-lead dualin-line ceramic package (frit-seal) glass lens.AS24 0 A9A4 23 A11A3 22 DEA2 21 A10A 1 20 ITAO 10 19 0700 11 18 0601 12 17 OS02 13 16 04GNO 14 IS 035-7663PIN NAMESAO-A13 ADDRESS INPUTCECHIP ENABLE INPU~OEOUTPUT ENABLE INPUTPGM PROGRAM00-07 DATA INPUT/OUTPUTJune 1988 1/1053

M27128ABLOCK DIAGRAMVceO--­GND o----to­VppO---DATA OUTPUT00- 07OUTPUT ENABLECHIP ENABLE ANDPROG.LOGICVDECODERAO-AI3ADDRESSINPUTSXDECODER5-7664ABSOLUTE MAXIMUM RATINGSSymbolParameterV, All Input or Output voltages with respect to groundVppTambTst!lSupply voltage with respect to groundAmbient temperatur,e under bias IF1IF6Storage temperature rangeVoltage on pin 24 with respect to groundValues'+,6.25 to - 0.6+ 14 to -0,6-10 to +80- 50 to +95- 65 to +125+ 13.5 to -0.6Stressss above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional oparatlon of the device at these or any other condHions above those indicat!>d in the operational sections of this specificationis not impll!>d' Exposure 10 absolute maximum rating conditions for extend!>d periods may affect device reliability.Unit.VV·C·C·CVOPERATING:::-------::MODESceMODE-PGMVpp Vee OUTPUTSOE AS (11-13,(20) (22) (24) (27) (1) (28) " 15-19)READ V,L V,L X ViH Vee Vee DOl,JTOUTPUT DISABLE V,L V,H X V,H Vee Vee HIGHZSTANDBY V,H X .X X Vee Vee' HIGHZFAST PROGRAMMING V,L , V,H X V,L vpp vee D,NVERIFY V,L V,L X V,H Vpp Vee DOl,JT'PROGRAM INHIBIT V,H X X: X Vpp , Vee HIGHZELECTRONIC SIGNATURE V,L V,L VH ,V,H, ,Vee Vee CODESNOTE: X can be V 1H or V1l211054

M27128AREAD OPERATIONDC AND AC CONDITIONSSelection Code Fl/-1Fl/- 2Fl/-3Fl/- 4Fl - 20Fl/- 25Fl/- 30Fl/- 45Fl F6/-4F6Operating Temperature Range o to 70'C o to 70'C -40 to 85'CVee Power Supply (1,2) 5V ±50Al 5V ±10% 5V ±5%Vpp Voltage (2) Vpp = Vee Vpp = Vee Vpp = VeeDC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsValuesMin. Typ. (3) Max.III Input Load Current VIN=5.5V 10 /LAILO Output Leakage Current VOUT=5.5V 10 /LAIpP1(2) Vpp Current Read Standby Vpp=5.5V 5 mAlee1(2) Vee Current Standby CE=VIH 40 mAlee2(2) Vee Current Active CE=OE=VIL 85 mAVpp=VeeVIL Input Low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 Vee+ 1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VVOH Output High Voltage IOH= -400 /LA 2.4 VVpp(2) Vpp Read Voltage Vee=5V±0.25V 3.8 Vee VUnitAC CHARACTERISTICSVcc± 5% 27128A·l 27128A·2 27128A 27128A·3 27128A·4Symbol Parameter Vcc±10% 27128A·20 27128A·25 27128A·30 27128A·45 UnitTest Conditions Min Max Min Max Min Max Min Max Min MaxtAce Address to Output Delay CE=OE=VIL 150 200 250 300 450 nsteE CE to Output Delay OE=VIL 150 200 250 300 450 nstOE OE to Output Delay CE=VIL 65 75 100 120 150 nstOF(4) OE High to Output Float CE=VIL 55 0 55 0 60 0 105 0 130 nstOH Output..!::!9ld from Address CE=OE= VIL 0 0 0 0 0 nsCE or OE WhicheverOccurred FirstCAPACITANCE(S) (Tamb=25°C, f= 1 MHz)Symbol Parameter Test Conditions Min. Typ. Max. UnitCIN' Input Capacitance VIN=OV 4 6 pFCOUT Output Capacitance VOUT=OV 8 12 pFNoles:1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.2. Vpp may be connected directly to Vcc except during programming.The supply current would then be the sum of ICC and IpP1 '3. Typical values are for T amb = 25°C and nominal supply voltages.4. This parameter is only sampled and not 100% tested. Output Float is defined as the point where data is no longer driven.(See timing diagram).5. This parameter is only sampled and is not 100"Al tested.3/1055

M27128AREAD OPERATION (Continued)AC TEST CONDITIONSOutput Load: 1 OOpF + lTTL GateInput Rise and Fall Times: :;;20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT13V. >O>

M27128ADEVICE OPERATIONThe seven modes of operations of the M27128Aare listed in the Operating Modes. A single 5V powersupply is required in the read mode. All inputsare TTL levels except for Vpp and 12V on A9 forElectronic Signature.READ MODEThe M27128A has two control functions, both ofwhich must be logically satisfied in order to obtaindata at the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (DE) is the output control and shouldbe used to gate data to the output pins, independentof device selection.Assuming that addresses are stable, address accesstime (tACe) is equal to delay from "CE to output(tCE). Data ~available at the Q!,!!puts after thefalling edge of OE, assuming that CE has been lowand addresses have been stable for at leasttACC-tOE·STANDBY MODEThe M27128A has a standby mode which reducesthe maximum active power current from 85 mA to40 mA. The M27128A is placed in the standby modeby applying a TTL high signal to the "CE input.When in the standby mode, the outputs are in ahigh impedance state, independent of the OE input.OUTPUT OR-TIEINGBecause EPROMs are usually used in larger memoryarrays, the product features a 2 line controlfunction which accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE shouldbe made a common connection to all devices inthe array and connected to the READ line from thesystem control bus.This assures that all deselected memory devicesare in their low power standby mode and that theoutput pins are only active when data is desiredfrom a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and tran-sient current peaks that are produced by the faIlingand rising edges of"CE. The magnitude of thistransient current peaks is dependent on the outputcapacitive and inductive loading of the device.The associated transient voltage peaks can be suppressedby complying with the two line output controland by properly selected decoupling capacitors.It is recommended that a 1 p.F ceramic capacitorbe used on every device between Vcc and GND.This should be a high frequency capacitor of lowinherent inductance and should be placed as closeto the device as possible. In addition, a 4.7 p.Fbulk electrolytic capacitors should be used betweenVcc and GND for every eight devices. The bulk capaCitorshould be located near where the powersupply is connected to the array. The purpose ofthe bulk capacitor is to overcome the voltage dropcaused by the inductive effects of PCB traces.PROGRAMMINGCaution: exceeding 13Von pin 1 (Vpp) will damagethe M27128A.When delivered, and after each erasure, all bits ofthe M27128A are in the" 1 " state. Data is introducedby selectively programming "Os" into the desiredbit locations. Although only "Os" will beprogrammed, both "1s" and "Os" can be presentin the data word. The only way to change a "0"to a "1" is by ultraviolet light erasure.The M27128A is in t. he pr.Q9!. ramming mode whenVpp input is at 12.5V and CE and PGM are at TTLlow. The data to be programmed is applied 8 bitsin parallel to the data output pins. The levels requiredfor the address and data inputs are TTL.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsM27128A EPROMs using an efficient and reliablemethod suited to the production programming environment.Programming reliability is also ensuredas the incremental program margin of each bytesis continually monitored to determine when it hasbeen successfully programmed. A flowchart of theM27128A Fast Programming Algorithm is shownon the last page. The Fast Programming Algorithmutilizes two different pulse types: initial and overprogram.The duration of the initial PGM pulse (s) is onemillisecond, which will then be followed by a longeroverprogram pulse of length 3Xmsec. (X is an iterationcounter and is equal to the number of the initialone millisecond pulses applied to a particularM27128A location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte are providedfor before the over program pulse is applied.5/1057

M27128ADEVICE OPERATION (Continued)The entire sequence of program pulses and byteverifications is performed at Vcc = 6V andVpp= 12.5V. When the Fast Programming cyclehas been completed, all bytes should be comparedto the original data with Vcc = Vpp = 5V.PROGRAM INHIBITProgramming of niultiple M27128As in parallel withdifferent data is also easily accq!!)plished. Exceptfor CE, all like inputs (including OE) of the parallelM27128A may be common. A TTL low pulse appliedto a M27128A's CEinput, with Vpp at 12.5V,will program that M27128A. A high level CE inputinhibits the other M27128A from beingprogrammed.PROGRAM VERIFYA verify should be performed on the programmedbits to determine that they were corre@programmed. The verify is accomplished with OEat V1L, CE at V1L, PGM at V1H and Vpp at 12.5V.ELECTRONIC SIGNATUREThe Electronic Signature mode allows the readingout of a binary code from an EPROM that will identifyits manufacturer and type. This mode is intendedfor use by programming equipment for thepurpose of automatically matching the device tobe programmed with its corresponding programmingalgorithm. This mode is functional in the 25°C± 5°C ambient temperature range that is requiredwhen programming the M27128A. To activate thismode, the programming equipment must force11.5V to 12.5V on address line A9 (pin 24) of theM27128A. Two identifier bytes may than be sequen-ced from the device outputs by toggling address lineAO (pin 10) from V1L to V1H. All other address linesmust be held at V1L during Electronic Signaturemode. Byte 0 (AO = V1J represents the manufacturercode and byte 1 (AO = V1H) the device identifiercode. For the SGS-THOMSON M27128A, thesetwo identifier bytes are given below. All identifiersfor manufacturer and device codes will possess oddparity, with the MSB (07) defined as the parity bit.ERASURE OPERATIONThe erasure characteristic of the M27128A is suchthat erasure begins when the cells are exposed tolight with wavelengths shorter than approximately4000 Angstrom A. It should be noted that sunlightand some type of flUorescent lamps havewavelengths in the 3000-4000 A range. Data showsthat constant exposure to room level fluorescentlighting could erase a typical M27128A in about 3years, while it would take approximately 1 week tocause erasure when expose to direct sunlight. Ifthe M27128A is to be exposed to these types oflighting conditions for extended periods of time, itis suggested that opaque labels be put over theM27128A.window to prevent unintentional erasure.The recommended erasure procedure for theM27128A is exposure to short wave ultraviolet lightwhich has wavelength 2537 A. The integrated dose(i.e. UV intenSity x exposure time) for erasureshould be a minimum of 15 W-sec/cm2. Theerasure time with this dosage is approximately 15to 20 minutes using an ultraviolet lamp with 12000uW/cm2 power rating. The M27128A should beplaced within 2.5 cm (1 inch) of the lamp tubes duringthe erasure. Some lamps have a filter on theirtubes which should be removed before erasure.ELECTRONIC SIGNATURE MODE~ IDENTIFIERAO 07 06(10) (19) (18)MANUFACTURER CODE VIL 0 0DEVICE CODE VIH 1 005 04 03 02 01 00 Hex(17) (16) (15) (13) (12) (11) Data..1 0 0 0 0 0 200 0 1 0 0 1 896/1058

M27128APROGRAMMING OPERATION (T amb=25°C ±5°C, Vcc(1)=6V ±O.25V, Vpp(l) = 12.5V ±O.3V)DC AND OPERATING CHARACTERISTICSymbolParameterTest ConditionsValues(See note 1) Min. Typ. Max.UnitIII Input Current (All Inputs) VIN = Vil or VIH 10 p.A.Vil Input Low Level (All Inputs) -0.1 0.8 VVIH Input High Level 2.0 VCC+ 1 VVOL Output Low Voltage During Verify IOl=2.1 mA 0.45 VVOH Output High Voltage During Verify IOH = - 400 p.A. 2.4 VICC2 V ce Supply Current (Program & Verify) 100 mAIpP2 Vpp Supply Current (Program) CE=Vll 50 mAVIO A9 Electronic Signature Voltage 11.5 12.5 VAC CHARACTERISTICSSymbolParameterTest ConditionsValues(See note 1) Min. Typ. Max. UnittAS Address Setup Time 2 1'8tOES OE Setup Time 2 1'8tos Data Setup Time 2 p,StAH Address Hold Time 0 p,StOH Data Hold Time 2 1'8tOFP(4) Output Enable Output Float Delay 0 130 n8tvps Vpp Setup Time 2 1'8tvcs Vce Setup Time 2 1'8tCES CE Setup Time 2 1'8tpw PGM Initial Program Pulse Width (see Note 3) 0.95 1.0 1.05 mstopw PGM Overprogram Pulse Width (see Note 2) 2.85 78.75 mstOE Data Valid from OE 150 nsNotes:1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.2. The length of the overprogram pulse may vary from 2.85msec to 78.75msec as a function of the iteration counter value X.3. Initial Program Pulse width tolerance is lmsec ±5%.4. This parameter is only sampled and not 100% tested.Output Float is defined as the pOint where data is no longer driven (see timing diagram).711059

M27128APROGRAMMING WAVEFORMSIVIHADDRESSES ;==X IePROGRAMVERIFYIADDRESS STABLEJVILlAStAHVIHH,LIDATADATA IN STABLE DATA OUT YALID /VILtos-- ~ tDFP12.5 YVpp5V ~ tyPSVCCITPGMDE6V5V ~tyCSV1H -VIL \tCESV1HVILVIHVIL~~~ ~"topw~5-75J, 312Notes:1. The input timing reference level is O.BV for a VIL and 2V for a VIH.2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.3. When programming the M2712BA a O.l~F capacitor is required across Vpp and GROUND to suppress spurious voltage transients whichcan damage the device.8/1060

M27128AFAST PROGRAMMING FLOWCHARTFAILDEVICEFAILED5-6&819/1061

M27128AORDI:RING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageM27128A-1 F1M27128A-2F1M27128AF1M27128A-3F1M27128A-4F1M27128A-20F1M27128A-25F1M27128A-30F1M27128A-45F1M27128AF6M27128A-4F6150 ns200 ns250 ns300 ns450 ns200 ns250 ns300 ns450 ns250 ns450 ns5V± 5%5V± 5%5V± 5%5V± 5%5V± 5%5V±10%5V±10%5V±10%5V±10%5V± 5%5V± 50/0o to + 70·e DIP-28o to + 70·e DIP-28o to + 70·e DIP-28o to + 70·e DIP-28o to + 70·e DIP-28to + 70·e DIP-28to + 70·e DIP-28to + 70·e DIP-28o to + 70·e DIP-28-40 to +85·e DIP-28-40 to +85·e DIP-28PACKAGE MECHANICAL DATA28-PIN CERAMIC DIP BULL'S EYEmmIncheaDim.Min Typ Max Min Typ MaxA 38.10 1.500B 13.05 13.36 0.514 0.526C 3.90 5.08 0.154 0.200D 3.00 0.118E 0.50 1.78 0.020 0.070e 3 33.02 13.00F 2.29 2.79 0.090 0.110G 0.40 0.55 0.016 0.022I 1.17 1.42 0.046 0.056L 0.22 0.31 0.009 0.012M 1.52 2.49 0.060 0.098N 16.51 18.00 0.650 0.709P 15.40 15.60 0.606 0.622a 5.71 0.2250 6.se 7.36 0.270 0.29010/1.062

M27256256K (32K x 8) NMOS UV ERASABLE PROM• FAST ACCESS TIME:170ns MAX M27256-1F1200ns MAX M27256-2F1/M27256-20F1250ns MAX M27256F1/M27256F6/M27256-25F1300ns MAX M27256-3F1/M27256-30F1450ns MAX M27256-4F1/M27256-4F6/M27256-45F1• 0 to +70°C STANDARD TEMP. RANGE• -40 to +85°C EXTENDED TEMP. RANGE• SINGLE + 5V POWER SUPPLY• ±10% VCC TOLERANCE AVAILABLE• LOW STANDBY CURRENT (40mA MAX)• TTL COMPATIBLE DURING READ ANDPROGRAM• FAST PROGRAMMING ALGORITHM• ELECTRONIC SIGNATUREDESCRIPTIONThe M27256 is a 262, 144-bit ultraviolet erasable andelectrically programmable read only memory(EPROM). It is organized as 32.768 words by 8 bitsand manufactured using SGS-THOMSON' NMOS­E3 process. The M27256 with its single + 5V powersupply and with an access time of 2oons, is idealfor use .with high performance + 5V microproces­!lor such as Z8, Z80 and Z8000. The M27256 hasan important feature which is to separate the outputcontrol, OJ,!Qtut Enable (OE) from the Chip Enablecontrol (CE). The OE control eliminates buscontention in multiple bus microprocessor systems.The M27256 also features a standby mode whichreduces the power dissipation without increasing accesstime. The active current is 100mA while themaximum standby current is only 40 mA, a 60% saving.The standby mode is achieved by applying aTTL-high signal to the CE input. The M27256 enablesimplementation of new, advanced systems withfirmware intensive architectures. The combinationof the M27256's high density, and new advancedmicroprocessors having megabit addressing capabilityprovides designers with opportunities to engineeruser-friendly, high reliability, high-performancesystems. The M27256 large storage capability enablesit to function as a high density software carrier.Entire operating systems, diagnostics, high-levellanguage programs and specialized application softwarecan reside in a M27256 directly on a system'smemory bus. This permits immediate microprocessoraccess and execution of software and eliminatesthe need for time consuming disk accesses anddownloads. The M27256 has an "Electronic Signature"that allows programmers to automatically identifydevice type and pinout.June 1988FDIP-28(Ceramic BUIl's Eye)(Ordering Information at the end of the datasheet)PIN NAMESAO-A14CEOEVppPIN CONNECTIONS~ VeeA,2 1 27 A'4A7 26 A,3A6 25 A8AS 24 A9A4 23 A11A3 22 OEA2 21 A,DA' 20 CEAD 10 19 0700 11 18 060' [12 17 0502 13 16 04GND"15 035- 7576ADDRESS INPUTCHIP ENABLE INPUTOUTPUT ENABLE INPUT00-07 DATA INPUT/OUTPUT1/1063

M27256BLOCK DIAGRAMVeco----­GNOo-­V"" 0-----DA.TA OUTPUTS00-07OUTPUTBUFFERSyDECODER'GATINGAO~A14'ADDRESSINPUTSDECODER262,144811CEll MATRIX5-7571ABSOLUTE MAXIMUM RATINGSSymbolParameterValueVI All input or Output voltages with respect to ground + 6.25 to - 0.6Vpp Supply voltage with respect to ground +14 to -.0,6TambAmbient temperature under bias IF1 -.10 to +80IF6 - 50 to +95Tsta Storage temperature range ~'65 to +,125Voltage on pin ,24 with respect to ground, , + 13.5 to -0.6 VStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Expbsure to absolute maximum rating conditions for extended periods may affect device reliability,UnitV.v·C·C·COPERATING MODES-:::------::SCEVpp Vee OUTPUTSOE A9 AO (11-13,(20) (22) (24) (10) (1) (28)MODE•15-19)READ VIL VIL X X Vee Vee DOUTOUTPUT DISABLE VIL VIH X X Vee .,Vee HIGHZSTANDBY VIH X X X Vee ' Vee HIGH ZPROGRAM VIL VIH X X Vpp Vee DINVERIFY VIH VIL >,< X Vpp Vee DOUTOPTIONAL VERIFY VIL VIL X X Vpp Vee 'DOUTPROGRAM iNHIBiT VIH VIH X X Vpp Vee HIGHZELECTRONIC SiGNATURE VIL VrL VH VIL Vee Vee MAN.CODEVIL VIL VH VIH Vee Vee DEV.CODENOTE: X can be VIH or VIL.VH= .12V ±O.5V211064

M27256READ OPERATIONDC AND AC CONDITIONSSelection Code F1/-1 F1/- 2F11 - 20F1/- 25F1/- 30F1/- 45F1 F6/-4F6-3F1/-4F1Operating Temperature Range o to 70·C o to 70·C -40 to 85·CVCC Power Supply (1,2) 5V ±5% 5V ±10% 5V ±5%Vpp Voltage (2) Vpp = Vcc Vpp = Vcc Vpp = VccDC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsValuesMin. Typ. (3) Max,III Input Load Current VIN=5.5V 10 p.AILO Output Leakage Current VOUT=5.5V Hi p.AIpP1(2) Vpp Current Read Standby Vpp=5.5V 5 mAICC1(2) Vcc Current Standby CE=VIH 20 40 mAICC2(2) VCC Current Active CE=OE=VIL 45 100 mAVpp=VccVIL Input Low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 VCC+ 1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VVOH Output High Voltage IOH = - 400 p.A 2.4 VVpP(2) Vpp Read Voltage Vcc=5V±0.25V 3.8 Vcc VUnitAC CHARACTERISTICSVcc± 5% 27256·1 27256·2 27256 27256·3 27256·4Symbol Parameter Vcc±10% 27256·20 27256·25 27256-30 27256-45 UnitTest Conditions Min Max Min Max Min Max Min Max Min MaxtACC Address to Output Delay CE=OE=VIL 170 200 250 300 450 nstCE CE to Output Delay OE=VIL 170 200 250 300 450 nstOE OE to Output Delay CE=VIL 70 75 100 120 150 nstOF(4) OE High to Output Float CE=VIL 35 0 55 0 60 0 105 0 130 nstOH Output Hold from Address CE-OE- VIL 0 0 0 0 0 nsCE or OE WhicheverOccurred FirstSymbol Parameter Test Conditions Min. Typ. Max. UnitCIN Input Capacitance VIN=OV 4 6 pFCOUT Output Capacitance VOUT=OV 8 12 pFNotea:1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of Icc and IpP1'3. Typical values are for T 8mb = 2S·C and nominal supply voltages. .4. This parameter is only sampled and not 100% tested. Output Float is defined as the point where data is no longer driven-seetiming diagram.5. This parameter is only sampled and not 100% tested.3/1065

M27256READ OPERATION (Continued)AC TEST CONDITIONSOutput Load: 100pF + 1TTL GateInput Rise and Fall Times: :;; 20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT24=>ttT~HI",GH:.;.Z=--__5-6809Notl!S:1, Typical values are for T amb = 25°C and nominal supply voltage,2, This parameter is only sampled and not 100% tested.3, DE may be delayed up to tACC - tOE after the falling edge CE without impact on tACC.4, tOF is specified from DE or CE whichever occurs first4/1066

M27256DEVICE OPERATIONThe eight modes of operations of the M27256 arelisted in the Operating Modes. A single 5V powersupply is required in the read mode. All inputs areTTL levels except for Vpp and 12V on A9 for ElectronicSignature.READ MODEThe M27256 has two control functions, both of whichmust be logically satisfied ill..Qfder to obtain dataat the outputs. Chip Enable (CE) is the power cQntroland should be used for device selection. OutputEnable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming .that addressesare stable, address access time (tACel is equalto delay from CE to output (tCE)' Data is availableat the outputs after the falling edge of OE, assumingthat CE has been low and addresses have beenstable for at least tACC-tOE'STANDBY MODEThe M27256 has a standby mode which reducesthe maximum active power current from 100 mA to40 rnA. The M27256 is placed in the standby modeby applying a TTL high signal to the CE input. Whenin the standby mode, the outputs are in a high impedancestate, independent of the OE input.TWO LINE OUTPUT CONTROLBecause EPROMs are usually used in largermemory arrays, the product features a 2 line controlfunction which accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus. This assures that all deselectedmemory devices are in their low power standbymode and that the Qutput pins are only active whendata is desired from a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and transientcurrent peaks that are produced by the falling andrising edges of CEo The magnitude of this transientcurrent peaks is dependent on the output capacitiveand inductive loading of the device. The associatedtrSlnsient voltage peaks can be suppressedby complying with the two line output control andby properly selected decoupling capacitors. It isrecommended that a 1 pF ceramic capacitor beused on every device between Vcc and GND. Thisshould be a high frequency capacitor of low inherentinductance and should be placed as close tothe device as possible. In addition, a 4.7 ,..F bulkelectrolytic capacitors should be used betweenVcc and GND for every eight devices. The bulkcapacitor should be located near where the powersupply is connected to the array. The purpose ofthe bulk capacitor is to overcome the voltage dropcaused by the inductive effects of PCB traces.PROGRAMMINGCaution: exceeding 13Von pin 1 (Vpp) will damagethe M27256.When delivered,andafter each erasure, all bits ofthe M27256 are in the "1" state. Data is introducedby selectively programming "Os" into the desiredbit locations. Although only "Os" will be programmed,both "1s" and "Os" can be present in the dataword. The only way to change a "0" to a "1" is byultraviolet light erasure. The M27256 is in the progrnmmingmode when Vpp input is at 12.5V andCE and is at TTL low. The data to be programmedis applied 8 bits in parallel to the data output pins.The levels required for the address and data inputsare TTL.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsM27256 EPROMs using an efficient and reliablemethod suited to the production programming environment.Programming reliability is also ensuredas the incremental program margin of each bytesis continually monitored to determine when it hasbeen successfully programmed. A flowchart of theM27256 Fast Programming Algorithm is shown onthe last page. The Fast Programming Algorithm utilizestwo different pulse types: init~and overprogram.The duration of the initial CE pulse (s) isone millisecond, which will then be followed by alonger overprogram pulse of length 3Xmsec. (X isan iteration counter and is equal to the number ofthe initial one millisecond pulses applied to a particularM27256 location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte areprovided for before the over program pulse is applied.The entire sequence of program pulses andbyte verifications is performed at Vcc=6V andVpp =12.5V. When the Fast Programming cyclehas been completed, all bytes should be comparedto the original data with Vcc=Vpp=5V.5/1067

M27256DEVICE OPERATION (Continued)PROGRAM INHIBITProgramming of multiple M27256s in parallel withdifferent data is also easily accoJJJ.Plished. Exceptfor CE, all like inputs (including OE)of the parallelM27256 may be common. A TTL low pulse appliedto a M27256's CE input, with Vp.aEt 12.5V, willprogram that M27256; A high level CE input inhibitsthe other M27256s from being programmed.PROGRAM VERIFYA verify should be performed on the programmedbits to determine that they were correctlyprogrammed. The verify is accomplished with OE atVIL, CE at VIH and Vpp at 12.5V.OPTIONAL VERIFYThe optional verify may be performed instead~the verify mode. It is performed with OE at VIL, CEat VIL (as opposed to the standard verify whic~ hasCE at VIH), and Vpp at 12.5V. The outputs willthree-state according to the signal presented to OE.Th'erefore, all devices with Vpp = 12.5V andOE = \ill.will present data on the bus independentof the CE state. When parallel programming severaldevices which share the common bus, Vpp shouldbe lowered to Vcc (= 6V) and the normal readmode used to execute a program verify.ELECTRONIC SIGNATUREThe Electronic Signature mode allows the readingout of a binary code from an EPROM that will identifyits manufacturer and type. This mode is intendedfor use by programming equipment for the purposeof automatically matching the device to beprogrammed with its corresponding programmingalgorithm. This mode is functional in the 25°C ± 5°Cambient temperature range that is required whenprogramming the M27256. To activate this mode,the programming equipment must force 11.5V to12.5V on address line A9 (pin 24)of the M27256.Two identifier bytes may then be sequenced fromthe device outputs by toggling address line AO(pin 10) from VIL to VIH. All other address linesmust be held at VIL during Electronic Signaturemode. Byte 0 (AO = VIJ represents the manufacturercode and byte 1 (AO = VI H) the device identi.­fier code. For the SGS-THOMSON f\il27256, thesetwo identifier bytes are given below. All identifiersfor manufacturer and device codes will possess oddparity, with the MSB (07) defined as the parity.bit.ERASURE OPERATIONThe erasure characteristic of the M27256 is suchthat erasure begins when the cells are exposed tolight with wavelengths shorter than approximately4000 Angstrom A. It shduld be noted that sunlightand some type of fluorescent lamps havewavelengths in the 3000-4000 A range. Data showsthat constant exposure to room level fluorescentlighting could erase a typical M27256 in about 3years, while it would take approximately 1 week tocause erasure when expose to direct sunlight. Ifthe M27256 is to be exposed to these types of lightingconditions for extended periods of time, it issuggested that opaque labels be put over theM27256 window to prevent unintentional erasure.The recommended erasure procedure for theM27256 is exposure to short wave ultraviolet lightwhich has wavelength 2537·A. The integrated dose(Le. UV intensity x exposure time) for erasureshould be a minimum of 15 W-sec/cm2. Theerasure. time with this dosage is approximately 15to 20 minutes using an ultraviolet lamp with 12000pW/cm2 power rating. The M27256 should beplaced within 2.5 cm (1 inch) of the lamp tubes duringthe erasure. Some lamps have a filter on theirtubes which should be removed before erasure.ELECTRONIC SIGNATURE MODEIDENTIFIER~AO 07 06(10) (19) (18)MANUFACTURER CODE VIL 0 0DEVICE CODE VIH 0 005 04 03 02 01 00 Hex(17) (16) (15) (13) (12) (11) Data1 0 0 0 0 0 200 0 0 1 0 0 046/1068

M27256PROGRAMMING OPERATION (Tamb=25°C ±5°C, V ee(1)=6V ±O.25V, Vpp(1) = 12.5V ±O.3VDC AND OPERATING CHARACTERISTIC:Symbol ParameterTest ConditionsValues(See note 1) Min. Typ. Max.UnitIII Input Current (All Inputs) VIN = VIL or VIH 10 p.AVIL Input Low Level (All Inputs) -0.1 0.8 VVIH Input High Level 2.0 Vee+ 1 VVOL Output Low Voltage During Verify IOL=2.1 mA 0.45 VVOH Output High Voltage During Verify IOH= -400,..A 2.4 Vlee2 Vee Supply Current (Program & Verify) 100 mAIpP2 Vpp Supply Current (Program) CE=VIL 50 rnAVIO A9 Electronic Signature Voltage 11.5 12.5 VAC CHARACTERISTICSTest ConditionsValuesSymbol Parameter Unit(See note 1) Min. Typ. Max.tAS Address Setup Time 2 ~stOES OE Setup Time 2 ~tos Data Setup Time 2 ~tAH Address Hold Time 0 ~stOH Data Hold Time 2 ~stOFP(4) Output Enable Output Float Delay 0 130 nstvps Vpp Setup Time 2 ~tves Vee Setup Time 2 ~tpw CE Initial Program Pulse Width (see Note 3) 0.95 1.0 1.05 mstopw CE Overprogram Pulse Width (see Note 2) 2.85 78.75 mstOE Data Valid from OE 150 nsNot .. :1. Vee must be applied simuRaneously or before Vpp and removed simuRaneously or after Vpp.2. The length of the overprogram pulse may vary from 2.85msec to 78.75msec as a function of the iteration counter value X.3. Initial Program Pulse width tolerance is 1msec *5%.4. This parameter is only sampled and not 100% tested.Output Float is defined as the pOint where data is no longer driven (see timing diagram).7/1069----.-._--

M27256PROGRAMMING WAVEFORMSPROGRAMPROGRAM VERIFV., JV1HADDRESSE S ADDRESS STABLE;XV1L- X'lASIVIHIHIGH Z~~DATA DATA IN STABLE DATA OUT VALIDVIL~1-t--'lOS ~IOFP~12.5 VVPPSV ~IVPSIAHVee6VSV/IvesCEDEVIHV1LVIHVIL~~ 10Etopw~ \~ ---=--5-98,23/1Notes:I. The input liming reference level is O.SV for a V1L and 2V for a V1H.2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.3. When programming the M27256 a O.I~F capaCitor is required across VPP and GROUND to suppress spurious voltage Iransients whichcan damage Ihe device.8/1070

M27256FAST PROGRAMMING FLOWCHARTDEVICEFAILED5·6&819/1071

M27256ORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageM27256-1F1M27256-2F1M27256F1M27256-3F1M27256-4F1M27256-20F1M27256-25F1M27256-30F1M27256-45F1M27256F6M27256-4F6170 ns200 ns250 ns300 ns450 ns200 ns250 ns300 ns450 ns250 ns450 ns5V± 5%5V± 5%5V± 5%5V± 5%5V± 5%5V±10%5V±10%5V±10%5V±10%5V± 5%5V± 5%o to + 70°C DIP-28o to + 70°C DIP-28o to + 70°C DIP-28to + 70°C DIP-28o to + 70°C DIP-28to + 70°C DIP-28to +70°C DIP-28to + 70°C DIP-28o to + 70°C DIP-28-40 to +85°C DIP-28-40 to +85°C DIP-28PACKAGE MECHANICAL DATA28-PIN CERAMIC DIP BULL'S EYEP058·E/4"N-mminchesDim.Min Typ Max Min Typ MaxA 38.10 1.500B 13.05 13.36 0.514 0.526C 3.30 5.08 0.154 0.200j.L D 3.00 0.118E 0.50 1.78 0.020 0.070,3 33.02 1.300F 2.29 2.79 0.090 0.110G 0.40 0.55 0.016 0.022I 1.17 1.42 0.046 0.056L 0.22 0.31 0.009 0.012M 1.52 2.49 0.060 0.098N 16.51 18.00 0.650 0.709P 15.40 15.80 0.606 0.622Q 5.71 0.2250 6.86 7.36 0.170 0.29010/1072

t="= SGS-THOMSONA.., L ~D©[R3@~I1~©'jj'[R3@~D©~M27512512K (64K x 8) NMOS UV ERASABLE PROMPRELIMINARY DATA• FAST ACCESS TIME:200ns MAX M27512-2F1• 0 TO + 70°C STANDARD TEMPERATURERANGE• SINGLE + 5V POWER SUPPLY• LOW STANDBY CURRENT (40mA MAX)• TTL COMPATIBLE• FAST PROGRAMMING• ELECTRONIC SIGNATUREDESCRIPTIONThe M27512 is a 524,288-bit ultraviolet erasable andelectrically programmable read only memory(EPROM). It is organized as 65,536 words by 8 bitsand manufactured using SGS-THOMSON' NMOS­E3 process. The M27512 with its single +5V powersupply and with an access time of 2oons, is idealfor use with high performance + 5V microprocessorallowing full speed operation without the additionof performance-degrading WAIT states. TheM27512 has an important feature whiCh isjQ..separatethe output control, Output....!;,nable (OENpp)from the Chip Enable control (CE). The OENppcontrol eliminates bus contention in multiple bus microprocessor systems. The M27512 also featuresa standby mode which reduces the power dissipationwithout increasing access time. The active currentis 125mA while the maximum standby currentis only 40 mA, a 70% saving. The standby modeis achieved by applying a TTL-high signal to the CEinput. The M27512 enables implementation of new,advanced systems with firmware intensive architectures.The combination of the M27512s high density,and new advanced microprocessors havingmegabit addressing capability provides designerswith opportunities to engineer user-friendly, high reliability,high-performance systems. The M275121argestorage capability enables it to function as a highdensity software carrier. Entire operating systems,diagnostics, high-level language programs and specializedapplication software can reside in a M27512directly on a system's memory bus. This permits immediatemicroprocessor access and execution ofsoftware and eliminates the need for time consumingdisk accesses and downloads. The M27512 has an"Electronic Signature" that allows programmers toautomatically identify device type and pinout. TheM27512 is available in a 28-lead dual in-line ceramicpackage glass lens (frit seal).June 1988~,~I'/jli"FDIP-28(Ceramic Bull's Eye)(Ordering Information at the end of the datasheet)PIN NAMESAO-A15CEOENppPIN CONNECTIONSA1S ~ ~ VeeA12 27 A14A7 26~ A13A6 25 ASAS 24 A9A4 23 AllA3 22 OE/VppA2 21 Al0Al 20 CEAO 10 19 0700 11 18 0601 r 12 17 0502 13 16 04GNO [14 15 035·157SADDRESS INPUTCHIP ENABLE INPUTOUTPUT ENABLE INPUT00-07 DATA INPUT/OUTPUT1/1573

M27512BLOCK DIAGRAMVee o-----?GNOO---DATA OUTPUTS00-07CEiiE.CEAND PROGRAMLOGICOUTPUTBUFFERSVDECOOERGATINGAO-A1SADDRESSINPUTSDECODER524.288CELL MATRIX5-7580ABSOLUTE MAXIMUM RATINGSSymbolParameterValueVI All Input or Output voltages with respect to ground + 6.5 to - 0.6Vpp Supply voltage ·with respect to ground +14 to - 0.6Tamb Ambient temperature under bias IF1 -10 to + 80IF6 -50 to + 95TstQ Storage temperature range -65 to. + 125Voltage on pin 24 with respect to ground + 13.5 to -0.6UnitVV°C°C°CVStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.OPERATING MODES-=---------:S CE OUTPUTSOElVpp A9 AO Vee (11-13,.'MODE(20) (22) (24) (10) (28) 15·19)READ VIL VIL X X Vee bOUTOUTPUT DISABLE VIL VIH X X Vee HIGH ZSTANDBY VIH X X X Vee HIGHZPROGRAM VIL Vpp X X Vee DiNPROGRAM INHIBIT VIH Vpp X X Vee HIGHZELECTRONIC SIGNATURE VIL VIL VH VIL Vee MAN.CODEVIL VIL VH VIH Vee DEV.CODENOTE: X car> ba V,H or V,l211574

M27512READ OPERATIONDC AND AC CONDITIONSSelection Code FlI-2FlI-3FlI - 25FlI- 30F1 F6Operating Temperature Range o to 70·C o to 70·C -40 to 85·CVcc Power Supply (1,2) 5V ±5% 5V ±10% 5V±5%Vpp Voltage (2) Vpp=Vcc Vpp=Vcc Vpp=VccDC AND OPERATING CHARACTERISTICSValuesSymbol Parameter Test ConditionsMin. Typ. (2) Max.UnitIII Input load Current VIN=5.5V 10 ~ILO Output leakage Current VOUT=5.5V 10 ~ICCI Vcc Current Standby CE=VIH 20 40 rnAICC2 VCC Current Active CE=OENpp=VIL 90 125 rnAVIL Input low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 VCC+ 1 VVOL Output low Voltage IOL=2.1 mA 0.45 VVOH Output High Voltage IOH= -400 p.A 2.4 VAC CHARACTERISTICSVcc± 5% 27512·2 27512 27512·3Symbol Parameter Vcc±10% 27512·25 27512·30 UnitTest Conditions Min Max Min Max Min MaxtACC Address to Output Delay CE = OENpp = VIL 200 250 300 nsteE CE to Output Delay OENpp=VIL 200 250 300 nstoE OENpp to Output Delay CE=VIL 75 100 120 nstOF(3) OE High to Output Float CE=VIL 0 55 0 60 0 105 nstOH Output Hold from Address CE or CE = OENpp = VIL 0 0 0 nsOE Whichever Occurred FirstCAPACITANCE(4) (Tamb=25°C, f= 1 MHz)Symbol Parameter Test Conditions Min. Typ. (2) Max. UnitCIN Input Capacitance VIN=OV 4 6 pFCOUT Output Capacitance VOUT=OV 8 12 pFNotes:1. vee must be applied simultaneously or before OElVpp and removed simultaneously or after OENpp.2. Typical values are for T amb = 25°C and nominal supply voltages. .3. This parameter is only sampled and not 100% tested. Output Float is defined as the point where data is no longer driven-seetiming diagram.4. This parameter is only sampled ,and not 100% tested.3/1575

M27512AC TEST CONDITIONSOutput Load: 100pF + 1TIL GateInput Rise and Fall Times: s 20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT>.2.4=X 2b 20>CTEST POINTS

M27512DEVICE OPERATIONThe six modes of operations of the M27512 are listedin the Operating Modes. A single 5V power supplyis required in the read mode. All inputs are TTLlevels except for OE/vpp and 12Von A9 for ElectronicSignature.READ MODEThe M27512 has two control functions, both of whichmust be logically active in order to obtain data atthe outputs. Chip Enable (CE) is the power controland should be used for device selection. OutputEnable (OE/Vpp) is the output control andshould be used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, the address access time (tAcclis equal to the delay from (;E to output (tccl. Datais available at the outputs after dela~ tOE fromthe falling edge of OE, assuming that CE has beenlow and addresses have been stable for at leasttACC-tOE'STANDBY MODEThe M27512 has a standby mode which reducesthe maximum active power current from 125 mAto 40 mAo The M27512 is placed in the standbymode by applying a TTL high signal to the CE input.When in the standby mode, the outputs arein a high impedance state, independent of theDE/Vpp input.TWO LINE OUTPUT CONTROLBecause EPROMs are usually used in largermemory arrays; the product features a 2 line controlfunction which accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE/vpp should bemade a common connection to all devices in thearray and connected to the READ line from the systemcontrol bus. This assures that all deselectedmemory devices are in their low power standbymode and that the output pins are only active whendata is desired from a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and transientcurrent peaks that are produced by the failingand rising edges of (;E. The magnitude of thistransient current peaks is dependent on the outputcapacitive and inductive loading of the device.The associated transient voltage peaks can be suppressedby complying with the two line output con-trol and by properly selected decoupling capacitors.It is recommended that a 1 /LF ceramic capacitorbe used on every device between Vee andGND. This should be a high frequency capacitorof low inherent inductance and should be placedas close to the device as possible. In addition, a4.7 /LF bulk electrolytic capacitor should be usedbetween Vee and GND for every eight devices.The bulk capacitor should be located near wherethe power supply is connected to the array. Thepurpose of the bulk capacitor is to overcome thevoltage drop caused by the inductive effects of PCBtraces.PROGRAMMINGCaution: exceeding 14Von pin 22 (OENpp) willpermanently damage the M27512.When delivered, and after each erasure, all bits ofthe M27512 are in the "1" state. Data is introducedby selectively programming "Os" into the desiredbit locations. Although only "Os" will beprogrammed, both "1s" and "Os" can be presentin tile data word. The only way to change a "0"to Ii "1" is by ultraviolet light erasureJ.he M27512is in the programming mode when OENpp inputis at 12.5V and (;E is at TTL-low. The data to beprogrammed is applied 8 bits in parallel to the dataoutput pins. The levels required for the address anddata inputs are TTL. The M27512 can usePRESTO· Programming Algorithm that drasticalyreduces the programming time (typically less than50 seconds) nevertheless to achieve compatibilitywith all programming equipments, standard FASTProgramming Algorithm can be used as well.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsM27512 EPROMs using an efficient and reliablemethod suited to the production programming environment.Programming reliability is also ensuredas the incremental program margin of each byteis continually monitored to determine when·it hasbeen successfully programmed. A flowchart of theM27512 Fast Programming Algorithm is shown inthe next page. The Fast Programming Algorithmutilizes two different pulse types: initial and overprogram.The duration of the initial CE pulse (s) isone millisecond, which will then be followed by alonger overprogram pulse of length 3X msec. (Xis an iteration counter and is equal to the numberof the initial one millisecond pulses applied to a particularM27512 location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte areprovided for before the over program pulse is applied.The entire sequence .2!.Jlrogram pulses isperformed at Vee =6Vand OENpp =12.5V (byteverifications at Vee = 6V and OENpp = VII). Whenthe Fast Programming cycle has been completed,all bytes should be compared to the original datawith Vee = 5V.5/1577

M27512DEVICE OPERATIONS (Continued)FAST PROGRAMMING ALGORITHM FLOW CHARTFAILDEVICEFAILED5·6\816/1578

M27512DEVICE OPERATION (Continued)PRESTO PROGRAMMING ALGORITHMPRESTO Programming Algorithm allows to programmthe whole array with a guaranteed margin,in a typical time of less than SO seconds (to be comparedwith 283 seconds for the Fast algorithm).This can be achieved with SGS-THOMSONM27512 due to several design innovations describedin next paragraph to improve programming efficiencyand to bring adequate margin for reliability.Before starting the programming the internal MAR­GIN MODE" circuit is set in order to guarantee thateach cell is programmed with enough margin. Thena sequence of SOO microseconds program pulsesare applied to each byte until a correct verify occurs.No overprogram pulses are applied since theverify in MARGIN MODE provides the necessarymargin to each programmed cell. PRESTO programmingalgorithm is supported on the full lineof DATA 1/0 programmers,for the most popular productionequipments the firmware revision are:- Series 1000: revision V08.1- Mode 120 A and 121 A: revision V14.1PRESTO PROGRAMMABLE ALGORITHM FLOW CHART(1 )(2 )INCREMENT ADDRESSS~10571Notes: 1. vee must be mantained at 6V during the whole programming algorithm between set and reset MARGIN MODE operations.A drop of Vee below 4V could reset the internal MARGIN MODE flip-flop giving place to insufficient programming margins.2. See MARGIN MODE set and reset waveforms.7/1579

M27512DEVICE OPERATION (Continued)MARGIN MODE SET AND RESET WAVEFORMS6VVee .J5VA8A9VIH.JVIl"12 VVIl;l2.SVOE IVppVIl;tAS9CfVIHVILtAS10 tAH10Al0VIHVIL5-10575Notes: I. Other addresses are don't care2. Set MARGIN MODE AIO=VIH, Reset MARGIN MODE AtO=VILMARGIN MODE AC CHARACTERISTICSValuesSymbol Parameter Test Conditions UnitMin. Typ. Max.tASIO Al0 Set Up Time 1 p,stAHIO A 10 Hold Time 1 p,stVPH Vpp Hold Time 2 p,stvps Vpp Set Up Time 2 p,stAS9 A9 Set up Time 2 p,StAH9 A9 Hold Time 2 p,s811580

M27512DEVICES OPERATION (Continued)PROGRAM INHIBITProgramming of multiple M27512s in parallel withdifferent data is also easily accQIDPlished. Exceptfor~, all like inputs (including OENpp) of the parallelM27512 may be common. A TTL low level pulseapplied to a M27512's ~ input, with OENppat 12.5V, will program that M27512. A high level~input inhibits the other M27512s from being programmed.PROGRAM VERIFYA verify (read) should be performed on the programmedbits to determine that they were corre~ programmed.The verify is accomplished with OENppand CE at VIL. Data should be verified tov after thefalling edge of CEoELECTRONIC SIGNATUREThe Electronic Signature mode allows the readingout of a binary code from an EPROM that will identifyits manufacturer and type. This mode is intendedfor use by programming equipment for thepurpose of automatically matching the device tobe programmed with its corresponding programmingalgorithm. This mode is functional in the 25°C±5°C ambient temperature range that is requiredwhen programming the M27512. To activate thismode, the programming equipment must force11.5V to 12.5V on address line A9 (pin 24) of theM27512. Two identifier bytes may then be sequencedfrom the device outputs by toggling addressline AO (pin 10) from VIL to VIH. All other addresslines must be held at VIL during Electronic Signa-ture mode, except for A14 and A15 which shouldbe held high. Byte 0 (AO = VILl represents the manufacturercode and byte 1 (AO = VI H) the deviceidentifier code. For the SGS M27512, these twoidentifier bytes are given here below. All identifiersfor manufacturer and device codes will possess oddparity, with the MSB (07) defined as the parity bit.ERASURE OPERATIONThe erasure characteristic of the M27512 is suchthat erasure begins when the cells are exposed tolight with wavelengths shorter than approximately4000 Angstrom A.. It should be noted that sunlightand some type of fluorescent lamps have wavelengthsin the 3000-4000 A range. Data shows thatconstant exposure to room level fluorescent lightingcould erase a typical M27512 in about 3 years,while it would take approximately 1 week to causeerasure when expose to direct sunlight. If theM27512 is to be exposed to these types of lightingconditions for extended periods of time, it is suggestedthat opaque labels be put over the M27512window to prevent unintentional erasure. The recommendederasure procedure for the M27512 isexposure to short wave ultraviolet light which haswavelength 2537 A.. The integrated dose (Le. UVintensity x exposure time) for erasure should be aminimum of 15 W-sec/cm2• The erasure time withthis dosage is approximately 15 to 20 minutes usingan ultraviolet lamp with 12000 uW/cm2 power rating.The M27512 should be placed within 2.5 cm(1 inch) of the lamp tubes during the erasure. SQmelamps have a filter on their tubes which shouldbe removed before erasure.ELECTRONIC SIGNATURE MODE~sIDENTIFIERAO 07 06(10) (19) (18)MANUFACTURER CODE VIL 0 0DEVICE CODE VIH 0 005 04 03 02 01 00 Hex(17) (16) (15) (13) (12) (11) Data1 0 0 0 0 0 200 0 1 1 0 1 00Noie: A9=12V :O.S\(; A1·AB, Al0·A13, CE, OENpp=V,L; A14, A1S=V,H9/1581

M27512PROGRAMMING OPERATION (T amb=25°C ::I:5°C, Vee(1)=6V d::O.25V, OENpp(l)= 12.5V ::I:O.5V)DC AND OPERATING CHARACTERISTIC:SymbolParameterTest ConditionsValues(See note 1) Min. Typ. Max.UnitIII Input Current (All Inputs) VIN = VIL or VIH 10 pAVIL Input Low Level (All Inputs) -0.1 0.8 VVIH Input High Level 2.0 Vee + 1 VVOL Output Low Voltage During Verify IOL=2.1 rnA 0.45 VVOH Output High Voltage During Verify 10H z -400 pA 2.4 Vlee2 Vee Supply Current 150 rnAIpP2 VPP Supply Current (Program) CE=VIL 50 rnAVIO A9 Electronic Signature Voltage 11.5 12.5 VAC CHARACTERISTICSSymbolParameterTest ConditionsValues(See note 1) Min. Typ. Max. UnittAS Address Setup Time 2 p.StOES OENpp Setup Time 2 ,.stoEH OENpp Hold Time 2 ,.stos Data Setup Time 2 p.StAH Address Hold Time 0 ,.stOH Data Hold Time 2 p.StOFP(4) Output Enable Output Float Delay 0 130 ns:tves Vee Setup Time 0 ,.stpW(3) CE Initial Program Pulse Width 0.95 1.0 1.05 mstOPW(2) CE Overprogram Pulse Width 2.85 78.75 mstov Data Valid from CE 1 nstVR OENpp Recovery Time 2 ,.stpRTOENpp Pulse Rise Time DuringProgramming50 nsNotes:1. Vce musl be ~pplied simultaneously or before OENpp and rEimoved simultaneously or after l5E'Npp.2. The length of the overprogram pulse may vary from 2.85msec to 78.7Smsec as a function of the iteration counter value X.3. Initial Program Pulse width tolerance is lmsEiC =5%.4. This parameter is only sampled .and not 100% tested. .Output Float is defined as the point where data is no longer driven (se9 timing diagram).10/1582

M27512PROGRAMMING WAVEFORMSt~lASADDRESS STABLELDATA------

M27512M27512 DESIGN INNOVATIONS FOR AN EFFI­CIENT PROGRAMMING PRESTOM27512 includes several design innovations to obtaina very efficient programming:- during programming the word line voltage isbootstrapped over the Vpp voltage by about 2V- the bit line voltage is regulated at the optimumvalue for fast write.This allows a reduction of about one order of magnitudein the programming time. The programmingis also independent of the Vpp voltage (fromabout 10V to 14V). The Vee voltage (6V during theAlgorithm) influences the programming speed sincethe cell drain voltage regulation uses Vee as a reference.The sensing scheme is also innovative in SGS­THOMSON M27512. The conventional sensingcompares the addressed cell within the memory arraywith a reference cell (usually one reference cellfor each word line) as shown in figure 1.Figure 1. Conventional Sensing Schematicteristics of the erased and the written cell in thememory array the "virtual" reference cell currentcan be drawn.The "virtual" reference cell current is the currentof the reference cell divided by the ratio betweenthe impedence of the left side loads and the. impedenceof the right side loads (usually the ratio rangesfrom 2 to 5),The figure 2 illustrates very well the dependanceof Vee (voltage on the addressed word line) on thethreshold shift of the cell: the sensing of a writtencell will not be correct where the "virtual" referencecell characteristic crosses and stays below the writtenceli characteristic (Vee max).The dependance of Vee max on the threshold shiftof a written cell can be illustrated as in figura 3,where the different lines are for different ratios betweenthe impedance of the loads.Figure 2 - Current relationship of reference and arraycells (Conventional Technique)ARRtAVV~ tELLWORD ----r-1ll'mLINEr---11 I REFERENCEG 6319Vcc5- 9787If the addressed cell is erased its current is the sameas the reference cell's current and the imbalanceat the inputs of the comparator (highervoltage on right side = 1) is obtained by connectinglower impedence load on the right side than on theleft.If the addressed cell is written (no current) the leftinput to the comparator will have a higher voltagethan the right side (0 state).The above approach has proven to be efficient andreliable but still shows a drawback that is the dependanceof the Vee operating range (at highVecl on the threshold shift of the written cell. Thiscan be easily understood by looking at the cell transcharacteristicsdiagram: together with the charac-Figure 3 - Dependance of Vee max on threshold shift(R = Loads impedance ratios) (conventional techniques)Vee maxR=3R=4Vth shift12/1584

M27512M27512 DESIGN INNOVATIONS FOR AN EFFI­CIENT PROGRAMMING PRESTO (Continued)As a conclusion at least a minimum threshold shiftof 2V to 3V must be required to the programmedcell to guarantee a wide Vee operation range andreliability.An innovative approach for the sensing was implementedinto the M27512 to remove the above describeddrawback. The sensing scheme isillustrated in figure 4: the impedance of the loadsis the same on both sides; on the left side an offsetcurrent is added to the addressed cell's current- (patent pending).Figure 4 - M27512 sensing schematicThe final result is that a threshold shift of about 1 Vfor a written cell is enough to allow a proper sensingin a very wide Vee operating range (figure 6).Figure 6 - Dependance of Vcc max on threshold Shift(M27512)VCCmaxG-6322VthshiftiOFFSETL5- 9188/1WORDLINE ---r1 1 ~.~ A~ReRtAYYr--4 I~ASREFERENCECELLThe improvement is easily pointed out in the diagramof the cell transcharacteristics (figure 5) thedifference in slope between the written cell and thereference cell are drastically reduced.Figure 5 - Current relemention ship of reference andarray cells (New Technique)IoFFSETG-6321For better process margin and producibility the offsetcurrent is not fixed but tracks the matrix cellcurrent. The improvement of both the programmingspeed and the sensing efficiency will reduce thetypical programming time per byte to below 200p.sec.In order to take full advantage ofthis the originalPRESTO programming algorithm was developpedas illustrated in previous paragraph.The Similarity with the Fast Programming Algorithmis evident but several main differences exist:- 500 p'sec elementary pulses- no overprogram pulses are applied after correctverification of a byte- the existence of a sufficient margin for thewritten cells is guaranteed by making the programverify in a special test mode calledMARGIN MODE' ...Reading a cell in MARGIN MODE requires to thewritten cell a threshold shift of about 2V: 1 V marginabove the threshold shift required for a correctoperation with wide Vee range in normal operatingmodes. The circuit arrangement that allows to guaranteethe margin is illustrated in figure 7.The result in the transcharacteristic plane helps tounderstand the MARGIN MODE feature (figure 8).The threshold shift margin has been carefully tunedin order to guarantee that the Vee operatingrange and the access time performance would notbe reduced by a cell marginally written; taking intoaccount the temperature range, noise conditions,and data retention (intrinsic charge loss).The MARGIN MODE is set before starting the programmingalgorithm and reset after the completion.13/1585

M27512Figure 7 - M27512 Sensing schematic with activatedmargin modeFigure 8 - Current relationship of reference and arraycells with margin mode activatedVBI~~AS.. I OFFSETIOFFSETG-6323 VCCWORD--crT1LINECELLS-9790CONCLUSIONM~7512 has ~uccesfully achieved the goal of drastlc~lIyre~uclng the programming time by:- Improving the programming efficiency- implementing an improved sensing schemeguaranteing by an innovative hardware approachan adequate margin for reliabilityThe goal has been achieved without requiring anyadditional scaling to the well proven NMOS-E3technology: further improvements can be foreseenwhen combining the new scaled down technologies(C~OS-E4) with the above circuit techniques ..ExtenSive characterization and life tests have demonstratedthe efficiency and the reliability of thesolutions adopted.14/1586

~ ________ ~3 ________ ~ ~ __ ~ ____ ~M27512ORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageM27512-2F1M27512F1M27512-3F1M27512-25F1M27512-30F1M27512F6200 ns250 ns300 ns250 ns300 ns250 ns5V± 5%5V± 5%5V± 5%5V±10%5V±10%5V± 5%o to + 70·eo to + 70·eo to + 70·eo to + 70·eo to +70·e-40 to +85·eDIP-28DIP-28DIP-28DIP-28DIP-28DIP-28PACKAGE MECHANICAL DATA28-PIN CERAMIC DIP BULL'S EYE~ n :-3"1:MIG FI' ~ 'I[]&12:::]JIP05S.1/2Dim.AMinB 14.50C 3.900 3.00E 0.50.3 33.02F 2.29G 0.40I 1.17L 0.22M 1.52N 16.51P 15.40Q0 8.64mminchesTyp Ms, Min Typ Max38.10 1.50014.90 0.571 0.5875.08 0.154 0.2000.1181.78 0.020 0.0701.3002.79 0.090 0.1100.55 0.016 0.0221.42 0.046 0.0560.31 0.009 0.0122.49 0.060 0.09818.00 0.650 0.70915.80 0.806 0.6225.71 0.2259.14 0.340 0.38015/1587

EPROM DEVICESCMOS UV EPROM89

ETC271616K BIT (2K x 8) CMOS UV ERASABLE PROM• CMOS POWER CONSUMPTION• PERFORMANCE.COMPATIBLE TO MARKETSTANDARD 8-BIT CMOS MICROP.• 2048 x 80RGANIZZATION• PIN COMPATIBLE TO 2716• ACCESS TIME DOWN TO 350 ns• SINGLE 5V POWER SUPPLY• STATIC - NO CLOCKS REQUIRED• TIL COMPATIBLE II0s DURING BOTH READAND PROGRAM MODES• THREE-STATE OUTPUT WITH OR-TIECAPABILITY• OPER. TEMP.: Oto + 70°C; -40to + 85°C(V suffix).QDIP-24(Ceramic Bull's Eye)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe ETC ~716 is a high speed 16K UV erasableand electrically reprogram mabie CMOS EPROM,ideally suited for applications where fast turnaround,pattern experimentation and low powerconsumption are important requirements.The ETC 2716 is packaged in a 24-pin dual-in-linepackage with transparent lid. The transparent lidallows the user to expose the chip to ultraviolet lightto erase the bit pattern. A new pattern can then bewritten into the device by following the programmingprocedure. This EPROM is fabricated with thereliable, high volume, time proven, p2 CMOS silicongate technology.PIN NAMESAO-Al0ADDRESS INPUTS00-0 7 DATA OUTPUTSCEIPGMOEVppVeeVssCHIP ENABLEIPROGRAMOUTPUT ENABLEREAD 5V, PROGRAM 25V5V'GROUND..A7A6A5A4A3A2A1AO000102vssvceA8.A9vppDEA10CE/PGM0706050403June 19881/991

ETC2716BLOCK DIAG~AM+-- vpp+-- vcc+-- VSSDATA OUTPUTS (PROGRAM INPUTS)Ob-07YGATING16,384BIT MATRIXPIN CONNECTION DURING READ OR PROGRAMMODEPIN NAME/NUMBERCElPGM OE Vpp18 20 21Read VIL VIL 5Program Pulsed VIL to VIH VIH 25Vee2455OUTPUTS9-1l. 13-17DOUTDIN'ABSOLUTE MAXIMUM RATINGS(l)SymbolTambTstgVppVinPoTemperature Under Bias"V" rangeStorage TemperatureParameterVpp Supply Voltage with Respect to VSSInput Voltages with Respect to Vss except VPPOutput Voltages with Respects to Vss.Power DissipationLead Temperature (Soldering 10 seconds)Value-10to +80-50 to +95-65 to +12526,5V to -0,36V to -0.3Vcc+0.3V toVss-0,3V1,0+300Note 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Opera,ting Temperature Range" they are, not meant to imply that the devices should be operated at these limits. The table of "ElectricalCharacteristics" provides conditions for actual. device operation.21992Unit·C·C·CVVW·C

ETC2716READ OPERATIONDC CHARACTERISTICS TA=O°C to + 70°C, VCC=5V±5%, Vpp=VCC (2), VSS=OV, (Unless otherwisespecilied)(6)Symbol Parameter Test Conditions Min. Typ. Max. UnitsIII Input Current VIN = VCC or GND - - 10 p,AILO Output Leakage Current VOUT=5.25V, CE/PGM=VIH - - 10 p,AVIL Input Low Voltage -0.1 - 0.8 VVIH(4) Input High Voltage 2.0 - VCC+1 VVOU Output Low Voltage IOL=2.1 mA - - 0.45 VVOHI Output High Voltage IOH= -400 p,A 2.4 - - VVOL2 Output Low Voltage IOL=O p,A - - 0.1 VVOH2 Output High Voltage IOH=O p,A Vcc-0.1 - - VIppi Vpp Supply Current Vpp=5.25V - - 10 p,AICCI VCC Supply Current Active CE/PGM, OE = VIL(TTL Levels) Address = VIH or VIL - 2 10 mAFrequency 1 MHz, I/O = OmAICC2 V CC Supply Current Active CE/PGM = OE = VIL (Note 5)(CMOS Levels) Addresses=GND or VCC - 1 5 mAFrequency 1MHz, 1/0=OmAIccssl V CC Supply Current Standby CE/PGM=VIH - 0,1 1 mAICCSS2 V CC Supply Current Standby CE/PGM=Vcc - 0,01 0,1 mAAC CHARACTERISTICS (TA = O°C to + 70°C, VCC = 5V ±5%, VPP = VCC, VSS = OV; Unless otherwisespecilied)(6).Symbol ETC2716-1 ETC2716 (-V)ParameterTest ConditionsAlternate StandardMin. Max. Min. Max.tACC TAVOV Address to Output Delay CE/PGM=OE=VIL - 350 - 450 nstCE TELOV CE to Output Delay OE=VIL - 350 - 450 nstOE TGLOV Output Enable to CE/PGM=VIL - 120 - 120 nsOutput DelaytOF(5) TGHOZ OE or CE High to CE/PGM=VIL 0 100 0 100 nsOutput Hi-ZtOH TAXOX Address to Output Hold CE/PGM = OE = VIL 0 - 0 - nstoo TEHOZ CE to Output Hi-Z OE=VIL 0 100 0 100 nsUnitCAPACITANCE(3) TA=25°C, 1=1 MHzSymbol Parameter Test Conditions Min. Typ. Max. UnitCI Input Capacitance VIN=OV 4 6 pFCo Output Capacitance VOUT=OV 8 12 pFNotes I. Typical conditions are for operation at: TA=25°C. VCC=5V, Vpp=VCC, and VSS=OV.2. Vpp may be connected to VCC except during program.3. Capacitance is guarallllllld..lly periodic testing. T A = 25°C, f = I MHz ..4. The inputs (Address, OE, CE) may go above VCC by one volt with no latch up danger. Only the output (data inputs duringprogramming) need be..restrk:Jed to VCC + 0.3V.5. T OF is specified for OE or CE which ever occurs first. This parameter is only sampled and not 100% tested.6. TA = - 40·C to + 85·C for "V" range3/993

ETC2716AC TEST CONDITIONSOutput Load: 1 TTL gate and CL = 100 pFInput Rise and Fall Times::; 20 nsInput pulse levels: O,4SV to 2,4VTiming Measurement Reference LevelInputs, OutputsO.BV and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT2.4=>

ETC2716DEVICE OPERATIONThe ETC2716 has 3 modes of operation in the normalsystem environment. These are shown in Table1.READ MODEThe ETC2716 read operation requires that OE =VIL, CE/PGM = VIL and that addresses Ao-A1O havebeen stabilized. Valid data will appear on theoutput pins after tACC tOE or tCE times (see SwitchingTime Wafeforms) depending on which is limiting.DESELECT MODEThe ETC2716 is deselected ~making OE = VIH.This mode is independent of CE/PGM and the conditionof the addresses. The outputs are Hi-Z whenOE = VIH. This allows OR-tying 2 or more ETC2716for memory expansion.STANDBY MODE (POWER DOWN)The ETC2716 may bllowered down to the standbymode by making CE/PGM = VIH. This is independentof OE and automatically puts the outputsin their Hi-Z state. The power is reduced to 0.4%of the normal operating power. VCC must be maintainedat 5V. Access time at power up remains eithertACC or tCE (see Switching Time Waveforms).PROGRAMMINGThe ETC2716 is shipped from SGS-THOMSONcompletely erased. All bits will be at a "1" level(output high) in this initial state and Cifter any fullerasure. Table II shows the 3 programming modes.PROGRAM MODEThe ETC2716 is programmed by introducing "O"sinto the desired locations. This is done 8 bits (a byte)at a time. Any individual address, a sequenceof addresses, or addresses chosen at random maybe programmed. Any or all of the 8 bits associatedwith an address location may be programmedwith a single program pulse applied to the chip ena-TABLE I. OPERATING MODES (VCC=5V)PIN NAMEINUMBERMODE CE/PGM OE Outputs18 20 9-11,13·17Read VIL VIL DourDeselect Don't Care VIH Hi·ZStandby VIH Don't Care Hi·Zble pin. All input voltage levels, including the programpulse on chip enable are TTL compatible. Theprogramming sequence is: _With Vpp = 25V, VCC = 5V, OE = VIH andCE/PGM = VIL, an address is selected and thedesired data word is applied to the output pins.(VIL = "0" and VIH = "1" for both address anddata). After the address and data signals are stablethe program pin is pulsed from VIL to VIHwith a pulse width between 45 ms and 55 ms.Multiple pulses are not needed but will not causedevice damage. No pins should be left open. A highlevel (VIH or higher) must not be maintained longerthan tpW(MAX) on the program pin during programming.ETC2716 may be programmed inparallel with the same data in this mode.PROGRAM VERIFY MODEThe programming of the ETC2716 is verified in theprogram verify mode which has Vpp at VCC (seeTable II). After programming an address, that sameaddress cannot be immediately verified withoutan address change (dummy read).PROGRAM INHIBIT MODEThe program inhibit mode allows programming severalETC2716 simultaneously with different datafor each one by controlling which ones receive theprogram pulse. All similar inputs of the ETC2716may be paralleled. PulSing the program pin (fromVIL to VIH) will program a unit while inhibiting theprogram pulse to a unit will keep it from being programmedand keeping OE = VIH will put its outputsin the HI-Z state.TABLE II. PROGRAMMING MODES (Vcc=5V)MODEPROGRAMPROGRAM VERIFYPROGRAM INHIBITCE/PGM18Pulsed VIL to VIHVILVILPIN NAME/NUMBEROE Vpp OUTPUTS20 21 9-11,13-17VIH 25 DINVIL 25(5) DourVIH 25 Hi-Z5/995

ETC2716ERASING~he ETC?716 !s erased by exposure to high inten­Slt~ ultraviolet hght through the transparent window.:r~I~ exposure discharges the floating gate to itsmilial state through induced photo current. It is recomme~dedthat the ETC2716 be kept out of directs~nhght. The UV content of sunlight may causea p~rllal e.rasure. of some bits in a relatively shortpenod of time. Direct sunlight can also cause temporaryfunctional failure. Extended exposure toroom level fluorescent lighting will also cause erasure.An opaque coating (paint, tape, label,etc.)should ~e placed over the package window if thisp~?duct IS to ~e operated under these lighting condilions.Covenng the window also reduces ICC dueto photodiode currents.An ultraviolet source of 2537A yielding a total integrateddosage of 15 watt-seconds/cm 2 is requi-red. This will erase the partin approximately 15 to20 min~tes!f a UV lamp with a 12,000 /l-W/cm 2 powerratmg IS used. The ETC2716 to be erasedshould be place 1 inch away from the lamp and nofilters should be used.An erasu.re system should be calibrated periodically.The distance from lamp to unit should be maintainedat 1 inch. The erasure time is increased bythe square of the distance (if the distance is doubledthe erasure time goes up by a factor of 4).Lamps lose intensity as they age. When a lamp ischanged, the distance is changed, or the lamp isaged, the system should be checked to make certa.infull erasure is occurring. Incomplete erasurewill cause symptoms that can be misleading. Programmers,components, and system designs havebeen erroneously suspected when incompleteerasure was the basic problem.TIMING DIAGRAMPROGRAM MODEPROGRAM__ PROGRAM VERIFY(DE VIH) (DE VIL) .VIH~~~~------------~~------------~ADDRESSESVIL~~~~~~ __ ~~~~~~::~ ______ J ~~A_DD_R_E_S_S_X_+_1DATAVIL===~DATA IN STABLEADDRESS X + 1_GVIH------~--_1--tl--,t~D~H--t--r--~VIL tDS (TPLDX) -(TDVPH) -- -1(TGHPH)VIH ------------:.....j....jtE/P'VIL ~=====;;tjtpw_ tos ~ ~--- - (TPHPL)tPF(TPL 1 PL1)Note: Symbols in parentheses are proposed JEDEC standard6/996

ETC2716PROGRAM OPERATIONS(1,2)DC AND OPERATIVE CHARACTERISTICS (TA=25°C±5°C) (VCC=5V±5%, Vpp=25V±1V)ValuesSymbol Parameter UnitMin. Typ. Max.III Input Leakage Current (Note 3) - - 10 ,"AVIL Input Low Level -0.1 - 0.8 VVIH Input High Level (Note 7) 2.2 - Vcc+ 1 VIcc VCC Power Supply Current - - 10 mAIpP1 Vpp Supply Current (Note 4) - - 10 ,"AIpP2 Vpp Supply Current During - - 30 mAProgramming Pulse (Note 5)AC CHARACTERISTICS (TA=25°C±5°C) (VCC=5V±5%, Vpp=5V±1V) (Note 6)Symbol Parameter Min. Typ. Max. UnitstAS Address Setup Time 2 - - ,"Stos OE Setup Time 2 - - ,"Stos Data Setup Time 2 - - ,"StAH Address Hold Time 2 - - ,"StoH OE Hold Time 2 - - ,"StOH Data Hold Time 2 - - ,"StOF Output Disable to Output Three 0 - 100 ,"sstate DelaytOE Output Enable to Output Delay - - 120 nstpw Program Pulse Width 45 50 55 mstpR Program Pulse Rise Time 5 - - nstpF Program Pulse Fall Time 5 - - nsNotes 1. VCC must be applied at the same time or before Vpp and removed after or at the same time as Vpp. To prevent damage tothe device it must not be inserted into a board with power applied.2. Care must be taken to prevent overshoot of the Vpp supply when switching to + 26V max.3. Qj/

ETC2716SWITCHING TIME WAVEFORMSR.ed Cycl. (CElPGM = VIL)ADDRESSESOUTPUT ENABLEOUTPUTVIHVILVIHVILVOHVOLVALIDtoH_-(TAXQX)IDFIACC-ttoE(TGLQV) (TGHQZ)--(TAVQV)-Hi ZVALIDVALIDHiZReed Cycl. (6E = VIL)ADDRESSESCHIP ENABLEOUTPUTVIHVIL ~~VALID VALIDVIHVILVOHVOL~ tOH ~(TAXQXI\ ;1II-i- teE 100(TELQV) (TEHQZ)--(TA.:g~-Hi ZVALID-I\.HiZADDRESSESCHIP ENABLEOUTPUTVIHVILVIHVILStandby Pow.r·Down Mod. (OE = VIL)VALID~ICE-ITELQV)/~N-STANDBY -ACTIVE'__ 100 _ IACCi' (TEHQZ) (TAVQV)VALIDVOHVALID FOR 1\ HI ZVALID FORVOL CURRENT ADDRESS LCURRENT ADDRESSSTANDBY\. HI ZfSymbols in parentheses are proposed JEDEC standard8/998

ETC2716ORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageETC2716QETC2716Q·1ETC2716Q·V450 ns350 ns450 ns5V± 5%5V± 5%5V± 5%o to + 70°C Dlp·24o to + 70°C Dlp·24-40 to +85°C DIP-24PACKAGE MECHANICAL DATA24-PIN CERAMIC DIP BULL'S EYEP05S·B/SOPTIONALDim.mminchesMin Typ Max Min Typ MaxA 32.3Q 1.272B 13.05 13.36 0.514 0.526C 3.90 5.08 0.154 0.2000 3.00 0.11801 (1 ) 3.40 0.134E 0.50 1.78 0.020 0.070.3 27.94 1.100F 2.29 2.79 0.090 0.110G 0.40 0.55 0.016 0.022I 1.17 1.42 0.048 0.056111') 1.27 1.52 0.050 0.060l 0.22 0.31 0.009 0.012M 1.52 2.49 0.060 0.098N 16.51 18.00 0.650 0.709P 15.40 15.60 0.606 0.622Q 5.71 0.22.10 6.86 7.36 0.270 0.290Note: 1. Optional see drawing9/999-------~~-- .. ---------- '--.- --'-'-

ETC273232K BIT (4K x 8) CMOS UV ERASABLE PROM• CMOS POWER CONSUMPTION: 26.25 mWMAX ACTIVE POWER, 0.53 mW MAXSTANDBY POWER• 4096 x 80RGANIZZATION• PIN COMPATIBLE TO M/ET2716, ETC2716,M2732A,• ACCESS TIME DOWN TO 350 ns• SINGLE 5V POWER SUPPLY• STATIC - NO CLOCKS REQUIRED• TTL COMPATIBLE II0s DURING BOTH READAND PROGRAM MODES• THREE-STATE OUTPUT WITH OR-TIECAPABILITY• OPER. TEMP. : 0 to + 70°C; - 40 to + 85°C(V suffix).QDIP-24(Ceramic Bull's Eye)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe ETC2732 is a high speed 32K UV erasable andelectrically reprogrammable CMOS EPROM, ideallysuited for applications where fast turn-around,pattern experimentation and low power consumptionare important requirements.The ETC2732 is packaged in a 24-pin dual-in-linepackage with transparent lid. The transparent lidallows the user to expose the chip to ultraviolet lightto erase the bit pattern. A new pattern can then bewritten into the device by following the programmingprocedure.This EPROM is fabricated with thereliable, high volume, time proven, p2 CMOS silicongate technology.PIN NAMESAO-A11ADDRESS INPUTS0 0-0 7 DATA OUTPUTSCEOEVppVeeVssCHIP ENABLEOUTPUT ENABLEREAD RV, PROGRAM 25V5VGROUNDA7A6ASA4A3A2A1AO000102vssveeASA9A11OEIVPPJune 19881/10101

ETC2732BLOCK DIAGRAMVCC~5VGNDl\ISS)~GNDOE/C~EPP -tl_......:CO---.NT_R_O_L_j___:·11--l LOGICiYDECODERDATA OUTPUTS00-0 7OUTPUT BUFFERSY. GATINGAD-All~DDRESSINPUTSXDECODER32,768-BITCELL MATRIX---+L-________ r---~ ________ ~PIN CONNECTION DURING READ OR PROGRAMMODEPIN NAME/NUMBERCE OE/Vpp Vee18 20 24READ VIL VIL 5VSTANDBY VIH Don't Care 5VPROGRAM VIL 25V 5VPROGRAM VERIFY VIL VIL 5VPROGRAM INHIBIT VIH 25V 5V• Symbol in parentheses are proposed JEDEC standard.OUTPUTS9-11,13-17DOUTHi-ZDINDOUTHi-ZABSOLUTE MAXIMUM RATINGSSymbol Parameter ValueTamb Temperature Under Bias -10to +80I'V" range -50 to +95Tstg Storage Temperature -65 to +125Vpp Vpp Supply Voltage with Respect to VSS 26.5V to - 0.3Yin Input Voltages with Respect to VSS except VPP 6V to -0.3Output Voltages with Respects to VSSVCC+0.3V toVSS~0:3VPo Power Dissipation 1.0WLead Temperature (Soldering 10 seconds)300 ......°CNote 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "OperatingTemperature Range" they are, not meant to imply that the devices should be operated at the~e limijs. The table of "Electric.alCharacteristics" provides conditions for actual device operation. . -Unit°C°C°CVV2/10102

ETC2732READ OPERATIONDC CHARACTERISTICS TA=OoC to + 70°C, VCC =SV ±S%, VSs=OV, (Unless otherwise specilied)(6)Symbol Parameter Test Conditions Min. TypJl) Max. UnitsIII Input Current VIN=VCC or GND - - 10 ",AILO Output Leakage Current VOUT=VCC or Vss, CE=VIH - - 10 ",AVIL Input Low Voltage -0.1 - 0.8 VVIH(3) Input High Voltage 2.0 - VCC+1 VVOLl Output Low Voltage IOL=2.1 mA - - 0.45 VVOHI Output High Voltage IOH= -400 ",A 2.4 - - VVOL2 Output Low Voltage IOL=O",A - - 0.1 VVOH2 Output High Voltage IOH=O",A Vcc-O.l - - VICCI VCC Supply Current Active CE=OE=VIL(TTL Levels) Input = VIH or VIL - 2 10 mAFrequency 1 MHz, 1/0 = OmAICC2 VCC Supply Current Active CE=OE=VIL (Note 4)(CMOS Levels) Inputs=GND or VCC - 1 5 mAFrequency 1 MHz, 1/0 = OmAICCSBI VCC Supply Current Standby CE=VIH - 0.1 1 mAICCSB2 VCC Supply Current Standby CE=Vcc - 0.01 0.1 rnAAC CHARACTERISTICS TA = OOC to C, VCC = SV ±S% VSS = OV; Unless otherwise specilied)(6).Symbol Parameter Test ConditionsETC2732-3ETC2732 (-V)Min. Max. Min. Max.tACC Address to Output Delay CE/PGM = OE = VIL - 350 - 450 nstCE CE to Output Delay OE=VIL - 350 - 450 nstOE Output Enable to CE/PGM=VIL - 150 - 150 nsOutput DelaytDF(4,5) OE or CE High to CE/PGM=VIL 0 130 0 130 nsOutput Hi-ZtOH Address to Output Hold CE/PGM = OE = VIL 0 - 0 - nsUnitCAPACITANCE (TA= +2SoC, 1=1 MHz) (Note 2)Symbol Parameter Test Conditions Min. Typ. Max. UnitCINI Input Capacitance Except OENpp VIN=OV 4 6 pFCIN2 OENpp Input Capacitance VIN=OV - 20 pFCOUT Output Capacitance VOUT=OV 8 12 pFNotes 1. Typical conditions are lor operation at: TA = 25°C, VCC = VPP = VCC, and VSS = OV.2. Capacitance is guaranteedJly periodic testing. TA = 25°C, I = 1 MHz.3. The inputs (Address, OE, CE) may go above VCC by one volt with no latch up danger. Only the output (data inputs duringprogramming) need be restricted to VCC + 0.3 V.4. The tDF compare level is determined as lollows:High to Hi-Z, the measured VOHI (DC) - 0.10VLow to HI-Z, the measured VOHtJQC) + 0.10V5. TDF is specified from OE or CE which ever occurs first. This parameter is only sampled, not 100% tested.6. TA= -40°C to +85°C for "V" range3/10103

ETC2732AC TEST CONDITIONSOutput Load: 1 TTL gate and CL= 100 pFInput Rise and Fall Timess 20 nsInput pulse levels: 0.45V to 2.4VTiming Measurement Reference· LevelInputs, Outputs0.8V and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT2.4=>TEST POINTS< •0.45 0.8 0.8I ~~~~ TEST1N914[ 3.3Kn'11-----.---0 OUT=I~ CL='OOpF..... ,CL INCLUDES JIG CAPACITANCEAC WAVEFORMSV,HADDRESS ES ADDRESS VALID)V,LCEV,HV ilI'CEiii'V,HV,LI 'OE(3)'ACC(3)V,HOUTPUTV,LHIGH ZIIIIII\.\\\\vHIGHZS~6809Notes:1. Typical values are for T amb = 25°C and nominal supply voltage2. This parameter is only sampled and not 100% tested. _3. (5l;' may be delayed !!Q.. to tACe • tOE after the falling edge CE wnhout impact on tACC4. tOFis specified form OE or Ce-whlchever occurs first.4/10104

ETC2732DEVICE OPERATIONThe five modes of operation of the ETC 2732 arelisted in the Operating Modes table. A single 5 Vpower supply is required in the read mode. All inputsare TTL levels except for OENpp during programming.In the program mode the OENpp inputis pulsed from a TTL level to 25V.READ MODEThe ETC2732 has two control functions, both ofwich must be logically active in order to obtain dataat the ouputs. Chip Enable (CE) is the power controland should be used for device selection. OutputEnable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, address access time (tACC) is equal tothe delay from CE to output (tCE). Data is availableat the ou.!mJts after the falling edge of OE,assuming that CE has been low and addresses havebeen stable for at least tACC-tOE.STANDBY MODEThe ETC2732 has a standby mode which reducesthe active power dissipation by 98%, from 26.25mW to 0.53mW. The ETC 2732 is placed in thestandby mode, by applying a TTL high signal to theCE input when in standby mode the outputsare in a high impedance state, independant of theOE input.OUTPUT OR-TYINGBecause EPROMS are usually used in larger memoryarrays, we have provided a 2-line control functionthat accomodates this use of multiple memoryconnection. The 2-line control function allows for.a) the lowest possible memory power dissipation,andb) complete assurance that output bus contentionwill not occur.To most efficiently us~hese two control lines, itis recommended that CE (pin 18) be decoded andused as the primary device selecting function, whileOE (pin 20) be made a common connection to alldevices in the array and connected to the READline from the system control bus. This assures thatall deselected memory devices are in their low powerstandby modes and that the output pins areactive only when data is desired from a particularmemory device.PROGRAMMINGCAUTION: Exceeding 26.5V on pin 20 (Vpp) willdamage the ETC2732.Initially, and after each erasure, all bits of the ETC2732 are in the" 1" state. Data is introduced byselectively programming "Os" into the desired bitlocations. Although only "Os" will be programmed,both "1s" and "Os" can be presented in the dataword. The only way to change a "0" to a "1" isby ultraviolet light erasure.The~C2732 is in the programming mode whenthe OENpp input is at 25V. It is reqUired that a 0.1ftF capacitor be placed across OENpp, and groundto suppress spurious voltage transients which maydamage the device. The data to be programmedis applied 8 bits in parallel to the data output pins.The levels required for the address and data inputsare TTL.When the address and data are stable, a 50 msactive low TTL program pulse is applied to the CEinput. A program pulse must be applied at eachaddress location to be programmed. You can programany location at any time-either individually,sequentially, or at random. The program pulse hasa maximum width of 55 ms. The ETC 2732 mustnot be programmed with a DC signal applied to theCE input.Programming of multiple ETC 2732s in parallel withthe same data can be easily accomplished due tothe simplicity of the programming requirements. likeinputs of the paralleled ETC 2732s may be connectedtogether when they are programmed withthe same data. A low level TTL pulse applied tothe CE input programs the paralleled.OPERATING MODES~ CEMODE (18)READVILOElVpp vee OUTPUTS(20) (24) (9-11,13-17)VIL 5 DourSTANDBY VIH Don't Care 5 Hi-ZPROGRAMVILVpp5 DINPROGRAM VERIFYVILVIL5 DourPROGRAM INHIBITVIHVpp5 Hi-Z~ SIiS-1HOMSON.., I. Ul1JO(i:;OO©~~~(i:;VOO©fiIIlO(i:;i\l5/10105

ETC2732PROGRAM INHIBITProgramming multiple ETC2732s in parallel withdifferent data is also easily accQIDPlished. Exceptfor CE, all like inputs (including OE) of the parallelETC2732s may be common. A TIL level programI2Y!se applied to an ETC2732s CE input withOENl2I2...at 25 V will program that ETC2732. A highlevel CE input inhibits the other ETC2732s frombeing programmed.PROGRAM VERIFYA verify should be performed on the programmedbits to determine whether they were corre~ pro-9.@mmed. The verify is accomplished with OENppCE at VIL. Data should be verified tov after the faIlingedge of CEoERASURE CHARACTERISTICSThe erasure characteristics of the ETC2732 aresuch that erasure begins to oCCl:.lr when exposedto light with wavelenghts shorter than approximately4000 Angstroms (A). It should be noted thatsunlight and certain types of fluorescent lamps havewavelenghts in the 3000 A - 4000 A range. Datashows that constant exposure to room-levelfluorescent lighting could erase the typical ETC2732 in approximately 3 years, while it would takeapproximately 1 week to cause erasure when exposedto direct sunlight. If the ETC2732 is to beexposed to these types of lighting conditions forextended periods of time, opaque labels should beplaced over the ETC2732 window to prevent unin~tentional erasure. Covering the window will alsoprevent temporary functional failure due to the generationof photo currents.The recommended erasure procedure for the ETC2732 is exposure to shortwave ultraviolet lightwhich has a wavelength of 2537 Angstroms (A). Theintegrated dose (i.e., UV intensity x exposure time)for erasure should be a minimum of 15W-sec/cm2.The erasure time with this dosage is approximately21 minutes using an ultraviolet lamp with a 12,000p.W/cm2 power rating. The ETC2732 should be placewithin 1 inc/1 of the lamp tubes during erasure,Some lamps have a filter on their tubes whichshould be removed before erasure.An erasure system should be calibrated periodically.The distance from lamp to unit should be maintainedat one inch. The erasure time increases asthe square of the distance. (If distance is doubledthe erasure time increases by a factor of 4). Lampslose intensity as they age. When a lamp is changed,the distance has changed or the lamp hasaged, the system should be checked to make certainfull erasure is occurring. Incomplete erasurewill cause symptoms that can be misleading. Pr~grammers, components, and even system designshave been erroneously suspected when incompleteerasure was the problem.SYSTEM CONSIDERATIONThe power swhitching characiterics of EPROMs requirecareful decoupling of the devices. The supplycurrent, ICC, has three segments that are ofinterest to the system designer - the standby cUrrentlevel, the active current level, and the transientcurrent peaks that are produced on the falling andrising edges of chip enable. The magnitude of thesetransient current peaks is dependent on the outputcapacitance loading of the device. The associatedtransient voltgage peaks can be suppressedby properly selected decoupling capacitors. It is recommendedthat a 0.1p.F Ceramic capaCitor beused an every device between Vee and GND. Thisshould be a high frequency capacitor of low inherentinductance. In addition, a 4.7p.F.bulk electoly,tic capacitor should be used between Vee andGND. for each eight devices. The bulk capacitorshould be located near where the power supply isconnected to the array. The purpose of the bulkcapaCitor is to overcome the voltage drop causedby the inductive effects of the PC board traces.6110106

ETC2732PROGRAMMING WAVEFOR'''SNote: All times shown in parentheses are minimumand in p,s unless otherwise specified.The input timing reference is 0.8V for a VIL and 2Vfor a VIH.TIMING DIAGRAMVIH::::::~~----------------------~~ __ ---r----------·~----~VIL::::::-:f~ ___________---i____....._~ ''____ADDRESSES ADDRESS X ADD X + I'AS12)VIH ====

ETC2732PROGRAMMING OPERATION (1,2)DC OPERATING CHARACTERISTICS T A = + 25°C ± 5°C, Vee = 5V :1:5%, Vpp = 25V:I: 1V; Unless otherwisespecified)Symbol Parameter Test ConditionsValuesMin. Typ. Max.III Input Current (All inputs) VIN = Vee or GND - - 10 p.AVOL Output Low Voltage During IOL=2.1 mA - - 0.45 VVerifyVOH Output High Voltage During IOH = - 400 p.A 2.4 - - VVerifylee Vec Supply Current - 2 10 mAVIL Input Low Level (All Inputs) -0.1 - 0.8 VVIHInput High Level (All InputsExcept OENpp) 2.0 - Vee+ 1 VIpp Vpp Supply Current CE = VIL, OE = Vpp - - 30 mAUnitAC CHARACTERISTICS (TA= +25°C±5°C, Vee = 5V:l:5%, Vpp 25V:l:1V).Symbol Parameter Test Conditions Min. Typ. Max. UnittAS Address Set·Up Time 2 - - I'lltOES OE Set·Up Time 2 - - I'lltos Data Set·Up Time 2 - - I'lltAH Address Hold Time 0 - - I'lltOEH OE Hold Time 2 - '- I'lltOH Data Hold Time 2 - - p'stOF Chip Enable to Output 0 - 130 nsFloat Delaytov Data Valid from CE CE = VIL; OE = VIL - - 1 I'lltpw CE Pulse Width During 45 50 55 msProgrammingtpRTOE Pulse Rise TimeDuring Programming 50 - - nstVR Vpp Recovery Time 2 - - I'llNotes 1. VeG must be applied simultaneously or ~fore Vpp and removed simultaneously.or after Vpp. The ETC 2732 must not be inser·ted Into or removed from a board with Vpp at 25 ± 1 V to prevent damage to. the device.2. The maximum allowable voltage which may be applied to the Vpp pin during programming is 26V. Care must be taken whenswitching the Vpp supply to prevent overshoot exceeding this 26V maximum specification. A 0.1. ~F capac"or is required acrossVpp, Vee to GND to suppress spurious voltage transients which may damage the device.8/10.108

ETC2732SWITCHING TIME WAVEFORMSRead Cyele,~ = VILIADDRESSESVIHVILOUTPUT ENABLEVlHVILtoEOUTPUTVOHVOLVAUDRead Cyele ,erE = VILIADDRESSESVIHVILCHIP ENABLEVIHVILteEOUTPUTVOLVAUDHI Z9/10109

ETC2732ORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageETC2732Q·3ETC2732QETC2732Q·45·V350 ns450 ns450 ns5V±50Al5V±50Al5V±50Alo to + 70·C Dlp·24o to + 70·C Dlp·24-40 to +85·C Dlp·24PACKAGE MECHANICAL DATA24-PIN CERAMIC DIP BULL'S EYEf=lrr;:;:;;:;;, ~~-i,:;to ni:iPi :1M ,------~ IL'POSS·BIBe3NOPTIONALmmInchesDim.Min Typ Max Min Typ MaxA 32.30 1.272B 13.05 13.36 0.514 0.526C 3.90 5.08 0.154 0.2000 3.00 0.11801 11) 3.40 0.134E O.SO 1.78 0.020 0.070,3 27.94 1.100F 2.29 2.79 0.090 0.110G 0.40 0.55 0.D16 0.022I 1.17 1.42 0.046 0.05611 11 ) 1.27 1.52 O.OSO 0.060l 0.22 0.31 0.009 0.012M 1.52 2.49 0.060 0.098N 16.51 18.00 0.650 0.709P 15.40 15.60 0.606 0.622Q 5.71 0.2250 6.86 7.36 0.270 0.290Note: ,. Optional see drawing10/10110

TS27C64AQ64K (8K x 8) CMOS UV ERASABLE PROM• FAST ACCESS TIME - 150ns, 200ns, 250ns,300ns• COMPATIBLE TO HIGH SPEED MICROPRO­CESSORS ZERO WAIT STATE• 28-PIN JEDEC APPROVED PIN-OUT• LOW POWER CONSUMPTION:ACTIVE 30mA MAX.STANDBY 1MA MAX.• PROGRAMMING VOLTAGE: 12.5 V• HIGH SPEED PROGRAMMING « 1 minute)• ELECTRONIC SIGNATURE• ALSO PROPOSED IN PLASTIC PACKAGES(OTP)~N~~~U'1QDIP-28(Ceramic Buli's Eye)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe TS27C64A is a high speed 65,536 bit UV erasableand electrically reprogrammable EPROMideally suited for applications where fast turnaroundand pattern experimentation are importantrequirements.The TS27C64A is packaged in a 28 pin dual-in-Iinepackage with transparent lid. The transparent lidallows the user to expose the chip to ultraviolet lightto erase the bit pattern. A new pattern can then bewritten into the device by following the programmingprocedure.PIN NAMESAO-AI2CEOEADDRESSCHIP. ENABLEOUTPUT ENABLE00-0 7 OUTPUTSPGMNCPROGRAMNON CONNECTEDVppVCCA12A7ASA5A4A3A2PGMNCA8A9AllOEAl0CEAO 0700 0601 0502 04Vss 03June 19881/9111

TS27C64AQBLOCK DIAGRAMVee_GND_Vpp_DATA DUTPUTS 00-07oUTPUT ENABLECHIP ENABLEAND PROG LOGICYDECODERYGATINGXDECODER85.538 BITCELL MATRIXABSOLUTE MAXIMUM RATINGS(l)SymbolParameterTamb Operating temperature rangeTS27C64ACQTS27C64AVQTstg Storage temperature rangeVpp(2) Supply voltageVin(2) Input voltages A9Except Vpp, A9Po Max power dissipationLead temperature(Soldering: 10 seconds)ValuehtoTHOto+70-40 to+85-65 to+125-0.6to+14-0.6to+13.5- 0.6 to + 6.251.5+300Notes: 1. "Maximum ratings" are those values beyond which the safety of the device cannot, be guaranteed. Except for "Operating, temperaturerange" they are not meant to imply that the devices should be operated at these limns. The, table of "Electrical characteristics"provides condnions for actual device operation.' ,2. With respect to GNOUnit·C·CVVW·COPERATING MODES~SCE OE A9 PGM Vpp Vee OUTPUTSMODE (~O) (22) (24) (27) (1) (28) (11-13 15-19)READ VIL VIL X VIH Vee Vee DOUTOUTPUT DISABLE VIL VIH X VIH Vee Vee Hi-ZSTANDBY VIH X X X Vee Vee HI-ZHIGH SPEED PROGRAMMING VIL VIH X VIL Vpp Vee DINPROGRAM VERIFY VIL VIL X VIH Vpp Vee DOUT'PROGRAM INHIBIT VIH X X X Vpp Vee Hi-ZELECTRONIC SIGNATURE(3) VIL VIL VH(2) VIH VCC Vee CODENotes: 1. X can be either V 1L or V 1H - 2. VH,=12.0V:O.5V3. Ali address lines at V 1L except A9 'and AO that is toggled from VIL (manufacturer code: 98) to, V'H, (type code: 08).219112

TS27C64AQREAD OPERATIONDC CHARACTERISTICS (Tamb=TL to TH, VCC=5V±10%, VSS=OV; Unless otherwise specified)(S)ValuesSymbol Parameter Test ConditionsMin. Typ.(1) Max.UnitILl Input Load Current VIN = Vcc or GND 10 ,..AILO Output Leakage Current YQUT=VCC or VSS,CE=VIH 10 ,..AVpp Vpp Read Voltage Vcc- 0.7 Vcc VVIL Input Low Voltage -0.1 0.8 VVIH Input High Voltage 2.0 Vcc+ 1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VIOL=O ,..A 0.1VOH Output High Voltage IOH= -400,..A 2.4 VIOH=O ,..A Vce- 0.1ICC2 Vcc Supply Active Current CE=OE=VIL, Inputs=VIH or 10 30 rnATTL LevelsVIL, f=5 MHz, 1/0=0 mAICCSB1 Vcc Supply Standby Current CE=VIH 0.5 1 mAICCSB2 VCC Supply Standby Current CE=VCC 10 100 ,..AIpP1 Vpp Read Current Vpp=VCC=5.5V 100 ,..ANote: 1. Typical conditions are for operation at: Tamb= +25°C, VCC=SV, Vpp=VCC, and VSS=OVAC CHARACTERISTICS(1)(Tamb=TL to TH)(S)27C64A 27C64A 27C64A 27C64ASymbol Parameter Test Conditions ·15 ·20 ·25 ·30 UnitMin Max Min Max Min Max Min MaxtACC Address to Output Delay CE=OE=VIL 150 200 250 300 nsteE CE to Output Delay OE=VIL 150 200 250 300 nstOE Output Enable to CE=VIL 75 80 100 120 nsOutput Delayto~2,4) OE or CE High to output 0 50 0 50 0 60 0 105 nsfloattOH Output Hold from CE=OE=VIL 0 0 0 0 nsaddresses, CE or OEwhichever occured firstCAPACITANCE Tamb= +25°C, f=1 MHz (Note 3)Symbol Parameter Test Conditions Min. Typ. Max. UnitCin Input Capacitance VIN""OV 4 6 pFCout Output Capacitance VOUT=OV 8 12 pFNotes: 1. VCC must be applied at the same time or before Vpp and removed after or at the same time as VPP'Vpp may be connectedto VCC except during program.2. The tOF compare level is determined as follows:High to THREE·STATE, the measured VOH(OC) -O.1VLow to THREE·STATE the measured VOL(OC) +O.1V.3. CapaCitance is guaranteed Bueriodic testing. T amI> = .. 2S oC, f = 1 MHz.4. T OF' is specified from l5E or CE whichever occurs first. This parameter is only sampled and not 100% tested.S. All parameters are specified at V cc = SV ,,; S% for 27C64-1SX, 27C64-20X, 27C64-2SX and 27C64-30X.& .SIiS·1HOMSON':11,. IliIH©OOillm.[§~OO@~H©$3/9113

TS27C64AQAC TEST CONDITIONSOutput Load: 1 TTL gate and CL = 100 pFInput Rise and Fall Times. s20 nsInput pulse levels: O.45V to 2.4VTiming Measurement Reference LevelInputs, OutputsO.SV and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUITI.3V>2.4 ~2b .. ' 20>

TS27C64AQDEVICE OPERATIONThe seven modes of operation of the TS27C64Aare listed in the Operating Modes table. A singleSV power supply is required in the read mode. Allinputs are TIL levels except for Vpp.READ MODEThe TS27C64A has two control functions, both ofwich must be logically active in order to obtain dataat the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, address access time (tACC) is equal tothe delay from CE (tCE). Data is available at theoutQl!ts after a delay OUoE from the falling edgeof OE, assuming that CE has been low and addresseshave been stable for at least tACC-tOE.STANDBY MODEThe TS27C64A has a standby mode which reducesthe maximum power dissipation to 5.5 mW. TheTS27C64A is placed in the standby mode by applyinga TIL high signal to the CE input. When instandby mode, the outputs arEUn.a high impedancestate, independent of the OE input.OUTPUT OR-TYINGBecause EPROMs are usually used in larger memoryarrays, we have provided two control lineswhich accomodate this multiple memory connection.The two control lines allow for:a) the lowest possible memory power dissipation,andb) complete assurance that output bus contentionwill not occur.To use these control lines most eficiently, CE (pin20) should be decoded and used as the primarydevice selecting function, while OE (pin 22) shouldbe made a common connection to all devices inthe array and connected to the READ line from thesystem control bus. This assures that all deselectedmemory devices are in their low power standby modesand that the output pins are active only whendata is desired from a particular memory device.PROGRAMMING MODESCaution: Exceeding 14Von pin 1 (Vpp) will damagethe TS27C64A.Initially, and after each erasure, all bits of theTS27C64A are in the "1" state. Data is introducedby selectively programming "Os" into the desiredbit locations. Although only "Os" will be programmed,both "1s" and "Os" can be presented in thedata word. The only way to change a "0" to a "1"is by ultraviolet light erasure.The TS27C64A is in the progm..mming mode whenth~p input is at 12.5 V and CE and PGM are bothat TIL Low. It is required that a 0.1 p.F capacitor beplaced across Vpp, Vee and ground to suppressspurious voltage transients which may damage thedevice. The data to be programmed is applied 8bits in parallel to the data output pins. The levelsrequired for the address and data inputs are TIL.Programming of multiple TS27C64As in parallelwith the same data can be easily accomplished dueto the simplicity of the programming requirements.Like inputs of the parallel TS27C64As may be connectedtogether when they are programmed withthe same data. A low level TIL pulse applied to thePGM input programs the paralleled TS27C64As.HIGH SPEED PROGRAMMINGThe high speed programming algorithm describedin the flow chart rapidly programs TS27C64A usingan efficient and reliable method particularly suitedto the production programming environment. Typicalprogramming times for individual devices areon the order of 1 minute.PROGRAM INHIBITProgramming of multiple TS27C64As in parallelwith different data is also easily accomplished~using the program inhibit mode. A high level on CEor PGM inputs inhibits the other TS27C64As frombeing programmed. Except for CE, all like inputs(including OE) of the parallel TS27C64As maybe commolJ.:....t. TIL low-level pulse applied to aTS27C64A CE and PGM inputs with Vpp at 12.SVwill program that TS27C64A.PROGRAM VERIFYA verify may be performed on the programmed bitsto determine that they were correctly prQQLammed.The verify is performed with CE and OE at VIL,PGM at VIH and Vpp at 12.5 V.ELECTRONIC SIGNATURE MODEElectronic signature mode allows the reading outof a binary code that will indentify the EPROM manufacturerand type. This mode is intended for useby programming equipment for the purpose of automaticallymatching the device to be programmedwith its corresponding programming algorithm. Thismode is functional in the 25°C ± 5°C ambient temperaturerange that is required when programmingthe TS27C64A. To activate this mode the programmingequipment must force 11.5V to 12.5V on addressline A9 (pin 24) of the TS27C64A. Two bytesmay then be sequenced from the device outputsby toggling address line AO (pin 10) from VILtoVIH. All other address lines must be held at VIL duringelectonic signature mode.5/9115

TS27C64AQERASINGThe TS27C64A is erased by exposure to high intensityultraviolet light through the transparent window.This exposure discharges the floating gateto its initial state through induced photo current.It is recommended that the TS27C64A be kept outof direct sunlight. The UV content of sunlight maycause a partial erasure of some bits in a relativelyshort period of time. Direct sunlight can also causetemporary functional failure. Extended exposureto room level fluorescent lighting will also causeerasure. An opaque coating (paint, tape, label, etc.)should be placed over the package window if thisproduct is to be operated under these lighting conditions.Coverting the window also reduces ICC dueto photodiode currents. An ultraviolet source of2537 A yielding a total integrated dosage of 15 wattseconds/cm2is required. This will erase the partin approximately 15 to 20 minutes if a UV lamp witha 12,000 p.W/cm 2 power rating is used. TheTS27C64A to be erased should be placed 1 inchfrom the lamp and no filters should be used.An erasure system should be calibrated periodically.The disance from lamp to unit should be maintainedat 1 inch. The erasure time is increased bythe square of the distance (if the distance is doubledthe erasure time goes up by a factor of 4).Lamps lose intensity as they age. When a lamp ischanged, the distance, or the lamp is aged, the systemshould be checked to make certain full erasureis occuring. Incomplete erasure will causesymptoms that can be misleading. Programmers,components, and system designs have ben erroneouslysuspected when incomplete erasure wasthe basic problem.PROGRAMMING OPERATIONS(1)(T amb = 25 ± 5°C, VCC = 6.0V ± 0.25V, Vpp = 12.5V ± 0.3V)DC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsII Input Current (all inputs) VI = VIL or VIHMin.VIL Input Low Level (all inputs) -0.1VIH Input High Level 2.0VOL Output low voltage during verify IOL=2.1 mAVOH Output high voltage during verify IOH = - 400 p.A 2.4lee3 Vee Supply current(Program & Verify)IpP2 Vpp supply current (Program) CE=VIL=PGMAC CHARACTERISTICSSymbol Parameter Test ConditionstAS Address Set-up Time 2tOES OE Set-up Time 2tos Data Set-up Time 2tAH Address Hold Time 0tOH Data Hold Time 2tOFP Output enable to output float delay 0tvps Vpp set-up time 2tves Vee set-up time 2Min.ValuesTyp.Valuestpw PGM initial program pulse width 0.95 1.0top~2) PGM overprogram pulse width 2.85teES CE set-up time 2tOE Data valid from OENotes: 1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.2. topw is defined in flow chart.Typ.UnitMax.10 p.A0.8 VVee+ 1 V0.45 VV30 mA30 mAUnitMax.p'sp'sp'sp'sp's130 nsp'sp's1.05 ms78.75 msp's150 ns6/9116

TS27C64AQAC TEST CONDITIONSInput rise and fall times (10% to 90%) :s;20nsInput pulse levels 0.45V to 2.4VInput timing reference level O.BV and 2.0VOutput timing reference level O.BV and 2.0VHIGH SPEED PROGRAMMING WAVEFORMSPROGRAMVERIFy----'=>

TS27C64AQHIGH SPEED PROGRAMMING FLOW CHART8/9118

TS27C64AQORDERING INFORMATIONPart Number Access Time Supply VoltageTS27C64A·15XCQTS27C64A-20XCQTS27C64A-25XCQTS27C64A-30XCQTS27C64A-15CQTS27C64A-20CQTS27C64A-25CQTS27C64A-30CQTS27C64A-15VQTS27C64A-20VQTS27C64A-25VQTS27C64A-30VQ150ns200ns250ns300ns150 ns200 ns250 ns300 ns150 ns200 ns250 ns300 ns5V± 5%5V± 5%5V± 5%5V± 5%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%Temp. Rangeo to +70·Co to +70·Co to +70·Co to + 70·Co to +70·Co to + 70·Co to +70·Co to +70·C-40 to +85·C-40 to +85·C-40 to +85·C-40 to +85·CPackageDIP-2BDIP-2BDIP-28DIP-28DIP-2BDIP-28DIP-28DIP-28DIP-28DIP-28DIP-28DIP-28PACKAGE MECHANICAL DATA28-PIN CERAMIC DIP BULL'S EYEI~.0MIG F.3mmInchesDim.Min Typ Max Min Typ MaxA38.10 1.500B 13.05 13.36 0.514 0.526C 3.90 5.08 0.154 0.2000 3.000.118E O.SO 1.78 0.020 0.070,3 33.021.300F 2.29 2.79 0.090 0.110G 0.40 0.55 0.016 0.022I 1.17 1.42 0.046 0.056L 0.22 0.31 0.009 0.012M 1.52 2.49 0.060 0.098N 16.51 18.00 0.650 0.709P 15.40 15.80 0.606 0.622Q0 6.865.717.36 0.2700.2250.2909/9119

TS27C256Q256K (32K x 8) CMOS UV ERASABLE PROM• FAST ACCESS TIME: 150ns, 170ns, 200ns,250ns, 300ns.• COMPATIBLE TO HIGH SPEEDMICROPROCESSORS ZERO WAIT STATE• 28-PIN JEDEC APPROVED PIN-OUT• LOW POWER CONSUMPTION:ACTIVE 30mA MAXSTANDBY 1 mA MAX• PROGRAMMING VOLTAGE 12.5V• HIGH SPEED PROGRAMMING• ELECTRDNIC SIGNATURE• WILL BE PROPOSED IN PLASTIC PACKAGE(OTP)QDIP-28(Ceramic Buli's Eye)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe TS27C256 is a high speed 262,144 bit UV erasableand electrically reprogrammable EPROMideally suited for applications where fast turnaroundand pattern experimentation are importantrequirements.The TS27C256 is packaged in a 28-pin dual-in-linepackage with transparent lid. The transparent lidallows the user to expose the chip to ultraviolet lightto erase the bit pattern. A new pattern can then bewritten into the device by following the programmingprocedure.PIN NAMESAO-A14CEOEADDRESSCHIP ENABLEOUTPUT ENABLE00-07 OUTPUTS-~Vpp 28 vccA12 27 A14A7 26 A13A6 4 25 ASA5 24 A9A4 I 6 23 A11A3 22 OEA2 I 8 21 Al0Al 20 CEAO 10 19 0700 [ 11 18 0601 [ 12 17 0502 I 13 16 04GND [ 14 15 035- 7516June 19881/9121

TS27C256QBLOCK DIAGRAMVee 0----.GND 0---------­Vpp 0-----DATA OUTPUTS00-07ANDiiE.ffPROGRAMlOGICOuTPUTBUFFERSDECODERy .GA'lINGAO~A14AOQRESSINPUTSDECODER262.14481TCELL MATRIX5-7571ABSOLUTE MAXIMUM RATINGS(l)SymbolTambTstgVpp(2)VIN(2)PoParameterOperating temperature rangeTS27C256CQTS27C256VQStorage temperature rangeSupply voltageInput voltagesExcept VpP.Max power dissipationA9A9Lead temperature(Soldering: 10 seconds)+300°CNotes: 1. "Maximum ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating temperaturerange" they are not meant to imply that the devices should be operated at these limits. The table of '!Electrical characteristics"provides conditions for actual device operation.2. With respect to GNOValueTL to THo to+ 70-40 to+85-65 to+ 125-0.6 to+14- 0.6 to + 13.5-0.6 to+6.251.5Unit°C°CVVWOPERATING MODES~S CE OE A9 Vpp Vee OUTPUTSMODE (20) (22) (24) (1) (28) (11-13 15-19)READ VIL VIL X Vee Vee DOUTOUTPUT DISABLE VIL VIH X Vee Vee Hi-ZSTANDBY VIH X X Vee Vee Hi-ZHIGH SPEED PROGRAMMING VIL VIH X Vpp Vee DINPROGRAM VERIFY VIH VIL X Vpp Vee DOUTPROGRAM INHIBIT VIH VIH X Vpp Vee Hi-ZELECTRONIC SIGNATURE(3) VIL VIL VH(2) Vee Vee CODENotes: 1 - X can be either VIL or VIH - 2 - VH=12.0V±0.5V3 - All address lines at VIL except A9 and AO that is toggled from VIL (manufacturer code: 98) to VIH (type code: 04).2/9122

TS27C256QREAD OPERATIONDC CHARACTERISTICS (Tamb=TL to TH, Vcc=5V±10%, VSS=OV; Unless otherwise specified)(5)Symbol Parameter Test ConditionsMin.ValuesTyp.(1)Max.UnitILl Input Load Current VIN=VCC or GND 10 ~ILO Output Leakage Current VOUT=VCC or VSS,CE=VIH 10 ~Vpp Vpp Read Voltage VCC-0.7 VCC VVIL Input Low Voltage -0.1 0.8 VVIH Input High Voltage 2.0 VCc+1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VIOL=O~ 0.1VOH Output High Voltage IOH= -400~ 2.4 VIOH=O p.AVcc-0.1ICC2 VCC Supply Active Current· CE=OE=VIL, Inputs=VIH or 10 30 mATTL LevelsVIL, f=5 MHz, 1/0=0 mAICCSB1 VCC Supply Standby Current VIH or VIL 0.05 1 mAICCSB2 VCC Supply Standby Current Vcc-0.1V or VSS+0.1V 1 10 ~IpP1 Vpp Read Current Vpp=Vcc=5.5V 10 ~Note: 1. Typical conditions are for oparation at: Tamb= + 25°C, VCC=5V, Vpp=VCC, and VSS=OVAC CHARACTERISTICS(1)(Tamb=TL to TH)(5)27C256 27C256 27C256 27C256 27C256Symbol Parameter Test Conditions -15 -17 -20 -25 -30 UnitMin Max Min Max Min Max Min Max Min MaxtACC Address to Output Delay CE=OE=VIL 150 170 200 250 300 nsteE CE to Output Delay OE=VIL 150 170 200 250 300 nstoE Output Enable to CE=VIL 75 75 75 100 120 nsOutput DelaytDF(2,4) OE or CE High to 0 50 0 50 0 55 0 60 0 75 nsoutput floattoH Output Hold from CE=OE=VIL 0 0 0 0 0 nsaddresses, CE or OEwhichever occured firstCAPACITANCE Tamb= + 25°C, f=1 MHz (Note 3)Symbol Parameter Conditions Min. Typ. Max. UnitCin Input Capacitance VIN=OV 4 6 pFCout Output Capacitance VOUT=OV 8 12 pFNotes:. 1. VCC must be applied at the same time or before Vpp and removed after or at the same time as VPP'Vpp may be connectedto VCC except during program.2. The tOF compare level is determined as follows:High to THREE-STATE, the measured V. OIi(OC) -0.1VLow to THREE·STATE the measured VOL(DC) +0.1V.3. CapaCitance is guaranteed B~erlodic testing. T a"/P = + 25°C, f = 1 MHz.4. T OF' is specified from OE or CE whichever occurs .rst. This parameter is only sampled and not 100% tested.5. All parameters are spacified at V cc = 5V ± 5% for 27C256-15X, 27C256-17X, 27C256-20X, 27C256-25X and 27C256-30X.3/9123

TS27C256QAC TEST CONDITIONSOutput Load: 1 TTL gate and CL= 100 pFInput Rise and Fall Times::s; 20 nsInput pulse leve.ls: 0.45V to 2.4VTiming Measurement Reference LevelInputs, OutputsO.BV and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT2.4 ==>..TEST POINTS

TS27C256QDEVICE OPERATIONThe seven modes of operation of the TS27C256are listed in the Operating Modes table. A single5V power supply is required in the read mode. Allinputs are TTL levels except for Vpp.READ MODEThe TS27C256 has two control functions, both ofwich must be logically active in order to obtain dataat the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, address access time (tACC) is equal tothe delay from CE to Output (tCe). Data is availableat the oUJrults after a delay of tOE from the fallingedge of OE, assuming that CE has been low andaddresses have been stable for at leasttAcc-tOE.STANDBY MODEThe TS27C256 has a standby mode which reducesthe maximum power dissipation to 5.5 mW. TheTS27C256 is placed in the standby mode by applyinga TTL high signal to the CE input. When instandby mode, the outputs are in a high impedancestate, independent of the OE input.OUTPUT OR-TYINGBecause EPROMs are usually used in larger memoryarrays, we have provided two control lineswhich accomodate this multiple memory connection.The two control lines allow for:a) the lowest possible memory power dissipation,andb) complete assurance that output bus contentionwill not occur.To use these control lines most efficiently, CE (pin20) should be decoded and used as the primary deviceselecting function, while OE (pin 22) should bemade a common connection to all devices in thearray and connected to the READ line from the systemcontrol bus. This assures that all deselectedmemory devices are in their low power standby modesand that the output pins are active only whendata is desired from a particular memory device.PROGRAMMING MODESCaution: Exceeding 14Von pin 1 (VppJ will damagethe TS27C256.Initially, . and after each erasure, all bits of theTS27C256 are in the "1" state. Data is introducedby selectively programming "Os" into the desiredbit locations. Although only "Os" will be programmed,both "1s" and "Os" can be presented in thedata word. The only way to change a "0" to a "1"is by ultraviolet light erasure.The TS27C256 is in the programming mode whenthe Vpp input is at 12.5 V and CE is at TTL Low.It is required that a 0.1 I'F capaCitor be placedacross Vpp, VCC and ground to suppress spuriousvoltage transients which may damage the device.The data to be programmed is applied 8 bits in parallelto the data output pins. The levels requiredfor the address and data inputs are TTL.Programming of multiple TS27C256s in parallelwith the same data can be easily accomplished dueto the simplicity of the programming requirements.Like inputs of the parallel TS27C256s may be connectedtogether when they are programmed withthe same data. A low level TTL pulse applied tothe CE input programs the paralleled TS27C256s.HIGH SPEED PROGAMMINGThe high speed programming algorithm describedin the flow chart rapidly programs TS27C256 usingan efficient and reliable method particularly suitedto the production programming environment. Typicalprogramming times for individual devices areon the order of 5 minutes.PROGRAM INHIBITProgramming of multiple TS27C256s in parallelwith different data is also easily accomplishedMusing the program inhibit mode. A high level on CEinput inhibits the other TS27C256S from being pro-9@mmed. Except for CE, all like inputs (includingOE) of the parallel TS27C256s may be common.A TTL low-level pulse applied to a TS27C256 CEinput with Vpp at 12.5 V will program thatTS27C256.PROGRAM VERIFYA verify may be performed on the programmed bitsto determine that they were correctly proQ@mmed.The verify is performed with OE at VIL, CE at VIHand Vpp at 12.5 V.ELECTRONIC SIGNATURE MODEElectronic signature mode allows the reading outof a binary code that will indentify the EPROM manufacturerand type. This mode is intended for useby programming equipment for the purpose of automaticallymatching the device to be programmedwith its corresponding programming algorithm. Thismode is functional in the 25°C ±5°C ambient temperaturerange that is required when programmingthe TS27C256. To activate this mode the programmingequipment must force 11.5V to 12.5V on addressline A9 (pin 24) of the TS27C256. Two bytesmay then be sequenced from the device outputsby toggling address line AD (pin 10) from VIL toVIH. All other address lines must be held at VIL duringelectonic signature mode.5/9125

TS27C256QERASINGThe TS27C256 is erased by exposure to high intensityultraviolet light through the transparent window.This exposure discharges the floating gateto its initial state through induced photo current.It is recommended that the TS27C256 be kept outof direct sunlight. The UV content of sunlight maycause a partial erasure of some bits in a relativelyshort period of time. Direct sunlight can also causetemporary functional failure. Extended exposureto room level fluorescent lighting will also causeerasure. An opaque coating (paint, tape, label, etc.)should be placed over the package window if thisproduct is to be operated under these lighting conditions.Covering the window also reduces ICC dueto photodiode currents.An ultraviolet source of 2537A yielding a total integrateddosage of 15 watt-seconds/cm2 is required.This will erase the part in apprOXimately 15 to20 minutes if a UV lamp with a 12,000 p,W/cm2 powerrating is used. The TS27C256 to be erasedshould be placed 1 inch from the lamp and no filtersshould be used.An erasure system should be calibrated periodically.The distance from lamp to unit should be maintainedat 1 inch. The erasure time is increased bythe square of the distance (if the distance is doubledthe erasure time goes up by a factor of 4).Lamps lose intensity as they age. When a lamp ischanged, the distance is changed, or the lamp isaged, the system should be checked to make certainfull erasure is occuring. Incomplete erasure willcause symptoms that can bemisleading. Programmers,components, and system designs have beenerroneously suspected when incomplete erasurewas the basic problem.PROGRAMMING OPERATIONS(I)(T amb = 25 ± 5°C, VCC = 6.0V ± 0.25V, Vpp = 12.5V ± 0.3V)DC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsII Input Current (all inputs) VI = VIL or VIHMin.VIL Input Low Level (all inputs) -0.1VIH Input High Level 2.0VOL Output low voltage during verify IOL=2.1 mAVOH Output high voltage during verify IOH= -400 pA 2.4lee3Vee Supply current(Program & Verify)IpP2 Vpp supply current (Program) CE=VILAC CHARACTERISTICSValuesTyp.Max.Unit10 pA0.8 VVee+ 1V0.45 VV30 mA30 mASymbol Parameter Test ConditionstAS Address Set-up Time 2toES OE Set-up Time 2tos Da,taSet-up Time 2tAH Address Hold Time 0tOH Data Hold Time 2tOFP Output enable to output float delay 0typs Vppset-up time 2tves Vce set-up time 2Min.Valuestpw PGM initial program pulse width 0.95 1.0toPW2) PGM overprogram pulse width 2.85tOEData valid from OENoles: ,.' Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.2. topw is defined in flow chari.Typ.UnitMax.¢3p.Sp.Sp.Sp.S130 nsp.Sp.S1.05 ms78.75 ms150 ns6/9126

TS27C256QAC TEST CONDITIONSInput rise and fall times (10% to 90%) ~20nsInput pulse levels 0.45V to 2.4VInput timing reference level O.BV and 2.0VOutput timing reference level O.BV and 2.0VHIGH SPEED PROGRAMMING WAVEFORMSVIHADDRESSESv lLXVIHDATAVIL12.5 VvppVee---/5V6V/5VADDRESS'ASIPROGRAMPROGRAM VERIFYSTABLEIDATA IN STABLEIDSi+----~IVPStvesIHIGH Z1r~DATA OUT VALIDV~I-f----',IXtAH -I DFPVIHCEOEVILVIHVIL~tpw.~~ \IOES 'tOE~ r---=----)-5-9623/11. The input timing reference level is O.B for VIL and 2.0V for VIH2. toE and tOFP are characteristics of the device but must be accommodate by the programmer.3. When programming the TS27C256, a O. 1 ~F capacitor is required across Vpp and ground to suppress spurious voltage transiens whichcan damage the device.7/9127

TS27C256QHIGH SPEED PROGRAMMING FLOW CHART8/9128

TS27C256QORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageTS27C256·15XCQTS27C256-17XCQTS27C256-20XCQTS27C256·25XCQTS27C256-30XCQTS27C256-17CQTS27C256-20CQTS27C256·25CQTS27C256-30CQTS27C256-15VQTS27C256-17VQTS27C256·20VQTS27C256·25VQTS27C256-30VQ150 ns170 ns200 ns250 ns300 ns170 ns200 ns250 ns300 ns150 ns170 ns200 ns250 ns300 ns5V± 5%5V± 5%5V± 5%5V± 5%5V± 5%5V±10%5V±10%5V±10%5V±10%5V± 5%5V±10%5V±10%5V±10%5V±10%to +70·C Dlp·28to +70·C Dlp·28o to +70·C Dlp·28to +70·C Dlp·28o to +70·C Dlp·28to +70·C Dlp·28to +70·C DIP·28to +70·C Dlp·28o to +70·C Dlp·28-40 to +85·C Dlp·28-40 to +85·C Dlp·28-40 to +85·C Dlp·28-40 to +85·C Dlp·28-40 to +85·C Dlp·28PACKAGE MECHANICAL DATA28·PIN CERAMIC DIP BULL'S EYE~'I:M I ~ F.3/' ~ jam::::}l-P058·E/4mmInchesDim.Min Typ Max Min Typ MaxA 38.10 1.500B 13.05 13.36 0.514 0.526C 3.110 5.08 0.154 0.200D 3.00 0.118E 0.50 1.78 0.020 0.070e3 33.02 1.300F 2.29 2.79 0.0lI0 0.110G 0.40 0.55 0.016 0.022I 1.17 1.42 0.046 0.056L 0.22 0.31 0.009 0.012M 1.52 2.49 0.080 0.098N 1851 18.00 0.650 0.708P 15.40 15.80 0.aJ6 0.822Q 5.71 0.2250 6.86 7.38 0.270 0.29!i9/9129

,1,;'"

u SGS-1HOMSON~ L [K'A]D©OO@rn[brn©'[j'OO@[R!]D©~ ST27C10011024K (128K x 8) CMOS UV ERASABLE PROMADVANCED DATA• 8 BITS OUTPUTS• FAST ACCESS TIME 120ns.• LOW "CMOS" CONSUMPTION SOmA (MAX.)• PROGRAMMING VOLTAGE 12.SV• ELECTRONIC SIGNATURE FOR AUTOMATEDPROGRAMMING• PROGRAMMING TIMES IN THE 20 SECONDSRANGE.DESCRIPTIONThe ST27C1001 is a high speed 1 Mbit UV erasableand electrically programmable EPROM ideallysuited for 8-bit microprocessors systemsrequiring large programs.It is organized as 131072 words by 8 bits, and packagedin a 32 pins Ceramic DIP Buli's eye package.ST will also introduce the following versions basedon the same architecture but with different configurations.They are:• ST27C1011 is a page addressed 1024K(8 x 16K x 8) device, packaged in a 28 pin DIPfor easy replacement of 64K and 128K standardEPROM versions.• ST87C1011 is the same device as theST27C1011 with latched addresses for designoptimization in multiplexed bus environment.• ST27C1000 is organized as 128K x 8 bits witha ROM compatible pinout.• ST87C1000 is the same device as theST27C1000 with latched addresses for designoptimization in multiplexed bus environment.PIN NAMESAO-A16CEOEPGMADDRESS INPUTCHIP ENABLE INPUTOUTPUT ENABLEPROGRAM00-0 7 DATA INPUT/OUTPUTNCNON CONNECTEDFDIP-32(Ceramic Bull's eye)(Ordering Information at the end of the datasheet)VppPIN CONNECTIONS~ vccA16 31 PGMA15 30 NCA 12 4 29 A14A7 ·5 28 A13A6 6 27 A8AS 26 A9A4 25 ~ AllA3 24 ~ DEA2 10 Z3 Al0Al 11 22 CE.AO 12 21 0700 13 20 0601 14 19 0502 15 18 04GNO 16 17 03S - 10651June 19881/2This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.131

ST27C1001BLOCK DIAGRAMv P P cr------ovC C cr------o­GN D cr------o-DATA OUTPUTS00-015PGMOEITOUTPUTBUFFERSyDECODERyGATINGAO-A10ADDRESSINPUTSXDECODER1.048.576CELL MATRIX5-106562/2132

M27C10241024K (64K x 16) CMOS UV ERASABLE PROMPRELIMINARY DATA• FAST ACCESS TIME:120ns MAX M27C1024-12XF1/M27C1024-12F1150ns MAX M27C1024-15XF1/M27C1024-15F11M27C1024-15XF6200ns MAX M27C1024-20XF1/M27C1024-20F11M27C1024-20XF6250ns MAX M27C1024-25XF1/M27C1024-25F11M27C1024-25XF6• 0 TO + 70°C STANDARD TEMPERATURERANGE• SINGLE + 5V POWER SUPPLY• LOW STANDBY CURRENT (1mA MAX)• TTL PROGRAMMING• VERY FAST AND RELIABLEPROGRAMMING ALGORITHM• ELECTRONIC SIGNATUREDESCRIPTIONThe M27C1024 is a 1,048,576-bit ultraviolet erasableand electrically programmable read only memory(EPROM). It is organized as 65,536 words by 16 bitsand manufactured using SGS-THOMSON' CMOS­E4 process. The M27C1024 with its single + 5V powersupply and with an access time of 120ns, is idealfor use in 16 bit microprocessor system allowing fullspeed operation without WAIT states. In high performanceCPU's (10MHz), the M27C1024 has animportant feature which is tQ..,§eparate the outputcontrol, OutpuLEnablILJOE) from the ChipEnable control (CE). The OE control eliminates buscontention in multiple bus microprocessor systems.The M27C1024 also features a standby modewhich reduces the power dissipation without increa­Sing access time. The active current is 50mA whilethe maximum standby current is only 1 mA. Thestandby mode is achieved by applying a TTL-highSignal to the CE input. The M27C1024 enablesimplementation of new, advanced systemswith firmware intensive architectures.The combination of the M27C1024s high density,and new advanced microprocessors having megabitaddressing capability provides designers withopportunities to engineer user-friendly, high reliability,high-performance systems. The M27C1024large storage capability enables it to function asa high density software carrier. The M27C1024 hasan "Electronic Signature" that allows programmersto automatically identify device type and pinout.June 1988FDIP-40(Ceramic Bull's Eye)(Ordering Information at the end of the datasheet)PIN NAMESAO-A15CEOEPGMVppPIN CONNECTIONS~ VccIT 2 39 PGM015 3 38 NC014•37 A15013 36 A14012 35 A 13all 34 A 12010 33 All09 32 A 1008 10 31 A9GND 11 3C GND07 12 29 A806 13 28 A705 14 27 A604 15 26 AS03 16 25 A402 17 2' A301 18 23 A 200 19 22 A1OE 20 21 AD5-10139ADDRESS INPUTCHIP ENABLE INPUTOUTPUT ENABLEPROGRAM00-015 DATA INPUT/OUTPUTNCNON CONNECTED1/10133

M27C1024BLOCK DIAGRAMVpp 0----:---+VCC 0---­GND 0----DATA OUTPUTS• 00-015PGM -,_OEITOUTPUTBUFFERSyDECODERyGATINGAO'A15ADDRESSINPUTSXDECODER5 -101~OABSOLUTE MAXIMUM RATINGSSymbolParameterValueVI All Input or Output voltages with respect to ground + 6.5 to - 0.6Vpp Supply voltage with respect to ground + 14 to - 0.6Tamb Ambient temperature under bias IFl -10 to +80IF6 -50 to +95Tstg Storage temperature range -65 to + 125Voltage on pin 31 with respect to ground + 13.5 to -0.6Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device, This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.UnitVV°C°C°CVOPERATING MODES=----------:NS CE OE A9 PGM VppMODE(2) (20) (31) (39) (1)OUTPUTSREAD L L X H Vee DOUTOUTPUT DISABLE L H X H Vee HIGHZSTANDBY H X X X Vee HIGH ZPROGRAM L X X L Vpp DINPROGRAM VERIFY L L X H Vpp DOUTPROGRAM INHIBIT H X X X Vpp HIGH ZELECTRONIC SIGNATURE L L VH H Vee CODENOTE: X=DON'TeARE; VH= 12V ±O.SV; H=HIGH; L=LOW2/10134

M27C1024READ OPERATIONDC AND AC CONDITIONSSelection Code -12XFlI-15XFl -12Fl/-15Fl - 15XF6/-20XF6- 20XFlI- 25XFl - 20Fl/- 25Fl -25XF6Operating Temperature Range o to 70·C o to 70·C -40 to 85·CVee Power Supply (1,2) 5V ±5% 5V ±10% 5V ±5%Vpp Voltage (2) Vpp = Vee Vpp = Vee Vpp = VeeDC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsValuesMin, Typ. (2) Max.III Input Load Current VIN=5.5V 10 p.AILOOutput LeakageCurrent VOUT=5.5V 10 p.Aleel Vee Current Standby CE=VIH 1 mAICC2 Vee Current Active CE=OE=VIL @f=8MHz 20 50 mAVIL Input Low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 Vee+ 0.5 VVOL Output Low Voltage IOL=2.1 mA 0.45 VVOH Output High Voltage IOH = - 400 p.A 2.4 VUnitAC CHARACTERISTICSSymbolParameterVcc±10% 27Cl024-121 27Cl024·151 27Cl024-201 27Cl024-251Vcc±5% 27Cl024-12X 27Cl024-15X 27Cl024-20X 27Cl024-25XTest Condition Min Max Min Max Min Max Min MaxtAee Address to Output Delay CE=OE=VIL 120 150 200 250 nsteE CE to Output Delay OE=VIL 120 150 200 250 nstoE OE to Output Delay CE=VIL 60 60 75 75 nstOF(3) OEHigh to Output Float CE=VIL 0 60 0 60 0 90 0 90 nstOH Output Hold from Address CE CE=OE=VIL 0 0 0 0 nsor OE Whichever Occurred FirstUnitCAPACITANCE(4) (T amb = 25°C, f = 1 MHz)Symbol Parameter Test Conditions Min. Typ. (2) Max. UnitCIN Input Capacitance VIN=OV 4 6 pFCOUT Output Capacitance VOUT=OV 8 12 pFNotes:1. Vcc must be applied simuHaneously or before Vpp and removed simultaneously or after Vpp.2. Typical values are for T amb = 25°C and nominal supply voltages.3. This parameter is only sampled and not 100% tested. Output Float is defined as the point where data is no longer driven-seetiming diagram.4. This parameter is only sampled and not 100% tested.3/10135---~--'------------------------~-------

M27C1024AC TEST CONDITIONSOutput Load: 1 OOpF + 1TTL GateInput Rise and Fall Times: :s;20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT2.4=>

M27C1024DEVICE OPERATIONThe modes of operations of the M27C1024 are listedin the Operating Modes. A single 5V powersupply is required in the read mode. All inputs areTTL levels except for 12V on A9 for Electronic Signature.READ MODEThe M27C1024 has two control functions, both ofwhich must be logically active in order to obtain dataat the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, the address access time (tAccl is equalto the delay from CE to output (tCE). Data is availableat the o'!:!!puts after delay al!oE from the faIlingedge of OE, assuming that CE has been lowand addresses have been stable for at leasttACC-tOE·The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active Current level, and transientcurrent peaks that are produced by the fallingand rising edges of CE. The magnitude of this transientcurrent peaks is dependent on the output capacitiveand inductive loading of the device. Theassociated transient voltage peaks can be suppressedby complying with the two line output controland by properly selected decoupling capacitors. Itis recommended that a 1 I'F ceramic capacitor beused on every device between Vcc and GND. Thisshould be a high frequency capacitor of low inherentinductance and should be placed as close tothe device as possible. In addition, a 4.7 I'F bulkelectrolytic capacitors should be used betweenVcc and GND for every eight devices. The bulk capacitorshould be located near where the powersupply is connected to the array.The purpose of the bulk capacitor is to overcomethe voltage drop caused by the inductive effectsof PCB traces.STANDBY MODEThe M27C1024 has a standby mode which reducesthe maximum active power current from 50 mAto 1 mAo The M27C1024 is placed in the standbymode by applying a TTL high signal to the CE input.When in the standby mode, the outputs arein a high impedance state, independent of the OEinput.TWO LINE OUTPUT CONTROLBecause EPROMs are usually used in larger memoryarrays, the product features a 2 line controlfunction which accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE shouldbe made a common connection to all devices inthe array and connected to the READ line from thesystem control bus. This assures that all deselectedmemory devices are in their low power standbymode and that the output pins are only activewhen data is desired from a particular memorydevice.SYSTEM CONSIDERATIONSThe power switching characteristics of CMOS-E4EPROMs require careful decoupling of the devices.PROGRAMMINGCaution: exceeding 14Von Vpppin will permanentlydamage the M27C 1 024.When delivered, and after each erasure, all bits ofthe M27C1024 are in the "1" state. Data is introducedby selectively programming "Os" into the desiredbit locations. Although only "Os" will be programmed,both "1s" and "Os" can be present inthe data word. The only way to change a "0" toa "1" is by ultraviolet light erasure. The M27C10,24is in the programming mode when Vpp input is at12.5V and CE and PGM are at TTL-low.The data to be programmed is applied 16 bits inparallel to the data output pins. The levels requiredfor the address and data inputs are TTL.Vee is specified to be 6.25V ±0.25V.VERY FAST AND RELIABLE PROGRAMMINGALGORITHM = PRESTO IIPRESTO II programming algorithm, available forthe M27C1024 is an enhancement of the PRESTOalgorithm used for the M27512.During programming and verify operation a MAR­GIN MODETM Circuit is automatically activated. Itprovides adequate margin on threshold voltage ofprogrammed cells, thus writing margin is independentfrom Vee in verify mode and over programpulse is not necessary, reducing programming timedown to a theoretical value of 6 seconds.5/10137

M27C,1024PROGRAM INHIBITProgramming of multiple M27C1024s in . parallelwith different data is alSO easily accomplished. Exceptfor CE', all like inputs of the parallel M27C1024may be common. A TIL low level pulse applied toa M27C1024's CE input, with Vpp at 12.5V, willprogram that M27C1024. A high level CE input inhibitsthe other M27C1024sfrom being programmed.VCC is specified to be 6.25V ±0.25V.PROGRAM VERIFYA verify (read) should be performed on the programmedbits to determine that they werecorre

M27C1024PROGRAMMING OPERATION (Tamb=25°C ±5°C, V ee(1)=6.25V ±O.25V, Vpp(l) = 12.5V ±O.5V)DC AND OPERATING CHARACTERISTIC:SymbolParameterTest Conditions(See note 1)ValuesMin. Typ. Max.UnitILl Input Current (All Inputs) VIN = VIL or VIH 10 ~AVIL Input Low Level (All Inputs) -0.1 0.8 VVIH Input High Level 2.0 Vee+ 0.5 VVOL Output Low Voltage During Verify IOL=2.1 mA 0.45 VVOH Output High Voltage During Verify IOH= -400 ~A 2.4 Vlee2 Vee Supply Current 20 50 mAIpP2 Vpp Supply Current (Program) CE=VIL 50 mAVIO A9 Electronic Signature Voltage 11.5 12.5 VAC CHARACTERISTICSSymbolParameterTest ConditionsValues(See note 1) Min. Typ. Max. UnittAS Address Setup Time 2 /istOES OE Setup Time 2 /istos Data Setup Time 2 /is ,tAH Address Hold Time 0 /istOH Data Hold Time 2 /istOFP(2) Output Enable Output Float Delay 0 130 nstvps Vpp Setup Time 2 /istves Vee Setup Time 2 /isteEs CE Setup Time 2 /istpw PGM Initial Program Pulse Width 95 100 105 /istOE Data Valid from OE 100 nsNotes:I. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.2. This parameter is only sampled and not 100% tested.Output Float is defined as the point where data is no longer driven (see timing diagram).7/10139

M27C1024PROGRAMMING WAVEFORMSVIHADDRESSESVILVIHDATAVILXlASIIDATAPROGRAMADDRE':>':> ':>TABLEIN ':>TABLEIIVERIFY1\ JHZI \DATA OUT VALID /~JIKlOS IDH IDFPIAHVpp12.S VSVJ IVPSVee6VSV/lvesaVIHVIL1\leESVIHPGMOEVILV1HVIL5-10658IpW~ IOE -.:..::..."\Notes:1. The input timing reference level is O.BV for a VIL and 2V for a VIH.2. tOE and tOPF are characteristics of the device but must be accommodated by the programmer.3. When programming the M27C1024 a O.1~F capacitor is required across Vpp and GROUND to suppress spurious voltage transientswhich can damage the device.8/10140

M27C1024PRESTO II PROGRAMMING ALGORITHMFAILINCREMENT ADDRESSNO5 ~ 9769129/10141

M27C1024ORDERING INFORMATIONPart NumberM27C1024·12F1M27C1024·15F1M27C1024·20F1M27C1024·25F1M27Cl024·12XFlM27Cl024·15XFlM27Cl024·20XF1M27Cl024·25XF1M27C1024·15XF6M27Cl024·20XF6M27Cl024·25XF6Access Time120 n5150 n5200 ns250 ns120 ns150 ns200 ns250 ns150 ns200 ns250 nsSupply Voltage5V±10%5V±10%5V±10%5V±10%5V± 5%5V± 5%5V± 5%5V± 5%5V± 5%5V± 5%5V± 5%Temp. Rangeo to + 70·Co to + 70·Co to + 70·Co to + 70·Co to + 70·Co to + 70·Co to + 70·Co to + 70·C-40 to +85·C-40 to +85·C-40 to +85·CPackageDIP·40DIP·40Dlp·40DIP·40DIP·40Dlp·40Dlp·40DIP·40DIP·40DIP·40Dlp·40PACKAGE MECHANICAL DATA40·PIN CERAMIC DIP BULL'S EYEmminchesDim.Min Typ Max Min Typ MaxAB 14.5053.4014.90 0.5712.1020.587C 3.90 5.08 0.154 0.200D 3.400.134E 0.50 1.78 0.020 0.07003 48.261.900F 2.29 2.79 0.090 0.110G 0.40 0.55 0.016 , 0.022I 1.27 1.52 0.050 0.060l 0.220.31 0.009 0.012M 1.52 2.49 0.060 0.098N 15.62 17.78 0.615 0.700P 15.40 15.80 0.606 0.622QK 7.905.718.38 0.3110.2250.330Kl 10.41 10.92 0.410 0.43010/10142

EPROM DEVICES143

ST2764AP64K (8K x 8) NMOS ONE TIME PROGRAMMABLE ROM• FAST ACCESS TIME: 180ns• 0 to + 70°C STANDARD TEMPERATURERANGE• S1.NGLE + 5V POWER SUPPLY• :1:10% VCC TOLERANCE AVAILABLE• LOW STANDBY CURRENT (35mA MAX)• TIL COMPATIBLE DURING READ ANDPROGRAM• FAST PROGRAMMING ALGORITHM• ELECTRONIC SIGNATUREPDIP-28(Plastic Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe ST2764AP.is a 65,536-bit one time programmableread only memory (OTP "ROM). It is organizecias 8,192 words by 8 bits and manufacturedusing SGS-THOMSON' NMOS-E3 process.The ST2764AP with its single + 5V power supplyand with an access time of 200ns, is ideal for usewith high performance + 5V microprocessor suchas Z8, zeo and Z8000. The ST2764AP has an importantfeature which is to separate the output control,Ou~ Enable (DE) from the Chip Enablecontrol (CE). The OE control eliminates bus contentioninmultiple bus microprocessor systems.The ST2764AP also features a standby mode whichreduces the power diSSipation without increasingaccess time. The 'active current is 75mA while themaximum standby current is only 35 mA, a 53%saving. The standby mode is achieved by applyinga TIL-high signal to the CE input. The ST2764APhas an "Electronic Signature" that allows programmersto automatically identify device type andpinout.The ST2764AP is available in a 28-lead dual in-lineplastic package and therefore can not be rewritten.PIN NAMESAO-A12CEOEPGMN.C.Vpp~ VeeAIZ 27 m;;A7 2& 'I.e.AI 25 ASAS 2' AtA4 23 AllU 22 iiiAI 2' AIDAI 20 tlAD .0 '9 0700"II 0101 12 17 0502 .3 .6 04GND 14 IS 035-1311.ADDRESS INPUTCHIP ENABLE INPUTOUTPUT ENABLE INPUTPROGRAMNO CONNECTION00-07 DATA INPUT/OUTPUTJune 19881110145

ST2764APBLOCK DIAGRAMDATA OUTPUT00· 01OUTPUT ENABLECHIP ENABLE ANDPROe;. LOGICOUTPUTBUFFERSvDECODERvGATING40-0412ADDRESSINPUTSDECODER65.536BITCELL MATRIX5-6361ABSOLUTE MAXIMUM RATINGSSymbolParameterValuesVI All Input or Output voltages with respect to ground +6.5 to -0.6Vpp Supply voltage with respect to ground +14 to -0,6Tamb Ambient temperature under bias -10to+80Tsto Storage temperature range - 65 to +125Voltage on pin 24 with respect to ground + 13.5 to - 0.6VStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.UnitVV·C·COPERATING MODES~ CE OE PGM Vpp Vee OUTPUTSA9 (11-13,(20) (22) (24) (27) (1) (28)MODE15-19)READ VIL VIL X VIH Vee Vee DOUTOUTPUT DISABLE VIL VIH X VIH Vee Vee HIGH ZSTANDBY VIH X X X Vee Vee HIGHZFAST PROGRAMMING VIL VIH X VIL Vpp Vee DINVERIFY VIL VIL X VIH Vpp Vee DOUTPROGRAM INHIBIT VIH X X X Vpp Vee HIGH ZELECTRONIC SIGNATURE VIL VIL VH VIH Vee Vee CODESNOTE: X can be V 1H or V 1l2110146

ST2764APREAD OPERA nONDC AND AC CONDITIONSSelection Code -18X1-20X -18/-20/- 25/-30Operating Temperature Range o to 70'C o to 70'eVee Power Supply (1,2) 5V ±5% 5V ±10%Vpp Voltage (2) Vpp = Vee Vpp = VeeDC AND OPERATING CHARACTERISTICSValuesSymbol Parameter Test ConditionsMin. Typ.(3) Max.UnitIII Input Load Current VIN=5.5V 10 p.AILO Output Leakage Current VOUT=5.5V 10 p.AIpp1(2) Vpp Current Read Vpp=5.5V 5 rnAlee1(2) Vee Current Standby CE=VIH 35 rnAlee2(2) Vee Current Active CE=OE=VIL 75 rnAVIL Input Low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 Vee + 1 VVOL Output Low Voltage IOL=2.1 rnA 0.45 VVOH Output High Voltage IOH = - 400 p.A 2.4 VVPP(2) Vpp Read Voltage Vee=5V±0.25V 3.8 Vee VAC CHARACTERISTICSVcc± 5% 2764A·18X 2764A·20XSymbol Parameter Vcc±10% 2764A·,18 2764A·20 2764A,·25 2764A·30 Unit~est Condltlonl Min Max Min Max Min Msx Min MaxtAee Address to Output Delay CE=OE=VIL 180 200 250 300 nsicE CE to Output Delay OE=VIL 180 200 250 300 nstoE OE to Output Delay CE=VIL 65 75 100 120 nstOF(4) OE High to Output Float CE=VIL 55 0 55 0 60 0 105 nstOH Output Hold from Address CE=OE= VIL 0 0 0 0 nsCE or OE WhicheverOccurred FirstSymbol Parameter Test Conditions Min. Typ. Max. UnitCIN Input Capacitance VIN=OV 4 6 pFCOUT Output Capacitance VOUT=OV 8 12 pFNotes:1. Yee must be applied simultaneously or before Ypp and removed simultaneously or after Ypp.2. Ypp may be connected directly to Yee except during programming.The supply current would then be the sum of Icc and IpPl'3. Typical values are for T 8mb = 2s'e and nominal supply vOltageS.. ' ,4. This parameter is only sampled and not 100% tested. Output Float is defined as the point where data is no longer driven-seetiming diagram.S. This parameter is only sampled and is not 100% tested.3110147

ST2764APREAD OPERATION (Continued)AC TEST CONDITIONSOutput Load: 100pF + 1 TTL GateInput Rise and Fall Times: :s;20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT"4=>('0'0> TEST POINTS < .O.AS 0.8 Q.8I ~~~~TEST1N914[ 3.3Kn111---1---0 OUTI Cl •• OOP: ...,CL INCLUDES JIG CAPACITANCEAC WAVEFORMSES)ADDRESS VALID-.,D(.....JI'CE~~ tOF(2..4)I---I 'OE 131t ACc (3)~-I-HIGH ZIIIIII v\\\\\AUD 0 UTPUT11.\ 1\ HIGH ZU,V5-6809Notes:1. Typical values are for T amb = 25°C and nominal supply voltage.2. This parameter is only sampled and not 100% tested.3. DE may be delayed up to tACC - tOE after the falling edge CE without impact on tACC.4. tDF is specified from DE or ITwhichever occurs first.4/10148

ST2764APDEVICE OPERATIONThe seven modes of operations of the ST2764APare listed in the Operating Modes. A single 5V powersupply is required in the read mode. All inputsare TTL levels except for Vpp and 12V on A9 forElectronic Signature.READ MODEThe ST2764AP has two control function, both ofwhich must be logically satisfied in order to obtaindata at the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection.Assuming that addresses are stable, address accesstime (tAccl is equal to delay from CE to output(tCE). Data ~available at the Q!!!puts after thefalling edge of OE, assuming that CE has been lowand addresses have been stable for at leasttACe-tOE·STANDBY MODEThe ST2764AP has a standby mode which reducesthe maximum active power current from 75 mA to35 mAo The ST2764AP is placed in the standbymode by applying a TTL high signal to the CE input.When in the standby mode, the outputs are in ahigh impedance state, independent of the OE input.OUTPUT OR-TIEINGBecause OTPs are usually used in larger memoryarrays, the product features a 2 line control functionwhich accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus.This assures that all deselected memory devicesare in their low power standby mode and that theoutput pins are only active when data is desiredfrom a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and tran-sient current peaks that are produced by the faIlingand rising edges of CEo The magnitude of thistransient current peaks is dependent on the outputcapacitive and inductive loading of the device.The associated transient voltage peaks can be suppressedby complying with the two line output controland by properly selected decoupling capacitors.It is recommended that a 1 p.F ceramic capacitorbe used on every device between Vcc and GND.This should be a high frequency capacitor of lowinherent inductance and should be placed as closeto the device as possible. In addition, a 4.7 p.F bulkelectrolytic capacitors should be used betweenVce and GND for every eight devices. The bulkcapaCitor should be located near where the powersupply is connected to the array. The purposeof the bulk capacitor is to overcome the voltagedrop caused by the inductive effects of PCB traces.PROGRAMMINGCaution: exceeding 14V on pin 1 (Vpp) willdamage the ST2764AP.When delivered, all bits of the ST2764AP are in the"1" state. Data is introduced by selectivelyprogramming "Os" into the desired bit locations.Although only "Os" will be programmed, both "Is"and "Os" can be present in the data word.The ST2764AP is in the p~ramming mode whenVpp input is at 12.5V and CE and PGM are at TTLlow. The data to be programmed is applied 8 bitsin parallel to the data output pins. The levels requiredfor the address and data inputs are TTL.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsST2764AP EPROMs using an efficient and reliablemethod suited to the production programmingenvironment. Programming reliability is also ensuredas the incremental program margin of eachbyte is continually monitored to determine whenit has been successfully programmed. A flowchartof the ST2764AP Fast Programming Algorithm isshown on the last page. The Fast Programming Algorithmutilizes two different pulse types: initial andoverprogram.The duration of the initial P(;M pulse (s) is one millisecond,which will then be followed by a longeroverprogram pulse of length 3Xmsec. (X is an iterationcounter and is equal to the number of the initialone millisecond pulses applied to a particularST2764AP location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte are providedfor before the over program pulse is applied.5/10149

ST2764APDEVICE OPERATION (Continued)The entire sequence of program pulses and byteverifications is performed at Vcc = 6V andVpp = 12.5V. When the Fast Programming cyclehas been completed, all bytes should be comparedto the original data with Vcc=Vpp=5V.PROGRAM INHIBITProgramming of multiple ST2764APs in parallel withdifferent data is also easily accq!!}plished. Exceptfor a:, all like inputs (including OE) of the parallelST2764AP may be common. A TTL low pulse apeplied to a ST2764AP's a: input, with Vpp at 12.5V,will program that ST2764AP. A high level a: inputinhibits the other ST2764AP from beingprogrammed.PROGRAM VERIFYA verify should be performed on the programmedbits to determine that they were corre

ST2764APPROGRAMMING OPERATION (Tamb=25°C :!:5°C, Vee(I)=6V :!:O.25V, Vpp(l) = 12.5V :!:O.3V)DC AND OPERATING CHARACTERISTICValuesSymbol Parameter Test ConClltlonsMin. Typ. Max.ILl Input Current (All Inputs) VIN = VIL or VIH 10VIL Input Low Level (All Inputs) -0.1 0.8VIH Input High Level 2.0 VeeVOL Output Low Voltage During Verify IOL=2.1 mA 0.45VOH Output High Voltage During Veri!9 IOH = - 400 p,A 2.4lee2 Vee Supply Current (Program & Verify) 75IpP2 Vpp Supply Current (Program) CE=VIL 50VIO A9 Electronic Signature Voltage 11.5 12.5Unitp,AVVVVmAmAVAC CHARACTERISTICSValuesSymbol Parameter Test ConditionsMin. Typ. Max.tAS Address Setup Time 2toES OE Setup Time 2tos Data Setup Time 2tAH Address Hold Time 0tOH Data Hold Time 2tOFP(4) Output Enable Output Float Delay 0 130tvps Vpp Setup Time 2tves Vee Setup Time 2tCES CE Setup Time . p,stpw PGM Initial Program Pulse Width (see Note 3) 0.95 1.0 1.05topw PGM Overprogram Pulse Width (see Note 2) 2.85 78.75tOE Data Valid from OE 150Unitp,sp,sp,sp,sp,snil"p,Sp,S2msmsnsNotes:I. Vcc must be applied simultsneously or before Vpp and removed simultaneously or after Vpp.2. The length of the overprogram pulse may vary from 2.85msec to 78.75msec as a function of the iteration counter value X.3. Intlial Program Pulse width tolerance is Imsec =5%.4. This parameter is only sampled and not 100% tested.Output Float is defined as the point where data is no longer driven (see timing diagram).7110151

ST2764APPROGRAMMING WAVEFORMSV1HADDRESSES;~V1LV1HDATAV1LVpplASlOS---~12.5 V5V ~ IvPSDATAPROGRAMADDRESS STABLEIN STABLE'(IDFPIIHILVERIFYIeIAHDATA OUT ~ALlD ~Vee6V5V~ IvesCEPGMDEV1HV1L\ICESV1H"V1LVIHV1L~/~IOPW-\ ~~ ~5-154 312Notes:1. The input timing reference level is O.SV for a V1L and 2V for a V1H.2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.3. When programming the ST2764AP a O.1~F capaCitor is required across Vpp and GROUND to suppress spurious vol!age transientswhich can damage the device.8/10152

ST2764APFAST PROGRAMMING FLOWCHART9/10153

ST2764APORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageST2764A-18XCPST2764A-20XCPST2764A-18CPST2764A-20CPST2764A-25CPST2764A-30CP180 ns200 ns180 ns200 ns250 ns300 ns5V± 5%5V ± 50/05V±10%5V±10%5V±10.%5V±10%to + 70 D Co to + 70 D Cto + 70 D Cto + 70°Co to + 70 D Co to + 70°CDIP-28DIP-28DIP-28DIP-28DIP-28DIP-28PACKAGE MECHANICAL DATA28-PIN PLASTIC DIPP043-D/3" --Fc1,-I--'-'--.. 1-mminchesDim.Min Typ Max Min Typ MaxAa 1 0,63 0,025B 0,45 omsb 1 0,23 0,31 0,009 0,012b 2 1,27 0,050C0 37,34 1,470E 15,20 16,68 0,598 0,6572,54 0,100•e3 33,02 1.300.4F 14,10 0,555I 4,45 0,175L 3,30 0,130KlK210110154

ST27128AP128K (16K x 8) NMOS ONE TIME PROGRAMMABLE ROM• FAST ACCESS TIME: 150ns• 0 to + 70°C STANDARD TEMPERATURERANGE• SINGLE + 5V POWER SUPPLY• :10% Vcc TOLERANCE AVAILABLE• LOW STANDBY CURRENT (40mA MAX)• TTL COMPATIBLE DURING READ ANDPROGRAM• FAST PROGRAMMING ALGORITHM• ELECTRONIC SIGNATUREPDIP-28(Plastic Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONS[)ESCRtPTlONrhe ST27128AP is a 131,072-bit one time programmableread only memory (OTPROM). It is organizedas 16,384 words by 8 bits and manufacturedusing SGS-THOMSON' NMOS-E3 process.rhe ST27128AP with its single + 5V power supplyand with an access time of 200ns, is ideal foruse with high performance + 5V microprocessorsuch as Z8, Z80 and Z8000. The ST27128AP hasan important feature which is to separate the outputcontrol, ~tut Enable (OE) from the Chip Enablecontrol (CE). The OE control eliminates buscontention in muHiple bus microprocessor systems.The ST27128AP also features a standby modewhich reduces the power dissipation without increasingaccess time. The active current is 85mA whi-Ie the maximum standby current is only 4OmA, a53% saving. The standby mode is achieved byapplyinga TIL-high signal to the CE input. TheST27128AP has an .. Electronic Signature" that allowsprogrammers to automatically identify devicetype and pinout. The ST27128AP is availablein a 28-lead dual in-line plastic package and the·refore cannot be rewritten.PIN NAMESAO-A13CEOEPGM00-07~--Vpp 1 ~ 2Bb VeeAU 1 27b PGMA7 1&b Al3A6 15 A8A5 [ 5 24 A9A4 ( 6 23 AllA3 17 21 DEA2 21 AIOAl 20 C1:AO 10 19 0700 11 1B 0601 11 17 0502 13 16 04GND 14 15 03$-7663ADDRESS INPUTCHIP ENABLE INPUTOUTPUT ENABLE INPUTPROGRAMDATA INPUT/OUTPUTJune 1988 1/10155

ST27128APBLOCK DIAGRAMYee 0-----­GNO 0-------=-+Yppo----+OUTPUT ENABLECHIP ENABLE ANDPROG. LOGICVDECODERAO-A13ADDRESSINPUTSXDECODERABSOLUTE MAXIMUM RATINGSSymbolVIVppTambT stgParameterAll Input or Output voltages with respect to groundSupply voltage with respect to groundAmbient temperature under biasStorage temperature rangeVoltage on pin 24 with respect to groundValuesUnit+ 6.25 to - 0.6 V+14to -0,6V-10 to +80 ·C- 65 to +125 ·C+ 13.5 to -0.6 VStresses above those lisled under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.OPERATING::------::MODES-MODE-PGMVpp Vee OUTPUTSCE OE A9(11·13,(20) (22) (24) (2!) (1) (28) 1!H9)READ VIL VIL X VIH Vee Vee DOUTOUTPUT DISABLE VIL VIH X VIH Vee Vee HIGH ZSTANDBY VIH X X X ,Vee Vee HIGH ZFAST PROGRAMMING VIL VIH X VIL Vpp Vee DINVERIFY VIL VIL X VIH Vpp Vee DOUTPROGRAM INHIBIT VIH X X X Vpp Vee HIGH ZELECTRONIC SIGNATURE ViL VIL VH VIH Vee Vee CODESNOTE: X can be V 1H 'or VII:'2110156

ST27128APREAD OPERATIONDC AND AC CONDITIONSSelection Code -15X/-20X - 201-25/- 30Operating Temperature Range o to 70°C o to 70°CVee Power Supply (1,2) 5V ±5% 5V ±10%Vpp Voltage (2) Vpp = Vee Vpp = VeeDC AND OPERATING CHARACTERISTICSValuesSymbol Parameter Test ConditionsMin. Typ. (3) Max.UnitIII Input Load Current VIN=5.5V 10 ~AILO Output Leakage Current VOUT=5.5V 10 ~AIpPl(2) Vpp Current Read Standby Vpp=5.5V 5 mAleel(2) Vee Current Standby CE=VIH 40 mAlee2(2) Vee Current Active CE=OE=VIL 85 mAVpp = VeeVIL Input Low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 Vee+ 1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VVOH Output High Voltage IOH= -400 ~A 2.4 VVpp(2) Vpp Read Voltage Vee =5V ±0.25V 3.8 Vee VAC CHARACTERISTICSVcc± 5%27128A·15X 27128A·20XSymbol Parameter Vcc±10% 27128A·20 27128A·25 27128A·30 UnitTest Conditions Min Max Min Max Min Max Min MaxtAee Address to Output Delay CE=OE=VIL 150 200 250 300 nsteE CE to Output Delay OE=VIL 150 200 250 300 nstOE OE to Output Delay CE=VIL 65 75 100 120 nstOF(4) OE High to Output Float CE=VIL 55 0 55 0 60 0 105 nstOH Output..!::!?ld from Address CE=OE= VIL 0 0 0 0 nsCE or OE WhicheverOccurred First:;APACITANCE(5) (Tamb=25°C, f=1 MHz)Symbol Parameter Test Conditions Min. Typ. Max. UnitCIN' Input Capacitance VIN=OV 4 6 pFCOUT Output Capacitance VOUT=OV 8 12 pFlotes:1. Vce must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.2. Vpp may be connected directly to Vce except during programming.The supply current would then be the sum of Icc and IpP1 '3. Typical values are for T amb = 25°C and nominal supply voltages.4. This parameter is only sampled and not 100% tested. Output Float is defined as the point where data is no longer driven.(See timing diagram).5. This parameter is only sampled and is not 100% tested.3/10157

ST27128APREAD OPERATION (Continued)AC TEST CONDITIONSOutput Load: 1 OOpF + HTL GateInput Rise and Fall Times: :s; 20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT1.3V2.4 =>(20 . > 10>!&C, • tOE after the falling edge CE without impact on tAce.4. tOF is specified from OE or CE whichever occurs first.4/10158/iii SGS·THOMSON~ I. iIilO©rnI@~~~©'iFrnI@IK!O©@

ST27128APDEVICE OPERATIONThe seven modes 0f operations of the ST27128APare listed in the Operating Modes. A single 5V powersupply is required in the read mode. All inputsare TIL levels except for Vpp and 12V on A9 forElectronic Signature.READ MODEThe ST27128AP has two control function, both ofwhich must be logically satisfied in order to obtaindata at the outputs. Chip Enable (~) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection.Assuming that addresses are stable, address accesstime (tACe) is equal to delay from CE to output(tc8. Data is available at the ~uts after thefalling edge of DE, assuming that CE has been lowand addresses have been stable for at leasttAce-teE'STANDBY MODEThe ST27128AP has a standby mode which reducesthe maximum active power current from 85 mAte 40 mAo The ST27128AP is placed in the standbymode by applying a TIL high signal to the crinput. When in the standby mode, the outputs arein a high impedance state, independent of the DEinput.OUTPUT OR-TIEINGBecause OTPs are usually used in larger memoryarrays, the product features a 2 line control functionwhich accommodates the use of multiple memoryconnection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE should-be made a common connection to all devices inthe array and connected to the READ line from thesystem control bus.This assures that all deselected memory devicesare in their low power standby mode and that theoutput pins are only active when data is desiredfrom a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and tran-sient current peaks that are produced by the faIlingand rising edges of~. The magnitude of thistransient current peaks is dependent on the outputcapacitive and inductive loading of the device.The associated transient voltage peaks can be suppressedby complying with the two line output controland by properly selected decoupling capacitors.It is recommended that a 1 ,.F ceramic capacitorbe used on every device between Vcc and GND.This should be a high frequency capacitor of lowinherent inductance and should be placed as closeto the device as possible. In addition, a 4.7 ,.Fbulk electrolytic capacitors should be used betweenVee and GND for every eight devices. The bulk capacitorshould be located near where the powersupply is connected to the array. The purpose ofthe bulk capacitor is to overcome the voltage dropcaused by the inductive effects of PCB traces.PROGRAMMINGCaution: exceeding 13Von pin 1 (Vpp) will damagethe ST27128AP.When delivered, all bits of the ST27128AP are inthe "1" state. Data is introduced by selectively programming"Os" into the desired bit locations. AI.though only "Os" will be programmed, both "1s"and "Os" can be present in the data word.The ST27128AP is in the P-rQgramming mode whenVpp input is at 12.5V and CE and PGM are at TILlow. The data to be programmed is applied 8 bitsin parallel to the data output pins. The levels requiredfor the address and data inputs are TIL.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsST27128AP EPROMs using an efficient and reliablemethod suited to the production programmingenvironment. Programming reliability is also ensuredas the incremental program margin of each bytesis continually monitored to determine when ithas been successfully programmed. A flowchart ofthe ST27128AP Fast Programming Algorithm isshown on the last page. The Fast Programming Algorithmutilizes two different pulse types: initial andoverprogram.The duration of the initial PGM pulse (s) is onemillisecond, which will then be followed by a longeroverprogram pulse of length 3Xmsec. (X is an iterationcounter and is equal to the number of the initialone millisecond pulses applied to a particularST27128AP location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte are providedfor before the over program pulse is applied.511.0159

DEVICE OPERATION (Continued)The entire sequence of program pulses and byteverifications is performed at Vee = 6V andVpp = 12.5V. When the Fast Programming cyclehas been ccimpleted,all bytes should be comparedto the original data,withVec=Vpp=5V.PROGRAM INHIBIT •Programming of multiple ST27128APs in parallelwith different data is also easilyaecomj:llished. Exceptfor CE,all like inputs (including OE) of theparallel M27128BA may be common. A TTL lowpulse applied to a ST27128AP's CE input, withVpp at 12.5V, will program that ST27128AP. Ahigh level CE input inhibits the other ST27128APfrom being programmed.PROGRAM VERIFYA verify should be performed on the programmedbits to determine that they were corre~programmed. The verify is accomplished with OEat'V1L, CE at V1L, PGM at V1H and Vpp at 12.5V.ELECTRONIC SIGNATUREThe Electronic Signature mode allows the readingout of a binary code from an EPROM that will identifY'itsmanufacturer and type. This mode'isintendedfor use by programming equipment for thepurpose of automatically matching the device tobe programmed with its corresponding programmingalgorithm. This mode is functional in the 25°C;l: 5°C ambient temperature range that is requiredwhen programming the ST27128AP. To activatethis mode, the programming equipment must force11,.5V to,12.5V (;m address line A9 (pin 24) of theST27128AP. Two identifier bytes may than be sequencedfrom the device outputs by toggling addressline AO (pin 10) from VII .. to V1H. All otheraddress lines must be held at V1L during ElectronicSignature mode. Byte 0 (AO = V1U represents themanufacturer code and byte 1 (AO = V1H) thedevice identifier code. For the SGS-THOMSONST27128AP, these two identifier bytes are givenbelow. All identifiers for manufacturer and devicecodes will possess odd parity, with the MSB (07)defined as the parity bit.ELECTRONIC SIGNATURE MODE~sIDENTIFIER ,AO 07 06(10) (19) (18)MANUFACTURER CODE VIL 0 0DEVICE CODE Viii 1 005 04 03 02 01 00 Hex(17) (16) (15) (13) (12) (11) Data1 0 0 0 0 0 200 0 1 0 0 1 896/10160

ST27128APPROGRAMMING OPERATION (Tamb=25°C ±5°C, Vee(I)=6V ±O.25V, Vpp(l) = 12.5V ±O.3V)DC AND OPERATING CHARACTERISTICSymbol ParameterTest C::ondltlonsValues(See note 1) Min. Typ. Max.UnitILl Input Current (All Inputs) VIN = VIL or VIH 10 pAVIL Input Low Level (All Inputs) -0.1 0.8 VVIH Input High Level 2.0 Vee+ 1 VVOL Output Low Voltage During Verify IOL=2.1 mA 0.45 VVOH Output High Voltage During Verify 10Hz -400 pA 2.4 Vlee2 Vee Supply Current (Program & Verify) 100 mAIpP2 Vpp Supply Current (Program) CE=VIL 50 mAVIO A9 Electronic Signature Voltage 11.5 12.5 VAC CHARACTERISTICSSymbolParameterTest ConditionsValues(See note 1) Min. Typ. Max. UnittAS Address Setup Time 2 ~stoes OE Setup Time 2 ~stos Data Setup Time 2 ~stAH Address Hold Time 0 ~stOH Data Hold Time 2 ~stOFp(4) Output En'able Output Float Delay 0 130 nstvps Vpp Setup Time 2tves Vee Setup Time 2 ~stees CE Setup Time 2 ~stpw PGM Initial Program Pulse Width (see Note 3) 0.95 1.0 1.05 mstopw PGM Overprogram Pulse Width (see Note 2) 2.85 78.75 mstoe Data Valid from OE 150 nsNotes:1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.2. The length of the overprogram pulse may vary from 2.85msec to 78.75msec as a function of the iteration counter value X.3. Initial Program Pulse width tolerance is lmsec ±5%.4. This parametar is only sampled and not 100% tested.Output Float Is defined as the point where data is no longer driven (see timing diagram),. '~s7110161

ST27128APPROGRAMMING WAVEFORMSVIHADD,RESSES;~VILVIHDATAVILVpptASlOS12.5 V5V ~ tvpsDATAPROGRAMADDRESS STABLEIN STABLE'{I+-----~IH,LVERIFYC.1 tAHDATA OUT ~ALID ~tDFPVee6V5V~ tvesCEVIHVIL\teEsVIHPGMDEVILVIHVIL'--"~topw\ ~~ ~5-754 312Notes:1. The input timing reference level is O.BV for a VIL and 2V for a VIH.2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.3. When programming the ST2712BAP a O.1~F capacitor is required across Vpp and GROUND to suppress spurious voltage transientswhich can damage the device.8/10162

ST27128APFAST PROGRAMMING FLOWCHART5-6'0819/10163

ST27128APORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageST27128A·15XCPST27128A·20XCPST27128A·20CPST27128A·25CPST27128A·30CP150 ns200 ns200 ns250 ns300 ns5V± 5%5V± 5%5V±10%5V±10%5V±10%to +70°Cto +70oCto +70oCto +70°Co to +70°CDlp·28Dlp·28DIP·28DIP·28Dlp·28PACKAGE MECHANICAL DATA2a·PIN PLASTIC DIP"FCT,E~mmInchesDim.Min Typ IIax Min Typ IIaxA81 0,63 0,025l- 8 0,45 0,018b 1 0.23 0,31 0,009 0,012b2 1.27 0,050CD 37,34 1.470E 15,20 16,68 0,588 0,657e 2,54 0,100e3 33.02 1.300e4F 14,10 0,555I 4,45 0,175l 3,30 0,130KlK210/10164

ST27256P256K (32K x 8) NMOS ONE TIME PROGRAMMABLE ROM• FAST ACCESS TIME: 170ns• 0 to + 70°C STANDARD TEMP. RANGE• SINGLE + 5V POWER SUPPLY• ±10% Vcc TOLERANCE AVAILABLE• LOW STANDBY CURRENT (40mA MAX)• TTL COMPATIBLE DURING READ ANDPROGRAM• FAST PROGRAMMING ALGORITHM• ELECTRONIC SIGNATURE"f~':'-:-":::~.'.::.:':':......'...'.'.. '..:: ..'.:'.'.::........•.....•.......... ::...':..'.. ,..:, .. :::..•.•. !: .. ,.•.::...:.•...•.•. :_.::.:~.:.:: .•. .•. :.•.•..",.:..·..•.•.)i\;;!!;~l!r;·y·2B1BDIP-28(Plastic Package)(Ordering Information at the end of the datasheet)DESCRIPTIONThe ST27256P is a 262, 144-bit one time programmableread only memory (OTP ROM). It is organizedas 32.768 words by 8 bits and manufacturedusing SGS-THOMSON' NMOS-E3 process. TheST27256P with its single + 5V power supply andwith an access time of 200ns, is ideal for use withhigh performance + 5V microprocessor such as Z8,Z80 and Z8000. The ST27256P has an importantfeature which is to separate the output control, Q!wtutEnable (OE) from the Chip Enable control (CE).The OE control eliminates bus contention in mUltiplebus microprocessor systems. The ST27256Palso features a standby mode which reduces thepower disSipation without increasing access time.The active current is 100mA while the maximumstandby current is only 40 mA, a 60% saving. Thestandby mode is achieved by applying a TTL-highsignal to the CE input. The ST27256P enables implementationof new, advanced systems with firmwareintensive architectures. The combination ofthe ST27256P's high density, and new advancedmicroprocessors having megabit addressing capabilityprovides designers with opportunities to engineeruser-friendly, high reliability, high-performancesystems. The ST27256P large storage capabilityenables it to function as a high density softwarecarrier. Entire operating systems, diagnostics,high-level language programs and specialized applicationsoftware can reside in a ST27256P directlyon a system's memory bus. This permits immediatemicroprocessor access and execution of softwareand eliminates the need for time consuming diskaccesses and downloads. The ST27256P has an"Electronic Signature" that allows programmersto automatically identify device type and pinout.PIN NAMESAO-A14CEOEPIN CONNECTIONS----~Vpp 1 2Bb VceA12 27 A14A7 26 A13A6 25 A8AS 24 A"A4 I 6 23 A11A3 22 OEA2 2' Al0Al 20 TIAO '0 19 0100 11 IS 0601"17 0502 13 '6 04GND '5 03"s - 7516ADDRESS INPUTCHIP ENABLE INPUTOUTPUT ENABLE INPUT00-07 DATA INPUT/OUTPUTJune 19881/10165

ST27256PBLOCK DIAGRAMVee 0-----.GNOO---DATA OUTPUTS00-07A(}·A1tADDRESS IINPUTS,DECODER262.1.4.49ITCELL MATRIXS-7s71ABSOLUTE MAXIMUM RATINGSSymbolVIVppTambTstgParameterAll Input or Output voltages with respect to groundSupply voltage with respect to groundAmbient temperature under biasStorage temperature range. Value+ 6.25 to - 0.6+14 to -0,6-10to +80.- 65 to +125Voltage on pin 24 with respect to ground+ 13.5 to -0.6VStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated In the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.UnitVV·C·COPERATING MODES==-------=MODECE OEVpp Vee OUTPUTSA9 AO (11.13, .(20) (22) (24) (10) (1) (28) 15-19)READ VIL VIL X X Vee Vee DQUTOUTPUT DISABLE VIL VIH X X Vee Vee HIGHZSTANDBY VIH X X X Vee Vee HIGH ZPROGRAM VIL VIH X X Vpp Vee DINVERIFY VIH VIL X X Vpp Vee DQUTOPTIONAL VERIFY VIL VIL X X Vpp Vee DQUTPROGRAM INHIBIT VIH VIH X X Vpp Vee HIGH ZELECTRONIC SIGNATURE VIL VIL VH VIL Vee . Vee ... MAN.CODESVIL VIL VH VIH Vee Vee DEV.CODENOTE: X can be VIH or VIL2110166

ST27256PREAD OPERATIONDC AND AC CONDITIONSSelection Code -17x/-20X - 20/- 25/- 30Operating Temperature Range o to 70 D C o to 70 D CVee Power Supply (1,2) 5V ±5% 5V ±10%Vpp Voltage (2) Vpp = Vee Vpp = VeeDC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsValuesMin. Typ. (3) Max.III Input Load Current VIN=5.5V 10 I"AILO Output Leakage Current VOUT=5.5V 10 I"AIpp1(2) Vpp Current Read Standby Vpp=5.5V 5 mAIce 1(2) Vee Current Standby CE=VIH 20 40 mAlee2(2) Vee Current Active CE=OE=VIL 45 100 mAVpp=VeeVIL Input Low Voltage -0.1 +0.8 VVIH Input High Voltage 2.0 Vee+ 1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VVOH Output High Voltage IOH= -400 I"A 2.4 VVPP(2) Vpp Read Voltage Vee=5V±0.25V 3.8 Vee VUnitAC CHARACTERISTICSVcc± 5% 27256·17X 27256·20XSymbol Parameter Vcc±10% 27256·20 27256·25 27256·30 UnitTest Conditions Min Max Min Max Min Max Min MaxtAee Address to Output Delay CE=OE=VIL 170 200 250 300 nsteE CE to Output Delay OE=VIL 170 200 250 300 nstOE OE to Output Delay CE=VIL 70 75 100 120 nstOF(4) OE High to Output Float CE=VIL 35 0 55 0 60 0 105 nstOH Output...!::!gld from Address CE=OE= VIL 0 0 0 0 nsCE or OE WhicheverOccurred FirstCAPACITANCE(S) (Tamb = 25°C, f = 1 MHz)Symbol Parameter Test Conditions Min. Typ. Max. UnitCIN Input Capacitance VIN=OV 4 6 pFCOUT Output Capacitance VOUT=OV 8 12 pFNotes:1. vcc must be applied simuttaneously or before Vpp and removed simultaneously or after Vpp.2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of Icc and IpP1 '3. Typical values are for T amb =2soe and nominal supply voltages.4. This parameter is only sampled and not 100% tested. Output Float is defined as the point where data is no longer driven·seetiming diagram.5. This parameter is only sampled and not 100% tested.3/10167

ST27256PREAD OPERATION (Continued)AC TEST CONDITIONSOutput Load: 100pF + HTL GateInput Rise and Fall Times: s;20nsInput Pulse Levels: 0.45 to 2.4VTiming Measurement Reference Levels: Inputs 0.8 and 2VOutputs 0.8 and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT2.4 =>

ST27256PDEVICE OPERATIONThe eight modes of operations of the ST27256P arelisted in the Operating Modes. A single 5V powersupply is required in the read mode. All inputs areTTL levels except for Vpp and 12V on A9 for ElectronicSignature.READ MODEThe ST27256P has two control function, both ofwhich must be logically satisfied in order to obtaindata at the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection. OutputEnable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, address access time (tAccl is equalto delay from CE to output (tCE)' Data is availableat the outputs after the falling edge of OE, assumingthat CE has been low and addresses have beenstable for at least tACC-tOE'STANDBY MODEThe ST27256P has a standby mode which reducesthe maximum active power current from 100 mA to40 mA. The ST27256P is placed in the standby modeby applying a TTL high signal to the CE input. Whenin the standby mode, the outputs are in a high impedancestate, independent of the OE input.TWO LINE OUTPUT CONTROLBecause OTPs are usually used in larger memoryarrays, the product features a 2 line control functionwhich accommodates the use of multiplememory connection. The two line control functionallows:a) the lowest possible memory power dissipationb) complete assurance that output bus contentionwill not occur.For the most efficient use of these two control lines,CE should be decoded and used as the primarydevice selecting function, while OE should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus. This assures that all deselectedmemory devices are in their low power standbymode and that the output pins are only active whendata is desired from a particular memory device.SYSTEM CONSIDERATIONSThe power switching characteristics of NMOS-E3EPROMs require careful decoupling of the devices.The supply current, Icc, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and transientcurrent peaks that are produced by the falling andrising edges of CE. The magnitude of this transientcurrent peaks is dependent on the output capacitiveand inductive loading of the device. The associatedtransient voltage peaks can be suppressedby complying with the two line output control andby properly selected decoupling capacitors. It isrecommended that a 1 pF ceramic capaCitor beused on every device between Vcc and GND. Thisshould be a high frequency capacitor of low inherentinductance and should be placed as close tothe device as possible. In addition, a 4.7 I'F bulkelectrolytic capacitors should be used betweenVcc and GND for every eight devices. The bulkcapacitor should be located near where the powersupply is connected to the array. The purpose ofthe bulk capacitor is to overcome the voltage dropcaused by the inductive effects of PCB traces.PROGRAMMINGCaution: exceeding 13Von pin 1 (Vpp) will damagethe ST27256P.When delivered, all bits of the ST27256P are in the"1" state. Data is introduced by selectively programming"Os" into the desired bit locations. Althoughonly "Os" will be programmed, both "1s" and "Os"can be present in the data word. The ST27256P isin the pro9@.mming mode when Vpp input is at12.5V and CE and is at TTL low. The data to beprogrammed is applied 8 bits in parallel to the. dataoutput pins. The levels required for the address anddata inputs are TTL.FAST PROGRAMMING ALGORITHMFast Programming Algorithm rapidly programsST27256P EPROMs using an efficient and reliablemethod suited to the production programming environment.Programming reliability is also ensuredas the incremental program margin of each bytesis continually monitored to determine when it hasbeen successfully programmed. A flowchart of theST27256P Fast Programming Algorithm is shownon the last page. The Fast Programming Algorithmutilizes two different pulse types: initial and overprogram.The duration of the initial CE pulse (s) isone millisecond, which will then be followed by alonger overprogram pulse of length 3Xmsec. (X isan iteration counter and is equal to the number ofthe initial one millisecond pulses applied to a particularST27256P location), before a correct verifyoccurs. Up to 25 one-millisecond pulses per byteare provided for before the over program pulse isapplied. The entire sequence of program pulsesand byte verifications is performed at Vcc =6V andVpp=12.5V. When the Fast Programming cyclehas been completed, all bytes should be comparedto the original data with Vcc =Vpp =5V.5/10169

ST27256PDEVICE OPERATION (Continued)PROGRAM INHIBITProgramming of multiple ST27256Ps in parallel withdifferent data is also easily acco..mplished. Exceptfor CE, all like inputs (including OE) of the parallelST27256P may be common. A TTL low pulse appliedto a ST27256P's CE input, with Vpp at 12.5V,will program that ST27256P. A high level CE inputinhibits the other ST27256Ps from being programmed.PROGRAM VERIFYA verify should be performed on the programmedbits to determine that they were correctlypro9.@!!1med. The verify is accomplished with OE atV1L, CE at V1H and Vpp at 12.5V.OPTIONAL VERihThe optional verify may be performed instead....Q!the verify mode. It is performed with OE at V1L, CEat V1L (as opposed to the standard verify which hasCE at V1H), and Vpp at 12.5V. The outputs willthree-state according to the signal presented to OE.Therefore, all devices with Vpp = 12.5V andOE = 'liLwili present data on the bus independentof the CE state. When parallel programming severaldevices which share the common bus, Vpp shouldbe lowered to Vee (= 6V) and the normal readmode used to execute a program verify.ELECTRONIC SIGNATUREThe Electronic Signature mode allows the readingout of a binary code from an EPROM that will identifyits manufacturer and type. This mode is intendedfor use by programming equipment for the purposeof automatically matching the device to beprogrammed with its corresponding programmingalgorithm. This mode is functional in. the 25°C±5°C ambient temperature range that is requiredwhen programming the ST27256P. To activate thismode, the programming equipment must force11.5V to 12.5V on address line A9' (pin 24) of theST27256P.Two identifier bytes may then be sequenced fromthe device outputs by toggling address line AD (pin10) from V1L to V1H. All other address lines must beheld at V1L during Electronic Signature mode. Byteo (AO = V1J represents the manufacturer code andbyte 1 (AO = V1H) the device identifier code. For theSGS-THOMSON ST27256P, these two identifierbytes are given below.All identifiers for manufacturer and device codeswill possess odd parity, with the MSB (07) definedas the parity bit.ELECTRONIC SIGNATURE MODE~IDENTIFIERAO 07 06(10) (19) (18)MANUFACTURER CODE VIL 0 0DEVICE CODE VIH 0 005 04 03 02 01 00 Hex(17) (16) (15) (13) (12) (11) Data1 0 0 0 0 0 200 0 0 1 0 0 046/10170

ST27256PPROGRAMMING OPERATION (Tamb = 25°C ±5°C, VeC

ST27256PPROGRAMMING. WAVEFORMSVIHADDRESSE SVIL~IHDATA.YIL12.5 VVppSY6VYeeSYVIHCEVILVIHOEVIL'J.'AS'OSItvps/lyesPROGRAMDATA IN STABLE\IADDRESS STABLE---~IHIGH Z~tOE~~ -=-..'OPW"\ ~PROGRAM VERIFY"..--(+DATA OUT VALID\,-' AH 'o...-...{/- ---' t DFPr=I}-5-9823/1Notes:1. The input timing reference level is O.SV for a VIL and 2V for a VIH.2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.3. When programming the ST27256P a O.I~F capacHor is required across VPP and GROUND to suppress spurious vonage transients whichcan damage the device.8/10172

ST27256PFAST PROGRAMMING FLOWCHARTFAILDEVICEFA ILED5-6'0819/10173

ST27256PORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageST27256-17XCPST27256-20XCPST27256-20CPST27256-25CPST27256-30CP170 ns200 ns200 ns250 ns300 ns5V± 5%5V± 5%5V±10%5V±10%5V ± 100Alto + 70·Cto +70·Co to + 70·Cto + 70·Co to + 70·CDIP-28DIP-28DIP-28DIP-28DIP-28PACKAGE MECHANICAL DATA28-PIN PLASTIC DIPf--"Fc1"EI--"-- l-mm Inell ..Dim.Min Typ Max Min Typ MaxAa 1 0.63 0.025B 0.45 0,018b 1 0.23 0.31 0.009 0.012b 2 127 0.050C0 37.34 1.470E 15.20 16.68 0.598 0.6572.54 0.100•e3 33.02 1.300e4F 14.10 0.555I 4.45 0.175l 3.30 0.130K1K210/10174

EPROM DEVICESCMOS OTP ROM175

~ SGS-1HOMSON..., L ~D©OO@rn[1,rn©li'OO@~D©~TS27C64AFNTS27C64AP64K (8Kx8) CMOS ONE TIME PROGRAMMABLE ROM• COMPATIBLE TO TS27C64A EPROM(ELECTRICAL PARAMETERS,PROGRAMMING)• PROGRAMMING VOLTAGE 12.5V• HIGH SPEED PROGRAMMING• 28-PIN JEDEC APPROVED PIN-OUT• 32-PIN JEDEC APPROVED PIN-OUT (PLCC)• IDEAL FOR AUTOMATIC INSERTIONPDIP-28(Plastic Package)FNPLCC32(Plastic Chip Carrier)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe TS27C64AP and TS27C64AFN are high speed65,536-bit One Time Programmable (OTP) CMOSROM ideally suited for applications where fast turnaroundis an important requirement.The TS27C64AP is packaged in a 28-pin dual-inlineplastic package, the TS27C64AFN in a 32-pinPLCC plastic package and therefore can not be rewritten.Programming is performed according tostandard SGS-THOMSON 64K EPROM procedure.1323130PIN NAMESAO-A12ADDRESSCECHIP ENABLEOEOUTPUT ENABLE00-0 7 OUTPUTSPGMPROGRAMNCNON CONNECTEDDUDO NOT USETS27C64AFN14 IS 16 1716 19 20==­.- NO:::> M

TS27C64AFN-TS27C64APBLOCK DIAGRAMVeco-­GNOO--­VppO---DATA OUTPUT00- 07OUTPUT ENABLECHIP ENABLE ANDPROG. LOGICOUTPUTBUFFERSDECODERyGAT INGAD-AI2ADDRESS -INPUTSxDECODER65.536 BITCELL MATRIX5-6361ABSOLUTE MAXIMUM RATINGS(1)SymbolTambTstgVpp(2)VIN(2)PDParameterOperating temperature rangeTS27C64A-CTS27C64A-VTS27C64A-TStorage temperature rangeSupply voltageInput voltagesExcept Vpp,Max power dissipationLead temperature(Soldering: 10 seconds)A9A9ValueTL to THo to+ 70-40 to+85-40 to+ 105765 to+125-0.6 to+ 14-0.6 to+ 13.5- 0.6 to + 6.251.5+300Notes: 1. "Maximum ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating temperaturerange" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical characteristics"provides conditions for actual device operation.2. With respect to GNDUnit°c°cVVW°cOPERATING MODESMODE ~SCE OE A9 PGM Vpp Vee OUTPUTSREAD VIL VIL X VIH Vee Vee DOUTOUTPUT DISABLE VIL VIH X VIH Vee Vee Hi-ZSTANDBY VIH X X X Vee Vee Hi-ZHIGH SPEED PROGRAMMING VIL VIH X VIL Vpp Vee DINPROGRAM VERIFY VIL VIL X VIH Vpp Vee DOUTPROGRAM INHIBIT VIH X X X Vpp Vee Hi-ZELECTRONIC SIGNATURE(3) VIL VIL VH(2) VIH VCC Vee CODENotes: 1. X can be either V1L or V1H - 2. VH=12.0V±0.5V3. All address lines at V1L except A9 and AD that is toggled from V1L (manufacturer code: 98) to V1H (type code: 08).2/10178

TS27C64AFN-TS27C64AP:AD OPERATION:; CHARACTERISTICS (T amb = T L to T H, Vcc = 5V ± 10%, GND = OV; Unless otherwise specified)Values;ymbol Parameter Test Conditions UnitMin. Typ.(1) Max.III Input Load Current VIN = Vcc or GND 10 pAILO Output Leakage Current ~UT=VCC or GND,CE=VIH 10 I'AVpp Vpp Read Voltage Vcc- 0.7 Vcc VVIL Input Low Voltage -0.1 0.8 VVIH Input High Voltage 2.0 Vcc+ 1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VIOL=O I'A 0.1VOH Output High Voltage IOH= -400 I'A 2.4 VIOH=O I'A Vcc- 0.1ICC2 Vcc Supply Active Current CE = OE = VIL, Inputs = VIH or 10 30 mATTL LevelsVll, f=5 MHz, 1/0=0 mAICCSBI V CC Supply Standby Current CE=VIH 0.5 1 mAICCSB2 V cc Supply Standby Current CE=Vcc 10 100 pAIppi V pp Read Current Vpp=Vcc=5.5V 100 p.ANote: I. Typical conditions are for operation at: Tamb= + 25°C, VCC=5V, Vpp=VCC, and VSS=OVAC CHARACTERISTICS(1)(T amb = TL to T H)27C64A 27C64A 27C64A 27C64ASymbol Parameter Test Conditions ·15 ·20 ·25 ·30 UnitMin Max Min Max Min Max Min MaxIACC Address to Output Delay CE=OE=VIL 150 200 250 300 nstCE CE to Output Delay OE=VIL 150 200 250 300 nstOE Output Enable to CE=VIL 75 80 100 120 nsOutput DelaytDF(2,4) OE or CE High to CE=Vll 0 50 0 50 0 60 0 105 nstOH Output Hold from CE=OE=Vll 0 0 0 0 nsaddresses, CE or OEwhichever occured firstCAPACITANCE T amb = + 25°C, f = 1 MHz (Note 3)Symbol Parameter Test Conditions Min. Typ. Max. UnitCin Input Capacitance VIN=OV 4 6 pFCout Output Capacitance VOUT=OV 8 12 pFNotes: 1. VCC must be applied at the same time or before Vpp and removed after or at the same time as Vpp.Vpp may be connectedto VCC except during program.2. The tDF compare level is determined as follows:High to THREE·STATE, the measured VOH(DC) -o.tVlow to THREE-STATE the measured VOl(DC) +O.tV.3. Capacitance is guaran!aad BjI...jleriodic testing. T a"lb = + 25°C, f = 1 MHz.4. T DF, is specified from OE or CE whichever occurs irS!. This parameter is only sampled and not 100% tested.3/10179

TS27C64AFN-TS27C64APAC TEST CONDITIONSOutput Load: 1 TTL gate and CL = 100 pFInput Rise and Fall Times,;;20 nsInput pulse levels: 0.4SV to 2.4VTiming Measurement Reference LevelInputs, Outputs0.8V and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT2.4 => 1O)CTEST POINTS < .0.45 0.8 o.sI ~v6~~TEST1N9143.3KnII-_~I-_-O OUTI=:c= CL"DOpF$-&802CL INCLUDES JIG CAPACITANCEAC WAVEFORMSV,HADDRESS ES ADDRESS VALID)V1lITV,HV,LI'CEOEV,HV,LI'OE (3)'ACC (3)HIGH Z 11111.\\\\\\ v HIGH Z5-6809Notes:1. Typical values are for T amb = 25°C and nominal supply voltage2. This parameter is only sampled and not 100% tested.3. OE may be delayed !!ILto tACe - tOE after the falling edge CE without impact on tACC4. tDFis specified form OE or CE whichever occurs first.4/10180

TS27C64AFN-TS27C64APDEVICE OPERATIONThe seven modes of operation of the TS27C64Aare listed in the Operating Modes table. A singleSV power supply is required in the read mode. Allinputs are TTL levels except for Vpp.READ MODEThe TS27C64A has two control functions, both ofwich must be logically active in order to obtain dataat the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, address access time (tACC) is equal tothe delay from CE to Output (tCE). Data is availableat the oUJrults after a delay of tOE from the fallingedge of OE, assuming that CE has been low andaddresses have been stable for at least tAcc-tOE.STANDBY MODEThe TS27C64A has a standby mode which reducesthe maximum power dissipation to S.S mW. TheTS27C64A is placed in the standby mode by applyinga TTL high signal to the CE input. When instandby mode, the outputs ar~a high impedancestate, independent of the OE input.OUTPUT OR-TYINGBecause OTPs are usually used in larger memoryarrays, we have provided two control lines whichaccomodate this multiple memory connection. Thetwo control lines allow for:a) the lowest possible memory power dissipation,andb) complete assurance that output bus contentionwill not occur.To use these control lines most efficiently, CEshould be decoded and used as the primary deviceselecting function, while OE should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus. This assures that all deselected memorydevices are in their low power standby modesand that the output pins are active only whendata is desired from a particular memory device.PROGRAMMINGCaution: Exceeding 14Von Vpp pin will damagethe TS27C64A.Initially, all bits of the TS27C64A are in the" 1" state.Data is introduced by selectively programming"Os" into the desired bit locations. Although only"Os" will be programmed, both "1s" and "Os" canbe presented in the data word.The TS27C64A is in the programming mode whenthe Vpp input is at 12.S V and CE and PGM areboth at TTL Low. It is required that a 0.1 /,F capacitorbe placed across Vpp, VCC and ground tosuppress spurious voltage transients which may damagethe device. The data to be programmed isapplied 8 bits in parallel to the data output pins.The levels required for the address and data inputsare TTL.Programming of multiple TS27C64As in parallelwith the same data can be easily accomplished dueto the simplicity of the programming requirements.Like inputs of the parallel TS27C64As may be connectedtogether when they are programmed withthe same data. A low level TTL pulse applied tothe PGM input programs the paralleledTS27C64As.HIGH SPEED PROGRAMMINGThe high speed programming algorithm describedin the flow chart rapidly programs TS27C64A usingan efficient and reliable method particularly suitedto the production programming environment. Typicalprogramming times for individual devices areon the order of 1 minute.PROGRAM INHIBITProgramming of multiple TS27C64As in parallelwith different data is also easily accomplished..Qyusing the program inhibit mode. A high level on CEor PGM inputs inhibits the other TS27C64As fromfrom being programmed. Except for CE, all likeinputs (including OE) of the parallel TS27C64Asmay be comm

TS27C64FN-TS27C64APPROGRAMMINGOPERATIONS(1)(T amb = 25 ± 5°C, VCC = 6.0V ± 0.25V, Vpp = 12.5V ± 0.3V)DC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsMin.ValuesTyp.Max.UnitII Input Current (all inputs) VI = VIL or VIHVIL Input Low Level (all inputs) -0.1VIH Input High Level 2.0VOL Output low voltage during verify IOL=2.1 mAVOH Output high voltage during verify IOH= -400 pA 2.4lee3Vee Supply current(Program & Verify)IpP2 Vpp supply current (Program) CE=VIL=PGM100.8Vee+ 10.453030pAVVVVmAmAAC CHARACTERISTICSSymbol Parameter Test ConditionstAS Address Set-up Time 2tOES OE Set-up Time 2tos Data Set-up Time 2tAH Address Hold Time 0tOH Data Hold Time 2tOFP Output enable to output float delay 0tvps Vpp set-up time 2tves Vee set-up time 2Min.Valuestpw PGM initial program pulse width 0.95 1.0topW

TS27C64AFN-TS27C64APHIGH SPEED PROGRAMMING WAVEFORMSV1HADDRESSES;~V1LV1HDATAV1LVPP12.5 V5V--.ItAStostvpsDATAPROGRAMADDRESS STABLEIN STABLEr-----IHILVERIFYtAHDATA OUT ~ALID >~ tOFP!cVee6.V5V ~tvesCEV1HV1L"-teEsPGMOEV1HV1L\F---->~V1H~ ~tOPw~ \V1L 510312'-71. The input timing reference level is 0.8V for VI Land 2.0V for VIH.2. tOE and tOFP are characteristics of the device but must be be accommodated by the programmer.3. When programming the TS27C64A, a 0.1 ~F capaCitor is required across Vpp and ground to suppress spurious voltage transiens whichcan damage the device.7/10183

TS27C64AFN-TS27C64APHIGH SPEED PROGRAMMING FLOW CHARTFAILDEVICEFAILED8/10184

TS27C64AFN-TS27C64APORDERING INFORMATION (TS27C64AP)Part NumberAccess TimeSupply VoltageTemp. RangePackageTS27C64A·15CPTS27C64A·2OCPTS27C64A·25CPTS27C64A-30CPTS27C64A·15VPTS27C64A·20VPTS27C64A·25VPTS27C64A-30VPTS27C64A·15TPTS27C64A·20TPTS27C64A·25TPTS27C64A-30TP150 ns200 ns250 ns300 ns150 ns200 ns250 ns300 ns150 ns200 ns250 ns300 ns5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%to + 70°C DIP·28to + 70°C DIP·28to + 70°C Dlp·28o to + 70°C Dlp·28-40 to + 85°C Dlp·28-40 to + 85°C Dlp·28-40 to + 85°C DIP·28-40 to + 85°C DIP·28-40 to +105°C DIP·28-40 to +105°C Dlp·28-40 to + 105°C DIP·28-40 to +105°C Dlp·28PACKAGE MECHANICAL DATA. 28"PIN PLASTIC DIP~.""">-I~ " . I, -,..AI 4 e.3'" D, "f'043.0/J"FCTE~l-DIm.mmInchesMin Typ Max Min Typ MaxAa 1 0.63 0.025B 0.45 0.018b 1 0.23 OJI 0.009 0.012b2 1.27 0.050CD 37.34 1.470E 15.20 16.88 0.596 0.887e 2.54 0.100e3 33.02 1.300e4F 14.10 0.555I 4.45 0.175L 3.30 0.130KlK29/10185

TS27C64AFN~TS27C64APORDERING INFORMATION (TS27C64AFN)Part Number Access TUne Supply VoltageTS27C64A-15CFN 150 ns 5V±10%TS27C64A-2OCFN 200 ns 5V±10%TS27C64A-25CFN 250 ns 5V±10%TS27C64A-3OCFN 300 ns 5V±10%TS27C64A-15VFN 150 ns 5V±10%TS27C64A-20VFN 200 ns 5V±10%TS27C64A-25VFN 250 ns 5V±10%.TS27C64A·3OVFN 300 ns 5V±10%TS27C64A-15TFN 150 ns 5V±10%TS27C64A·20TFN 200 ns 5V±10%TS27C64A-25TFN 250 ns 5V±10%TS27C64A·3OTFN 300 ns 5V±10%.Temp. Range Packageto + 70·C PLCC32to + 70·C PLCC32to + 70·C PLCC32o to + 70·C PLCC32-40 to + 85·C PLCC32-40 to + 85·C PLCC32-4010 + 85·C PLCC32-4010 + 85·C PLCC32-4010 +105·C PLCC32-4010 +105·C PLCC32-4010 +105·C PLCC32-4010 +105·C PLCC32PACKAGE MECHANICAL DATAPLCC32 32-LEAD PLASTIC LEADED CHIP CARRIER11--. 050I NOMmmInctIesDim.... Uax II. MaxA 3.04 3.55 .120 .140AI 1.98 2.41 .078 .0958 0.33 0.53 .013 .02181 0.66 0.81 .028 .0320 12.31 12.57 .485 .49501 11.35 11.50 .447 .453D2 9.90 10.92 .390 .430E 14.85 15.11 .585 .595El 13.89 14.04 . .547 .553E2 12.44 13.48 .490 .53010(10186

ST27C256FNST27C256P256K (32K x 8) CMOS ONE TIME PROGRAMMABLE ROM• COMPATIBLE TO ST27C256 EPROM (ELEC­TRICAL PARAMETER,PROGRAMMING)• PROGRAMMING VOLTAGE 12.5V.• HIGH SPEED PROGRAMMING• 28-PIN JEDEC APPROVED PIN-OUT• 32-PIN JEDEC APPROVED PIN OUT• IDEAL FOR AUTOMATIC INSERTIONPDIP-28(Plastic Package)FNPLCC32(Plastic Chip Carrier)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe ST27C256P and ST27C256FN are high speed262,144K bit One Time Programmable (OTP)CMOS ROM ideally suited for applications wherefast turn-around is an important requirement.The ST27C256P is packaged in a 28-pin dual-inlineplastic package, the ST27C256FN in a 32-pinPLCC plastic package, and therefore can not bere-written. Programming is performed according tostandard SGS-THOMSON 256K EPROM procedure.A12 2 27 1414147 26 A13AS 2S A8145 24 149144 23 1411143 7 ST27C256P 22 OE142 21 1410141 20 CE140 10 19 0100 11 IS 0601 12 17 0502 13 16 04GNO 14 15 03PIN NAMESAO-A14ADDRESSCECHIP ENABLEOEOUTPUT ENABLE00-0 7 OUTPUTSNCNON CONNECTEDDUDO NOT USEA6 ~ 5AS [ •A4[ 7A3 [ •A2 ~ ,A1 ~ 10AD ~ 11NC ~ 1200 11I 12 11 30ST27C256FN,.1516171119205S~~8~~":f>2t ~ AS28 J A927 JAil2e JNC25 ~ OE,. ~ A1D21 geE22 P 07" p06June 19881/10187

ST27C256FN-ST27C256PBLOCK DIAGRAMVcc~GNDer­Vpp~DATA OUTPUTS00-07OECEANDOE.ffPROGRAMLOGICOUTPUTBUFFERSVDECODERGATINGAO-A14ADDRESSINPUTSDECODER262,144BITCELL MATRIX5·7517MAXIMUM RATINGS (Note 1)SymbolTambTstgVpp(2)Vin(2)PDRatingOperating temperature rangeST27C256-CST27C256-VST27C256-TStorage temperature rangeSupply voltageInput voltagesExcept Vpp,Max power dissipationLead temperature(Soldering: 10 seconds)A9~ A9Valueh to THo to+ 70-40 to+85-40 to+ 105+65 to+ 125-0.6 to+ 14-0.6to+ 13.5- 0.6 to + 6.251.5+300Notes: 1. "Maximum ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating temperaturerange" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical characteristics"provides conditions for actual device operation.2. With respect to V SSUnit°c°cVVW°cOPERATING MODES~NSMODECE OE A9 Vpp Vee OUTPUTSREAD VIL VIL X Vee Vee DOUTOUTPUT DISABLE VIL VIH X Vee Vee Hi-ZSTANDBY VIH X X Vee Vee Hi-ZHIGH SPEED PROGRAMMING VIL VIH X Vpp Vee DINPROGRAM VERIFY VIH VIL X Vpp Vee DOUTPROGRAM INHIBIT VIH VIH X Vpp Vee Hi-ZELECTRONIC SIGNATURE(3) VIL VIL VH (2) VCC Vee CODENotes: 1. X can be either VIL or VIH - 2 - VH = 12.0V ± O.5V3. All address lines at VIL except A9 and AO that is toggled from VIL(manufacturer code: 96) to VIH (type code: 04).2/101885i SGS-THOMSON-:r i. i1il1~1RI©~~~~VIlil©ill~~

-~-----.-.. .._ST27C256FN·ST27C256PREAD OPERATION)C CHARACTERISTICS (Tamb = TL to TH, VCC = 5V ± 10%, VSS = OV; Unless otherwise specified)Symbol Parameter Test ConditionsMin.ValuesTypJI)III Input Load Current VIN=Vee or GND 10 "AILO Output Leakage Current ~UT=Vee or VSS,CE=VIH 10 /LAVpp Vpp Read Voltage Vee- 0.7 Vee VVIL Input Low Voltage -0.1 0.8 VVIH Input High Voltage 2.0 Vee+ 1 VVOL Output Low Voltage IOL=2.1 mA 0.45 VIOL=O /LA 0.1VOH Output High Voltage IOH= -400 /LA 2.4 VIOH=O /LA Vee- 0.1lee2 Vee Supply Active Current CE = OE = VIL, Inputs = VIH or 10 30 mATTL LevelsVIL, 1=5 MHz, 1/0=0 mAleeSBI Vee Supply Standby Current CE = VIH OE = Inputs 0.05 1 mAleeSB2 Vee Supply Standby Current CE=Vee- O.1V,OE=lnputs 1 10 /LAIpPI Vpp Read Current Vpp = Vee =5.5V 100 /LA~ole: 1. Typical conditions are for operation at: T amb = + 25°C, Vee = 5V, Vpp = Vee, and VSS = OVMax.Unit~C CHARACTERISTICS(I ,2,3)(T amb = TL to T H)27C256 27C256 27C256 27C256Symbol Parameter Test Conditions ·17 ·20 ·25 ·30 UnitMin Max Min Max Min Max Min MaxtAee Address to Output Delay CE=OE=VIL 170 200 250 300 nsteE CE to Output Delay OE=VIL 170 200 250 300 nstOE Output Enable to CE=VIL 75 75 100 120 nsOutput DelaytOF(2)(4) OE or CE High to CE=VIL 0 50 0 55 0 60 0 75 nstOH Output Hold from CE=OE=VIL 0 0 0 0 nsaddresses, CE or OEwhichever occured first~APACITANCE Tamb = + 25°C, f = 1 MHzSymbol Parameter Test Conditions Min. Typ. Max. UnitCin Input Capacitance VIN=OV 4 6 pFCout Output Capacitance VOUT=OV 8 12 pFloles: I. Vee must be applied at the same time or before Vpp and removed after or at the same time as VPP'Vpp may be connectedto Vee except during program.2. The tOF compare level is determined as follows:High to THREE-STATE, the measured VOH(OC) -O.tVLow to THREE-STATE the measured VOL(OC) + o. tV.3. Capacitance is guaranlaed BlL-Ileriodic testing. T am/l = + 25°C, f = I MHz.4. T DF, is specified from OE or eE whichever occurs first. This parameter is only sampled and not 100% tested.3/10....._.._....._._..._----_._--_...- .._-----189

ST27C256FN·ST27C256PAC TEST CONDITIONSOutput Load: 1 TTL gate and CL = 100 pFInput Rise and Fall Timess 20 nsInput pulse levels: 0.45V to 2.4VTiming Measurement Reference LevelInputs, OutputsO.BV and 2VAC TESTING INPUT/OUTPUT WAVEFORMAC TESTING LOAD CIRCUIT'.'=X'D > TEST POINTS< 20>

ST27C256FN·ST27C256PDEVICE OPERATIONThe seven modes of operation of the ST27C256are listed in the Operating Modes table. A single5V power supply is required in the read mode. Allinputs are TTL levels except for Vpp.READ MODEThe ST27C256 has two control functions, both ofwich must be logically active in order to obtain dataat the outputs. Chip Enable (CE) is the powercontrol and should be used for device selection.Output Enable (OE) is the output control and shouldbe used to gate data to the output pins, independentof device selection. Assuming that addressesare stable, address access time (tACe) is equal tothe delay from CE to Output (tCE). Data is availableat the ol!!Q..uts after a delay of tOE from the fallingedge of OE, assuming that CE has been low andaddresses have been stable for at least tACC-tOE.STANDBY MODEThe ST27C256 has a standby mode which reducesthe maximum power dissipation to 5.25 mW.The ST27C256 is placed in the standby mode byapplying a TTL high signal to the CE input. When instandby mode, the outputs are.ln.a high impedancestate, independent of the OE input.OUTPUT OR-TYINGBecause OTPs are usually used in larger memoryarrays, we have provided two control lines whichaccomodate this multiple memory connection. Thetwo control lines allow for:a) the lowest possible memory power dissipation,andb) complete assurance that output bus contentionwill not occur.To use these control lines most efficiently, CEshould be decoded and used as the primary deviceselecting function, while OE should be made acommon connection to all devices in the array andconnected to the READ line from the system controlbus. This assures that all deselected memorydevices are in their low power standby modes andthat the output pins are active only when data isdesired from a particular memory device.PROGRAMMING MODESCaution: Exceeding 14Von Vpp pin will damagethe ST27C256.Initially, all bits olthe ST27C256 are in the" 1" state.Data is introduced by selectively programming"Os" into the desired bit locations. Although only"Os" will be programmed, both "1s" and "Os" canbe presented in the data word.The ST27C256 is in the programming mode whenthe Vpp input is at 12.5 V and CE and PGM areboth at TTL Low. It is required that a 0.1 /"F capacitorbe placed across Vpp, VCC and ground tosuppress spurious voltage transients which may damagethe device. The data to be programmed isapplied 8 bits in parallel to the data output pins.The levels required for the address and data inputsare TTL.Programming of multiple ST27C256s in parallelwith the same data can be easily accomplished dueto the simplicity of the programming requirements.Like inputs of the paralleled ST27C256s may beconnected together when they are programmedwith the same data. A low level TTL pulse appliedto the CE input programs the paralleledST27C256s.HIGH SPEED PROGRAMMINGThe high speed programming algorithm describedin the flow chart rapidly programs ST27C256 usingan efficient and reliable method particularly suitedto the production programming environment. Typicalprogramming times for individual devices areon the order of 5 minute.PROGRAM INHIBITProgramming of multiple ST27C256s in parallelwith different data is also easily accomplished.Qyusing the program inhibit mode. A high level on CEinputs inhibits the other ...§J27C256s from beingprogrammed. Except for CE, all like inputs (includingOE) of the parallel ST27C256s may becommon. A......JTL low-level pulse applied to aST27C256 CE input with Vpp at 12.5V will programthat ST27C256.PROGRAM VERIFYA verify may be performed on the programmed bitsto determine that they were correctly pro.9@mmed.The verify is performed with OE at VIL, CE at V'H,and Vpp at 12.5 V.ELECTRONIC SIGNATURE MODEElectronic signature mode allows the reading outof a binary code that will indentify the EPROMs manufacturerand type. This mode is intended for useby programming equipment for the purpose of automaticallymatching the device to be programmedwith its corresponding programming algorithm. Thismode is functional in the 25°C ± 5°C ambient temperaturerange that is required when programmingthe ST27C256. To activate this mode the programmingequipment must force 11.5V to 12.5V on addressline A9 of the ST27C256. Two bytes may thenbe sequenced from the device outputs by togglingaddress line AO from V,L to V,H. All other addresslines must be held at V,L during electonic signaturemode.5/10191

ST27C256FN-ST27C256PPROGRAMMING CHARACTERISTICS (Tamb=25±5°C, VCC= 6.0V±0.25V, Vpp= 12.5V±0.3V)DC AND OPERATING CHARACTERISTICSValuesSymbol Parameter Test ConditionsUnitMin. Typ. Max.II Input Current (all inputs) VI 2 VIL or VIHVIL Input Low Level (all inputs) -0.1VIH Input High Level 2.0VOL Output low voltage during verify IOL=2.1 mAVOH Output high voltage during verify IOH= -400 ~ 2.4lee3Vee Supply current(Program & Verify)IpP2 VPP supply current (Program) CE=VIL10 ~0.8 VVee+ 1 V0.45 VV40 mA30 mAAC CHARACTERISTICSSymbol Parameter Test ConditionstAS Address Set-up Time 2toES OE Set-up Time 2tos Data Set-up Time 2tAH Address Hold Time 0tOH Data Hold Time 2tOFP Output enable to output float delay 0tvps VPP set-up time 2tves Vee set-up time 2Min.Valuestpw PGM initial program pulse width 0.95 1.0tOPW(2) CE overprogram pulse width 2.85tOEData valid from OENotes: 1. vcc must be applied simultaneously or before Vpp and removed simultaneously or'alter Vpp.2. topw is de~ined in flow chart.Typ.UnitMax./Ls/Ls/LS/LS/LS130 ns/LS/LS1.05 ms78.75 rns150 nsAC TEST CONDITIONSInput rise and fall times (10% to 90%) s20nsInput pulse levels O.45V to 2.4VInput timing reference level O.BV and 2.0VOutput timing reference level O.BV and 2.0V6110192

ST27C256FN-ST27C256PHIGH SPEED PROGRAMMING WAVEFORMSPROGRAMPROGRAM VERIFVVIHADORE SSE SX VILVIHDATAVIL12.5 VVpp6VVee5VADDRESS STABLE ItAsI 'AH"IIHIGH Z ~~DATA IN STABLE'\ DATA OUT VALIDV~'OS ~'DFP--..5VI I'VPSII.i~VIHVILVIHVIL/r=IvesCEOE\~tOES 'IOE~~ ---::.:....'OPW \~}-1. The input timing reference level is O.8V for VI Land 2.0V for VIH.2. toe and tDFP are characteristics of the device but must be be accommodated by the programmer.3. When programming the ST27C256. a O.lI'F capacitor is required across Vpp and ground to suppress spurious voltage transiens whichcan damage the device.7/10193

ST27C256FN·ST27C256PHIGH SPEED PROGRAMMING FLOW CHARTFAILDEVICEFAILED5·6&818/10194

ST27C256FN-ST27C256PORDERING INFORMATION (ST27C256P)Part NumberAccess TimeSupply VoltageTemp. RangePackageST27C256· 17CPST27C256·20CPST27C256·25CPST27C256·30CPST27C256· 17VPST27C256·20VPST27C256·25VPST27C256·30VPST27C256· 17TPST27C256·20TPST27C256·25TPST27C256·30TP170 ns200 ns250 ns300 ns170 ns200 ns250 ns300 ns170 ns200 ns250 ns300 ns5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%5V±10%to + 70°C DIP·28to + 70°C DIP·28o to + 70°C Dlp·28o to + 70°C DIP·28-40 to + 85°C DIP·28-40 to + 85°C DIP·28-40 to + 85°C DIP·28-40 to + 85°C DIP·28-40 to +105°C DIP·28-40 to +105°C DIP·28-40 to +105°C DIP·28-40 to + 105°C Dlp·28PACKAGE MECHANICAL DATA28·PIN PLASTIC DIP1-------'''-------Dim.mminchesMin Typ Max Min Typ MaxAa 1 0,63 0,0258 0,45 0.D16b 1 0,23 0,31 0,009 0,012b 2 1.27 0,050C0 37,34 1.470E 15,20 16,66 0,596 0,657e 2,54 0,100e3 33,02 1.300e4F 14,10 0,555I 4,45 0,175l 3,30 0,130K1K29/10195

ST27C256FN-ST27C256PORDERING INFORMATION (ST27C256FN)Part Number Access Time Supply VoltageTemp. RangePackageST27C256·17CFN 170 ns 5V±10%ST27C256·20CFN 200 ns 5V±10%ST27C256·25CFN 250 ns 5V±10%ST27C256·30CFN 300 ns 5V±10%ST27C256·17VFN 170 ns 5V±10oAlST27C256-20VFN 200 ns 5V±10%ST27C256-25VFN 250 ns 5V±10%ST27C256·30VFN 300 ns 5V±10%ST27C256-17TFN 170 ns 5V±10%ST27C256-20TFN 200 ns 5V±10%ST27C256-25TFN 250 ns 5V±10%ST27C256-30TFN 300 ns 5V±10%010 + 70°C PLCC32010 + 70°C PLCC32010 + 70°C PLCC32010 + 70°C PLCC32-4010 + 85°C PLCC32-4010 + 85°C PLCC32-4010 + 85°C PLCC32-4010 + 85°C PLCC32-4010 +105°C PLCC32-4010 + 105°C PLCC32-4010 + 105°C PLCC32-4010 + 105°C PLCC32PACKAGE MECHANICAL DATAPLCC32·32·LEAD PLASTIC LEADED CHIP CARRIER'--n-rTT"TT"rT"'1"l"TT"r r.023.029~1 "1r-.050I NOMDim.mmInchesllin Max Min MaxA 3.04 3.55 .120 .140A 1 1.98 2.41 .078 .095B 0.33 0.53 .013 .021B 1 0.66 0.81 .028 .0320 12.31 12.57 .485 .49501 11.35 11.50 .447 .453D2 9.90 10.92 .390 .430E 14.85 15.11 .585 .595E1 13.89 14.04 .547 .553E2 12.44 13.46 .490 .53010/10196

EEPROM DEVICESNMOS EEPROM197

SGS-1HOMSON~ ., L ~D©ffi1@rn[brn©'D'OO@~D©~ M85711024 BIT SERIAL S-BUS/12C BUS NMOS EEPROM• 10 YEAR DATA RETENTION• SINGLE + 5V POWER SUPPLY• AUTOMATIC POWER DOWN• INTERNAL HIGH VOLTAGE ANDSHAPING GENERATOR• SELF TIMED EIW OPERATION• AUTOMATIC ERASE BEFORE WRITE• 3-WIRES S-BUS (12C BUS COMPATIBLE)• 2 CHIP SELECT FOR SIMPLEMEMORY EXTENSION• SELF INCREMENTING ADDRESS REGISTER• MULTI-MODE ADDRESSING (WHEN MS = VIHALLOWING:- PARTITIONING OF THE 1024 BITS INTO:- 12th 8bit- 64 x 16bit- 32 x 32bit- OPCODE-LiKE ADDRESSES FOR:- halting of a modify operation- reading of the device "busy" status- "block erase" operation- reloading of the address register with thepre-increment valueDESCRIPTIONThe M8571 is a 1024-bit Electrically Erasable ProgrammableRead Only Memory (EEPROM). It allowspartitioning of the 1024-bit into: 128 x 8-bit(bytes); 64 x 16-bit (words); 32 x 32-bit (pages).The M8571 is manufactured with SGS­THOMSON's reliable floating gate technology. Addressesand data are transferred serially via a threelinebidirectional bus (S-BUS). When the MS pinis at VIL the device works like the PCD 8571CMOS RAM. The built-in address register is incrementedautomatically after writing or reading ofeach address partition.The M8571 is designed and tested for applicationsrequiring up to 10.000 erase/write cycles and dataretention in excess than 100 years.The M8571 is available in 8-pin dual in-line plasticand ceramic packages.PIN DESCRIPTION- Vee; GND: Power supplies.- SCL: Clock line for the S-BUS system.- SEN: Start/Stop line for the S-BUS system.- SDA: Data line for the S-BUS system (open drain).- CS1/CS2: Chip Select inputs. In order to selecta device the 2 bits (7th and 6th) in the first byteJune 1988BDIP-8(Plastic Package)(Ordering Information at the end of the datasheet)PIN NAMESCSSENSCLSDAVccGNDMSCSICS2SENGNDPIN CONNECTIONS5-7839CHIP SELECT INPUTSSTART/STOP INPUTCLOCK INPUTDATA INPUT/OUTPUTPOWER SUPPLYGROUNDMODE SELECT INPUTMSSCLSDAof the interface protocol, must match the CSvalues.- MS: Mode Select input to determine the operatingmode of the M8571 (this pill can recognizea non standard level, VIN ~ 7.5V, to enable"Block Erase" operations).1/11199

M8571BLOCK DIAGRAMr-.SENASDASCC ~~ STARTSTOP~DETECTOR(N>----- CHIP ADDRESS1 RECOGNIZERINTERFACETIMING____ GENERATOR~CSICS2o--GNDo--VCCMSSTATUS REG.E/WTIMINGCONTROL+ I~ ADDRESS+8ACKUPREGISTERSnOPCODE DECODERADDRESSESOPCODES~L~ --1 WORD l~IDECODERDATA REG.RD/WR COMPARECIRCUITS2~ COLUMNCOLUMN~ DECODER SELECTIONff-HIGH VOLTAGESUPPLY :---,."'--- ROW 16 64.1681TGENERATOR--DECODER CELL MATRIXSHAPERS-7b38f2ABSOLUTE MAXIMUM RATINGSSymbol Parameter ValueVI All Input or Output voltages with respect to ground + 6 to - 0.6Tamb Ambient temperature under bias IB1 -10 to + 80IB6 -50 to + 95Tst9 Storage temperature range -65 to + 125Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or,any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.UnitV°C°C°C2/11200

M8571ELECTRICAL CHARACTERISTICS (0° to + 70°C, for standard Temperature/- 40° to + 85°C for extendedTemperature, VCC = 5V ± 1 0% unless otherwise specified)DC AND OPERATING CHARACTERISTICSSymbol Parameter Test ConditionsValuesMin. Typ. Max.UnitILl Input Load Current VIN=5.5V 10 ~AILO Output Leakage Current VOUT=5.5V 10 ~AICC2 VCC Current Active 10 20 mAVIL Input Low Voltage .,.0.1 1.5 VVIH Input High Voltage 3.0 Vcc+l VVOL Output Low Voltage IOL=3 mA 0.4 VAC CHARACTERISTICS (refer to S-8US Timing Diagram)Symbol Parameter Test ConditionsMin.ValuesfSCL SCL clock frequency 0 125 KHzTI Tolerable spike width on bus 100 nstM SCL low to SDA data out valid 3.5 itstBUF Time the bus must be free 4 itSbefore a new transmissioncan starttHOSTA Start condition hold time 4 itStLOW Clock low period 4 itStHIGH Clock high period 4 ~stsu STA Start condition set-up time 4 its(for a repeated start condition)tHO OAT Data in hold time 0 ~stsu OAT Data in set-up time 250 nstR SDA and SCL rise time 700 nstF SDA and SCL fall time 300 nstsu STO Stop condition set-up time 4 ~sMax.UnitERASEIWRITE CHARACTERISTICSValuesSymbol Parameter Test ConditionsMin. Typ. Max.UnittEW EraselWrite cycle time Note 1 6 10 mstBE Block erase time 5 10 msNote 1: The tEW is the same for byte, word, and page configuration3/11201

M8571S-BUS TIMING DIAGRAMSDASCLSEN$-10128, SU 510 -1-44--S-BUS DESCRIPTIONThe S-BUS is a three-wire bidirectional data-buswith functional features similar to the 12C bus. Infact the S-BUS includes decoding of START/STOPconditions and the arbitration procedure in case ofmulti master system configuration. Both differenttransmission modes are shown in figures 2a and 2b.As it can be seen, the SDA line, in the 12C bus,represents the AND combination of SDA and SENlines in the S-BUS.If the SDA and the SEN lines of the S-BUS areshort-circuit connected, they appear as the SDAline of 12C bus.The START/STOP conditions (respectively points1 and 6) are detected (by the peripherals designedto work with S-BUS) by a transition of the SEN line(1- - >0/0- - >1) while the SCL line is at thehigh level.The SDA line is only allowed to change during thetime the SCL line is low (points 2, 3, 4, 5). Afterthe START information (point 1) the SEN linereturns to the high level and remains unchangedfor all the time the transmission is performed.When the transmission is completed (point 5) theSDA line is set to high level and, at the same time,the SEN line returns to the low level in order to supplythe STOP information with a low to high transition;while the SCL line is at high level.On the S-BUS, as on the 12C bus, each byte of eightbits is followed by one acknowledge bit which isa high level put on the SDA line by transmitter.A peripheral that acknowledges has to pull downthe SDA line during the acknowledge clock pulseas shown in Figure 3.SCLFIG. 1 - S-BUS CONFIGURATIONBinir\ ,,,\,,irFT-1 ! \.JJ . V \..J V W! 1: ::: :: : :~ ~--- ----J rn-:iL--11 ~iiI ,I I I I I I--h! ~-.----+---i i +SEN 1 \.LA. i· i ~ iI I,- __ JIIIIIIIII I1.. __ .JSCL1 2 3 5 6STARTSTOPFIG. 2 - I'C BUS CONFIGURATIONr--'--ti\fv', 1\JVt!~ : r-~~----. ... i! fiSOA i~ ~iL_JL_Jr--..,STARTFIG. 3 - ACKNOWLEDGESTOPSCL ~SOA ~,:i,1 ~SEN\ i '---11'-'\-,-'/-'----....,~ ~ ____ J~! I----------~I--------------! \l..Jl_JSTARTi4/11202

M8571S-BUS DESCRIPTION (Continued)An addressed receiver has to generate anaknowledge after the reception of each byte; otherwisethe SDA line remains at the high level duringthe ninth clock pulse time.In this case the master transmitter can generatethe STOP information, via the SEN line, in orderto abort the transfer.COMPATIBILITY S-BUS/l2C BUS.Using the S-BUS protocol it's possible to implement"mixed" system including S-BUS/l2C busperipherals.In order to have the compability with the 12C busperipherals, the devices including the S-BUS interfacemust have their SDA and SEN pins connectedtogether as shown in figures 5a and 5b.It is also possible to use mixed S-BUS/l2C bus protocolsas showed in figure 5c. S-BUS peripheralswill only react to S-BUS protocol signals, while 12Cbus peripheral will only react to 12C bus signals.FIG. 4 - SYSTEM WITH S-BUS PERIPHERALSseLSDASEN~pS·BUSPROTOCOL5-792512seLSDASENseL- SDA'--- SENS-8USDEVICES-BU5DEVICEFig. 5 - SYSTEM WITH "MIXED" S-BUS/12C BUS PERIPHERALseLSOASEN ~seLL SDASENseLSOAseLSDAL SEN,",p5-8USPROTOCOLM8S?1[2C BUSMASTERMaS71~~SCLL--seL- SDA- SDA(a)12C BUSSLAVE(b)12C BUSSLAVE5-7929seLSOASEN,",p5-BUSIJIe BUSPROTOCOLseLSOASENMaS?1(e)-L--seLSOAPC BUSSLAVE.5/11203

M8571S·BUS DESCRIPTION (Continued)MUL TIMASTER SYSTEM.The S·BUS allows the implementation of the multimasterconfiguration (two or more master stationsand slave peripherals). In such a system if two ormore transmitter, through the SEN line (SEN 1 ..... 0while SCL= 1), require the bus at the same time, thearbitration procedure is performed as in the 12C bus.FIG. 6 - MUL TIM ASTER SYSTEMseLSCLSOASOASENSEN~p ~pS-BUSS-8USMASTERMASTERselSOASEN~pS-BUSMASTER_1seLSOA,"pPC8USMASTER~ sel>-- SOASEN>-- sel~- SOAM8S?112C BUSSLAVE- sel- SOA5EN- sel~ SOA'---- SEN5-864811S-BUSSLAVE5 8649"Ma5?16/11204

M8571S·BUS INTERFACEThe serial, 3-wire, interface (SDA, SCl and SEN,,:,ires are open drain to allow "wired-and" operation)connects several devices which can be dividedinto "masters" and "slaves". A master is a devicethat can manage a data transfer; as such, it drivesthe Start and Stop (SEN), the clock (SCl) and thedata (SDA) lines. The bus is "multimaster" in thatmore master devices can access it; arbitrationprocedures are provided in the bus management.Obviously, at least one master must be present onthe bus. The M8571 is a hardware slave device.It can only answer the requests of the masters onthe bus; therefore SDA is an 110, while SCl andSEN are inputs. The S-8US allows two operatingspeed: high (125KHz) and low (2KHz). The M8571can work at both high and low speed.START/STOP ACKNOWLEDGEThe timing specs of the S-8US protocol require thatdata on the SDA and SEN lines be stable duringthe "high" time of SCL. Two exceptions to this ruleare foreseen and they are used to signal the startand stop condition of a data transfer.A "high to loW" transition on the SEN line, with SCl"high", is a start (STA),A "low to high" transition on the SEN line, with SCl"high", is a stop.Data are transmitted in 8-bit groups; after eachgroup, a ninth bit is interposed, with the purposeof acknowledging the transmitting sequence (thetransmitter device place a "1" on the bus, the acknowledgingreceiver a "0").INTERFACE PROTOCOLThe following description deals with 8-bits datatransfers, so that it fully fits when the memory is"seen" as 128 x 8 array. Although the basic structureof the protocol remains the same the behaviourof the M8571 in 16 or 32 bit data transfers is somewhatdifferent. The differencies are descibed lateron.The interface protocol comprises:- A start condition (STA)- A "chip address" byte, trasmitted by the master,containing two different informations.a) the code identifying the device the masterwants to address (this information is presentin the first seven bits); 4bits indicates thetype of the device (Le. memory, tuning, AID,etc.; the code for memories is 1010); thenthere is a bit at low level and 2bits that arethe Chip Select configuration that mustmatch the hardware present on the 2 CSpins (this is the case of a device with 2 ChipSelect like the M8571 , for M8571 CS1 andCS2 must match respectively the 7th and the6th bit of the byte).b) the direction of transmission on the bus (thisinformation is given in the 8th bit of thebyte); "0" means "Write", that is from themaster to the slave, while "1" means"Read". The addressed slave must alwaysacknowledge.The sequence, from now on, is different accordingto the value of the RIW bit.1) RiW = "0" (WRITE)In all the following bytes the master acts astransmitter; the sequence follows with:a) a "word address" byte containing the addressof the selected memory word and/oropcode (see word address/opcode section).b) a "data" byte which will be written at the addressgiven in the previous byte.c) further data bytes which, due to the self incrementingaddress register, will be writtenin the "next" memory locations. At the endof each byte the M8571 acknowledges.d) a stop condition (STO)After receiving and acknowledging a data byte ora set of data bytes to be written, the M8571 automaticallyerases the addressed memory locationsand rewrites them with the received data. Since theEIW time for an EEPROM is in the order of 10 msthe next operation can take place only after tE~(what the master can and must do is described inthe E/W TIME SPECS section).An example of a write sequence is given beJow:o. STA1. 10100ss0 A (M8571 acknowledges only if"ss" matches its CS code)2. xyyyyyyy A3. z z z z z z z z A (at this moment the M8571starts writing zzzzzzzz at theaddress yyyyyyy)4a. t t t t t t t t H (the new data is not acknowledgedwhile the M8571 isbusy)4b. t t t t t It t A (now the M8571 writes datat t t t t t It at addressyyyyyyy + 1)The write sequence can be composed by an unlimitednumber of data bytes.7/11205

M8571MASTER TRANSMITS TO SLAVE RECEIVER (WRITE MODE)Is Iacknowtedgefrom lIaveItR/Wacknowledge'rom lIaveI MSBacknowledgefrom slave~L--Iastb~auto incrementmemory word address2) R/W = "1" (READ)In this case the slave acts as transmitter and, therefore,the transmission changes direction. The secondbyte of the sequence will be sent by theM8571 and it will contain the data present in thememory present at the address pointed by the "current"value of the address register. Following byteswill be the data present at the "next" addresses.At the end of each byte, the M8571 places a "1"on the bus during acknowledge time and waits forthe master to send a "0" (meaning "acknowledge").When the master want to stop the transfer, it givesa "1" (not "acknowledged"): as a consequence,the M8571 leaves the bus high so that the mastercan give the stop condition. An example is givenbelow:O. STA1. 10100ss1 A2. xxxxxxxx H (xxxxxxxxisthedatapresentin the currently addressedmemory location; H is the highlevel placed on the bus byM8571)3) MIXED SEQUENCEWhen the master wants to read a memory locationdifferent from the one currently addressed, a longersequence is needed, which includes the writing ofthe address register. The sequence is as follows:O. STA1. 10100ss0 A2. xyyyyyyy A3. STA4. 10100ss1 A5. xxxxxxxx HWhere xxxxxxxx is the data present in the yyyyyyymemory locationAs appears from the example, a start condition canbe given without a previous stop condition.MASTER READS SLAVE IMMEDIATELY AFTER FIRST BYTE (READ MODE)acknowledge acknowledge acknowledge'rom lIave 'rom master 'rom master, 'MSB iI 5 I ~L~VE: A~O~E~ :. H : : :OA:TA: : : H : : : : : : : 11 I p IR/tW L--- n bytes---ij L-- n bytes ~auto incrementword address8/11206

M8571MASTER. READS AFTER SETTING WORD ADDRESS (WRITE WORD ADDRESS; READ DATA)acknowtedilefrom slaveacknowtedgefrom ,laveacknowledgefrom slaveacknowledgefrom meater~ ~ ~S SLAVE ADDRESS 0 A X WORD ADDRESS A S SLAVE ADDRESS DATA Aacknowledgefrom masterlise ~I : : :D~TA: : : I, I p IL..- last byte ~••• his moment mas.er } ~ n bytes --lItransmitter becomesmaster receiver andM8S71 slave receiverbecomes slave transmitterAI Wauto incrementword address4) EfW TIME SPECSAfter the beginning of an EfW operation at a certainlocation the M8571 is "busy" until the operationis finished. To show this busy state, the M8571refuses acknowledge of the next data bytes to removethe M8571 from the "busy" state a data bytemust be sent after the tEW is over. This "dummy"byte will not be acknowledged and written. The datato be written in the next address must be sent againand will be acknowledged and written by theM8571.The master device that wants to use the self incrementfeature must therefore keep sending the nextdata byte and monitoring the acknowledge bit untilit becomes active.The communication sequence on the bus becomes,therefore.O. STA1. 10100ss0 A2. xyyyyyyy A3. zzzzzzzz A4a. t t t t t t t t H (not acknowledged whent

M85715) WORD ADDRESS/OPCODEThe second byte transmitted in a write sequencecan assume several meaning according to thevalue of the MS pin. In any case, it carries all theinformations the M8571 needs to perform thedesired operation.MS can assume three different values:- VIL (VIN :$ 1.5V)- VIH (3.0V :$ VIN < Vce + 1)- VH (9.0V :$ VIN :$ 12V)With regards to the value of MS, the possible behavioursare:a) MS = VIL ("RAM mode")In this mode the M8571 is compatible with thePCD 8571 RAM (128 x 8bit). The second byteof the sequence gives the address of the wordto be selected, both for write and for read:1. xyyyyyyy Ayyyyyyy is the word address; the first bitis "don't care; the main feature of thismode are the following:the memory appears as an 128 x 8 arrayonly "byte operations are allowed;EIW operations are stopped by thefollowing accesses.b) MS = VIH (EEPROM mode)The word address-byte now must be regarded asmixed address-opcode byte; more precisely, thefirst three bits indicate the meaning to be attributedto the remainder of the byte. The possible combinationsare:Oyyyyyyy10yyyyyy110yyyyy11111111111000001110010011110001byte-mode (8 bits) RD or EIWat address yyyyyyyword-mode (16 bits) RD or EIWat address yyyyyypage-mode (32 bits) RD or EIWat address yyyyyEIW cycle stopRead busy bitBlock Erase (needs VH on MSpin, see also BLOCK mode)Reload Address Register withpre-increment dataIn this mode, as well as in RAM mode, the "busy"information is transmitted from the M8571 to themaster using the "no acknowledge" format. Furthermore,"Read busy bit" instruction, which is alwaysanswered by the M8571 no matter what it isdoing, allows the master to know wheter the "noacknowledge" condition comes from a "busy" statusor from a malfunction; the "busy" status is signalledby the byte 11100101; the "no busy" by00011010.Also in this mode the self-incrementing addressregister is available, both for read and for write, foreach word length.The M8571 is provided with a double register forstoring the address that is sent during the secondbyte of a write sequence.When the self-incrementing is used, this addressbecomes the "starting address" of the modifiedstring of bytes. The "reload" instruction allows themaster to recover this address if it wants to readthe modified string from the beginning, without theneed for external storage of the "starting address".c) MS = VH (BLOCK mode)The only instruction that can be executed in thismode is "Block Erase", which is useful to erasethe whole array in a single shot. This can occureither during testing or at the set-up of a new system,when the whole memory must be written.When this instruction is given, the self-timing circuitryis disabled, so that the operation must bestopped (after tBE) by the master executing aSTART on the bus. The "enable" feature obtainedwith the non standard level on MS was added toavoid unintentional clearing of the whole memory,whenever the "Block Erase" code was erroneouslysent.6) 16-bit or 32-bit OPERATIONSThe obvious advantage of an operation on 16 bits(a word) or on 32 bits (a page) is that the EIW timeis 1 Oms for the whole word or page. When a wordor page mode operation is required, the device behaviourundergoes some slight modifications:The M8571 waits for receiving all the bytes thatcompose the word or the page before starting anEIW operation;- The self-incrementing address register keeps intoaccount the word or page lenght so that, at theend of a word or page mode operation, it pOintsto the next word or page.10/11208

M8571ORDERING INFORMATIONPort Number Max Frequency Supply VoltageM8571B1M8571B6125 KHz 5V±10%125 KHz 5V±10%Temp. RangePackage0° to + 70 0 e Dlp·8- 40° to + 85°e DIP·8PACKAGE MECHANICAL DATAa-PIN PLASTIC DIP/-.'ILl;:~'If-t\jj~~I I I- .ll..10- 81. i-r--- -; j..l>. .,i-!--z001nn'...n.....n.B ,- ~- -- r-, ,U UIU UPOO1·F/6m-\ I IEI- ~Dim.mmInchesMin Typ Max Min Typ MaxAal 0.70 0.028B 1.39 1.65 0.055 0.065Bl 0.91 1.04. 0.036 0.041b 0.50 0.02bl 0.38 0.50 0.015 0.020C0 9.80 0.38601E 8.90 0.350e 2.54 0.100e3 7.62 0.300e4F 7.10 0.280I 4.80 0.189l 3.30 0.130NZ 0.44 1.80 0.017 0.06311/11209

M9306256 BIT (16 x 16) SERIAL NMOS EEPROM• SINGLE SUPPLY READIWRITE/ERASEOPERATIONS (5V±10%)• TTL COMPATIBLE• 16x16 READIWRITE MEMORY• LOW STANDBY CURRENT• LOW COST SOLUTION FOR NON VOLATILEERASE AND WRITE MEMORY• RELIABLE FLOTOX PROCESS• EXTENDED TEMPERATURE RANGEBDIP-8(Plastic Package)MS08(Plastic Micropackage)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe M9306 is a 256 bit non-volatile sequential accessmemory manufactured using SGS­THOMSON FLOATING GATE process. It is aperipheral memory designed for data storageand/or timing and is accessed via a simple serialinterface.The device contains 256 bits organized as 16 x 16.The M9306 has been designed to meet applicationrequiring up to 10000 EIW cycles per word. Writteninformation has at least 10 years data retention.A power down. mode allows consumption tobe decreased.CS 1 8 VCCNC01 3 6 NC00 4 5 GNOPIN NAMESS-6969CSSKDIDOVeeGNDCHIP SELECTSERIAL DATA CLOCKSERIAL DATA INPUTSERIAL DATA OUTPUTPOWER SUPPLYGROUNDJune 19881/6211

M9306BLOCK DIAGRAM00DI---+-+-+-+------~--~INSTRUCTION'----------------1 DECODECS--~------------------~CONTROl.ANDCLOCKGENERATORSSK----------------~1_ ______ t_------~~~5-697011ABSOLUTE MAXIMUM RATINGSSymbol Parameter ValuesVI Voltage Relative to GND +6V to -0.3Tamb Ambient Operating Temperature: standard o to + 70extended -40 to +85TstQ Ambient Storage Temperature -65 to + 125UnitV°C°C°CStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability (except for T amb)2/6212

M9306ELECTRICAL CHARACTERISTICS (O°C to + 70°C, for standard Temperature/- 40°C to + 85°C forextended Temperature, VCC = 5V ± 10% unless otherwise specified)Symbol Parameter Test Conditions Min. Typ. Max. UnitVcc Operating Voltage 4.5 5.5 VICC1 Operating Current Vcc = 5.5V, CS = 1 1.5 5 mAICC2 Standby Current Vce=5.5V. CS=O 1.2 3 mAIce3 EIW Operating Current Vce=5.5V 2.5 6 mAVIL Input Voltage Levels -0.1 0.8VIH 2.0 Vee+ 1VOL Output Voltage Levels IOL=2.1 mA 0.4VOH IOH = - 400 p.A 2.4ILl Input Leakage Current VIN=5.5V 10 ",AILO Output Leakage Current Vour=5.5V, CS=O 10 ",ASK Frequency 250' kHzSK Duty Cycle 25 75 %Input Set-Up and HoldTimes:tess CS 0.2 ",stesH 0tOIS 01 0.2tOIH 0.2tp01 Output Delay CL=100 pF 0.5 ",stpoe DO VOL=0.8V, 0.5VOH=2.0VtEIW EraselWrite Pulse Width 5 30 mstes Min CS Low Time (Note 1) CL = 100 pF 1 ",s• The maximum SK Frequency is 500 KHz when SK Duty Cycle is as 50%~ote: 1. CS must be brought low for a minimum of 1",s (Ves) between consecutive instruction cycles.VV3/6213

M93D6FUNCTIONAL DESCRIPTIONThe input and output pins are controlled byseparate serial formats. Seven 9-bit instruction canbe executed. The instruction format as a logical "1"has a start bit, four bits as an op code, and fourbits of address. The on-chip programming voltagegenerator allows the user to use a single power supply(Vce). The serial output (DO) pin is valid onlyduring the read mode. During all other modes theDO pin is in high impedance state, eliminating buscontention.READThe read instruction is the only instruction whichoutputs serial data on the DO pin. After a READinstruction is received, the instruction and addressare decoded, followed by data transfer from the memoryregister into a 16 bit serial out shift register.A dummy bit (logical "0") preceds the 16 bit dataoutput string. The output data changes during thehigh state of the system clock.ERASEIWRITE ENABLE AND DISABLEProgramming must be preceded once by programmingenable (EWEN) instruction. Programming remainsenabled until a programming disable(EWDS) instruction in executed. The programmingdisable instruction is provided to protect againstaccidental data disturbance.Execution of a READ instruction is independent ofboth EWEN and EWDS instructions.ERASELike most EEPROMs, the register must first be erased(all bits set to 1 s) before the register canbe written (certain bits set to Os). After an ERASEinstruction is input, CS is dropped low. This fallingedge of CS determines the start of programming.The register at the address specified in the instructionis then set entirely to 1 s. When the erase/writeprogramming time (tE/w) constraint has beensatisfied, CS is brought up for at least one SK period.A new instruction may then be input, or a lowpower standby state may be achieved by droppingCS low.WRITEThe WRITE instruction is followed by 16 bits of datawhich are written into the specified address. Thisregister must have been previously erased. Likeany programming mode, erase/write time is determinedby the low state of CS following the instruction.The on chip high voltage section onlygenerates high voltage during this programmingmode, which prevents spurious programming duringother modes. When CS rises to V1H, the programmingcycles ends. All programming modeshould be ended with CS high for one SK period,or followed by another instruction.CHIP WRITEEntire chip can be written for ease of testing. Writingthe chip means that all registers in the memoryarray have each bytes set as the byte sent withthe instruction.CHIP ERASEEntire chip erasing is provided for ease of programming.Erasing the chip means that all registers inthe memory array have each bit set to a 1. Eachregister is then ready for a WRITE instruction.INSTRUCTION SETInstruction 58 Op Code AddressREAD 1 10XX A3A2A1AOWRITE 1 01XX A3A2A1AOERASE 1 11XX A3A2A1AOEWEN 1 0011 X X X XEWDS 1 0000 XXXXERAL 1 0010 XXXXWRAL 1 0001 XXXXDataD15-DOD15-DOCommentsRead register A3A2A 1 AOWrite register A3A2A 1 AOErase register A3A2A 1 AOErase/write enableErase/write disableErase all registersWrite all registers4/6214

M9306TIMING DIAGRAMS5K01C500A(AOWAITE~SKCS01001SK* THI515 THE MAXIMUM 5K FREQUENC.YS_697112J~J0:\,-____ ~~ ___________\1... ___ _---------------~~JlJlJ1J"ULJUl.J VUU V1..fl.Jl.SlJLf1JlcsJ I I I~J,.--------01 ~~EAA5E(WEN(~:~E/WRITE(NABLE'DISABLE)£AAl(ERASE ALL)WRAL~::~~~~01~1 1\0 C;::;X~~I SKcs~ ::L01 --.-JI\O_____~~~A~3~~A~2~~A~1~~AO~~~~DON'T~.::~,.-L__CARE,~~...... , ...... ~.J'=:JI\=""_~~5-1:1\05/6215

M9306ORDERING INFORMATIONPart Number Max Frequency Supply Voltage Temp. Range PackageM9306B1 250 KHz 5V±100f0 0° to + 70 0 e DIP-8M9306B6 250 KHz 5V±100f0 - 40° to + 85°e DIP-8M9306M1 250 KHz 5V±100f0 OOto + 70 0 e S08M9306M6 250 KHz 5V±100f0 - 40° to + 85°e S08PACKAGE MECHANICAL DATA8-PIN PLASTIC DIP mm inchesDim.Min Typ Max Min Typ MaxA.1 0.70 0.028B 1.39 1.65 0.055 0.065Bl 0.91 1.04 0.036 0.041b 0.50 0.02bl 0.38 0.50 0.Q15 0.020CD 9.80 0.386DlE 8.90 0.3508 2.54 0.100a3 7.62 0.30084F 7.10 0.280I 4.80 0.189L 3.30 0.130NZ 0.44 1.60 0.017 0.063P001·F/68-LEAD PLASTIC MICROPACKAGE mm Inc~esDim.Min Typ Max Min Typ MaxA 2.00 0.Q79al 0.10 0.20 0.004 0.008a2 1.70 0.067b 0.40 0.Q16bl 0.20 0.008CclD 5.08 0.200E 6.30 0.248•1.27 0.05083 3.81 0.150F 4.10 4.30 0.161 0.169G 4.90 0.193L 0.25 . 0.Q10M 0.635 0.025NAP013·DI16/6216

SGS-THOMSON~ .." L ~o©oo@rnl1,rn©'i]'OO@[K!]O©~ M93461024 BIT (64 x 16) SERIAL NMOS EEPROM• SINGLE SUPPLY READIWRITE/ERASEOPERATIONS (5V±10%)• TTL COMPATIBLE• 64x 16 READIWRITE MEMORY• LOW STANDBY CURRENT• LOW COST SOLUTION FOR NON VOLATILEERASE AND WRITE MEMORY• RELIABLE FLOTOX PROCESS• SELF-TIMED PROGRAMMING CYCLE• DEVICE STATUS SIGNAL DURINGPROGRAMMING• POWER-ON/OFF DATA PROTECTIONCIRCUITRY• AUTOERASE• BULK PROGRAMMING ENABLE OR DISABLEFOR ENHANCED DATA PROTECTIONDESCRIPTIONThe M9346 is a 1024 bit non-volatile sequential accessmemory manufactured using SGS­THOMSON FLOATING GATE process. It is a peripheralmemory designed for data storage and/ortiming and is accessed via a simple serial interface.The device contains 1024 bits organized as64x16. Written information is stored in a floatinggate cell until updated by an erase and write cycle.Bulk programming instructions (Chip Erase, ChipWrite) can be enabled or disabled by the user forenhanced data protection. The M9346 has beendesigned for applications requiring up to 104 erase/writecycles per register. A power down modeallows a consumption decrease by 75%.PIN NAMESCSSKDIDOVccGNDBPENCCHIP SELECTSERIAL DATA CLOCKSERIAL DATA INPUTSERIAL DATA OUTPUTPOWER SUPPLYGROUNDBULK PROGRAMMING ENABLENO CONNECTBDIP-8(Plastic Package)MS014(Plastic Micropackage)(Ordering Information at the end of the datasheet)PIN CONNECTIONSCS 1 8 VceSK 2 NC01 3 6 BPE00 4 5 GNOS-6969/1NC 1 NCCSSKNCVCCNCNC01 BPEDONCS -10636NCJune 19881/9217

M9346BLOCK DIAGRAMDl~-r------------------s "77~2 { 2ABSOLUTE MAXIMUM RATINGSSymbol Parameter Values UnitVI Voltage Relative to GND + 6Vto -0.3 VTamb Ambient Operating Temperature: standard o to + 70°Cextended -40 to +85Tstg Ambient Storage temperature ". -65 to + 125 °cStresses in excess of those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at these or any other conditions in excess of those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability (exceptfor Tamb).2/9218

M9346ELECTRICAL CHARACTERISTICS (0° to + 70°C, for standard Temperarure/- 40° to + 85°C for extendedTemperarure, VCC = 5V ± 10% unless otherwise specified)Symbol Parameter Test Conditions Min. Typ.Vcc Operating Voltage 4.5ICCl Operating Current Vcc=5.5V, CS=1 1.5ICC2 Standby Current Vcc=5.5V, CS=O 1.2ICC3 EIW Operating Current Vcc=5.5V, SK=1 2.5VIL Input Voltage Levels -0.1VIH 2.0VOL Output Voltage Levels IOL=2.1 mAVOH IOH= -400 p.A 2.4III Input Leakage Current VIN=5.5VILO Output Leakage Current Vour=5.5V, CS=OSK Frequency 0SK Duty Cycle 25Input Set-Up and HoldTimes:tCSAE CS (Note 2) 0.4tcss 0.2tCSH 0tOIS0.401tOIH0.4tpOl Output CL=100 pFDOVOL = 0.8V, VOH=2Vtpoo VIL = 0.45V, VIH = 2.40VtE/wSelf-Timed Program Cycletcs Min CS Low Time (Note 1) 1tsv Rising Edge of CS to CL=100 pFStatus ValidtOH, tlHFalling Edge of CSto DO tri-stateMax. Unit5.5 V12 mA3 mA12 mA0.8Vcc+1V0.4V10 I'A10 I'A250 kHz75 %I's2I'S210 msI'S1 I's0.4 I'sNote:.1. CS must be brought low for a minimum of l~s (I{:"') between consecutive instruction cycles.2. tCSAE condition has to be fullfilled in "WRITE WITH AUTOERASE" mode.3/9219

M9346FUNCTIONAL DESCRIPTIONThe input and output pins are controlled byseparate serial formats. Eight 9-bit instructions canbe executed. The instruction format has a logical"1" as a start bit, two bits as an op code, and sixbits of address. The on-chip programming voltagegenerator allows the user to use a single power supply(Vccl. It only generates high voltage during theprogramming modes (write, erase, chip-erase, chipwrite)to prevent spurious programming duringother modes.The programming cycle is self timed, with the dataout (DO) pin indicating the ready/busy state of thechip. The serial output (DO) pin is valid as data outduring the read mode, and if initiated, as aready/busy status indicator during a programmingcycle. During all other modes the DO pin is in highimpedance state eliminating bus contention. TheBulk programming instructions (ERAL, WRAL) areenabled or disabled by the BPE pin. This pin connectedto V 1H enables the executions of previousmentioned instructions. The BPE pin connected toV1L causes the same instructions to be ignored. Ifthe BPE pin is not connected, it is pulled-up to Veeby an on-chip pull-up and the Bulk programminginstructions are enabled. Execution of the EWEN,EWDS, WRITE and ERASE instructions are independentfrom the state of the BPE pin.READThe read instruction is the only instruction whichoutputs serial data on the DO pin. After a READinstruction is received, the instruction and addressare decoded, followed by data transfer from thememory register into a 16 bit serial out shift register.A dummy bit (logical "0") precedes the 16 bit dataoutput string. The output data changes during thehigh state of the system clock.ERASEIWRITE ENABLE AND DISABLEWhen Vee is applied to the part it powers up in theprogramming disable (EWDS) state, programmingmust be preceded by programming enable (EWEN)instruction. Programming remains enabled until aprogramming disable (EWDS) instruction is executedor Vee is removed from the part. The programmingdisable instruction is provided to protectagainst accidental data disturb. Execution of aREAD instruction is independent of both EWENand EWDS instructions.ERASE (Note 2)Like most EEPROMs, the register must first beerased (all bits set to logical' 1 ') before the registercan be written (certain bits set to logical '0'). Afteran ERASE instruction is input, es is dropped low.This falling edge of es determines the start ofthe self-timed programming cycle. If es is broughthigh subsequently (after observing the tes specification),the DO pin will indicate the ready/busy statusof the chip. The DO pin will go low if the chipis still programming. The DO pin will go high whenall bits of the register at the address specified inthe instruction have been set to a logical' 1'. Thepart is now ready for the next instruction sequence.WRITE (Note 2)The WRITE instruction is followed by 16 bits of datato be written into the specified address. After thelast bit of data (DO) is put on the data in (DI) pin,es must be brought low before the next rising edgeof the SK clock. This falling edge of es initiatesthe self-timed programming cycle. Like all programmingmodes, DO indicates the ready/busy statusof the chip if es is brought high after a minimumof 1 fls (tes). DO = logical '0' indicates thatprogramming is still in progress. DO = logical '1'indicates that the register at the address specifedin the instruction has been written with the data patternspecified in the instruction and the part is readyfor another instruction. The register to be writteninto must have been previously erased.WRITE WITH AUTOERASE (Note 2)The WRITE instruction is followed by 16 bits of datato be written into the specified address. After thelast bit of data (DO) is put on the data in (DI) pines must be brought low before the next falling edgeof the SK clock.This falling edge of es initiates the self-timedprogramming cycle. Like all programming modes,DO indicates the ready/busy status of the chip ifes is brought high after a minimum of 1 fls (tcs).DO = logical '0' indicates that programming is stillin progress. DO = logical '1' indicates that theregister at the address specifed in the instructionhas been written with the data pattern specified inthe instruction and the part is ready for another instruction.4/9220

M9346FUNCTIONAL DESCRIPTION (Continued)CHIP ERASE (Note 2)Entire chip erasing is provided for ease of programming.Erasing the chip means that all registers inthe memory array have each bit set to a logical '1'.Each register is then ready for a WRITE instruction.The chip erase cycle is identical to the erase cycleexcept for the different op code. The Chip Erase(ERAL) instruction is ignored if the BPE pin isat VIL, i.e. the array data is not changed.CHIP WRITE (Note 2)All registers must be erased before a chip write operation.The chip write cycle is identical to the writecycle except for the different op code. All registersare simultaneously written with the data patternspecified in the instruction. The Chip Write (WRAL)instruction is ignored if the BPE pin is at VIL, i.e.the array data is not changed.01100It is possible to connect the Data In and Data Outpins together. However, with this configuration itis possible for a "bus conflict" to occur during the"dummy zero" that precedes the read operation,if Ao is a logic high level. Under such a conditionthe voltage level seen at Data Out is undefined andwill depend upon the relative impedance of DataOut and the signal source driving Ao. The highercurrent sourcing capability of Ao, the higher voltageat the Data Out pin. To solve this problem the01 pin must be in high impedance after the last risingedge of the SK clock.POWER ON DATA PROTECTION CIRCUITRYDuring power-up all modes of operation are inhibiteduntil Vee has reached a level of between 2.8and 3.5 volts. During power-down the source dataprotection circuitry acts to inhibit all modes whenVee has fallen below the voltage range of 2.8 to3.5 volts.Note 1: es must be brought low for a minimum of 1 p.S (tesl betweenconsecutive instruction cycles.Note 2: During a programming mode (wrHe, erase, chip erase, chipwrite). SK clock is only needed while the actual instruction. i.e. startbH, op code, address and data, is being input. It can remain deactivatedduring the EraselWrite pulse width (tEIW)'5/9221

M9346INSTRUCTION SETInstruction S8 Op Code Address Data CommentsREAD 1 10 ASA4A3A2A1AO Read register ASA4A3A2A1AOWRITE 1 01 ASA4A3A2A1AO 01S-00 Write register ASA4A3A2A1AOERASE 1 11 ASA4A3A2A1AO Erase regil'ter ASA4A3A2A1AOWR. AUTOERASE 1 01 ASA4A3A2A1AO 01S-00 Erase/write register ASA4A3A2A 1 AOEWEN 1 00 11 x x x x Erase/write enableEWOS 1 00 OOxxxx Erase/write disableERAL 1 00 10 xx x x Erase all registersWRAL 1 00 ... 01 x x x x 01S-00 Write all registersM9346 has 8 instructions as shown. Note that the MSB of any given instruction is a "1" and is viewed as a start bit in the interface sequence.The next 8 bits carry the op code and the 6-bit address for 1 of 64, 16-bit registers.TIMING DIAGRAMSSYNCHRONOUS DATA TIMINGVIHSKVIL()4jIs01VIHVILCS VIHVIL"oH00 VOL2pstpootpOI* THIS IS THE MINIMUM SK PERIOD7-.7723/16/9222

M9346TIMING DIAGRAMSINSTRUCTION TIMINGCS/~--------------------~)r-----CHECK STATUSSTANDBYERASEDOTRI-STATE/~~~~--------------~~I[lJL11.Jl.SLrLtcsICS------------------------------------~'fCHECK STATUS STANDBYERALtcsCS J CHECK STATUS STANDBYWRALOJDOTRI-STATE5-7725117/9223

M9346TIMING DIAGRAMS (Continued)INSTRUCTION TIMINGSKJ1....f1...f1..'I.....fUU1..S4n.n..fl,f1..JLJ1...J'esI~r-__________________ ~lri---~r~rAN~~es / ~READ01 ~XiiO\ ........---.....,~---_ji_l-----DOtOH tlH_~TR~I..~S~TA~T~E ____________ ~:xJo~I)GOO~~~-T~R~I.~S~TA~T~E_es /WRITEWRITEWITHes /AUTOERA:;,r 01 ~~,J\~~---+ .. fj .. ----+--00TRI-STATESKEWENEWOSes /''\ STANDBY01 -----f'T'\I.!OL.......QO...j/{,~\{i:::*ll'1I.!wj,Zlzr/,~w,~W-1liWfiZlw1li;wj,Zl~~l(;j,Zl~,I-r------------_ENABLE =11DISABLE =00 $-7721./18/9224

M9346ORDERING INFORMATIONPart Number Max Frequency Supply Voltage Temp. Range PackageM9346B1 250 KHz 5V±100f0 0 0 to + 70 0 e DIP-SM9346B6 250 KHz 5V±100f0 -40 0 to +S5°e DIP-SM9346M1 250 KHz 5V±100f0 0° to + 70 0 e S014M9346M6 250 KHz 5V±100f0 - 40° to + S5°e S014PACKAGE MECHANICAL DATAa·PIN PLASTIC DIP mm inchesDim.Min Typ Max Min Typ Max~i\ I I Bl 0.91 1.04 0.036 0.041I--1r--t! A.1 0.70 0.028-J. r-- I-F=; ,---l8 1.39 1.65 0.055 0,065b 0.50 0.02I- ...hl- bl 0.38 0,50 0.015 0.020I I IC-~- B1. '- D 9.60 0.386- .l>-Dl~ EZ e' Z E 6.90 0,350•2.54 0.1000 .3 7.62 0.300DI.4.n n 'n.nF 7.10 0.2808 ; I 4.60 0,189L 3.30 0.130~-- --e- N, ,U LJILJ UPOOI.F/6Z 0.44 1.60 0.017 0.06314·LEAD PLASTIC MICROPACKAGE mm inchesDim.Min Typ Max Min Typ MaxL G A 1.75 0.069'r~ !, gillal 0.10 0.20 0.004 0.008In ~~a2 1.60 0.063I ~ b 0.35 0.46 0.014 0.D18U\bl 0,19 0.25 0.007 0.010j nu =iC 0,50 0.020E f- l ~ cl 45' 45'Dill 8.55 8.75 0.337 0.344o ,__E 5.80 6.20 0.228 0.2441,27•0.050.3 7,62 0.300Fill 3.80 4.00 0.150 0.157I! .G 4.60 5.30 0.181 0.209~ n n n rh n n r~L 0.50 1.27 0.020 0.050M 0,68 0.027,NiR- j-------f----- -~U U U ~ U U U S 8' 8'PO/3·G/3 ' Note: 1. D and F do nol include moldflash or prolusions. They should nol exceed0.15 mm/.006 inches.919225

EEPROM DEVICESCMOS EEPROM227

ST24C022K BIT SERIAL 2 WIRE BUS CMOS EEPROMPRELIMINARY DATA• 256 x 8 SERIAL EEPROM• SINGLE +5V ONLY OPERATION• COMPATIBLE WITH THE INTER­INTEGRATED-CIRCUIT BUS• FULLY TTL COMPATIBLE INPUTS ANDOUTPUTS• UNLIMITED READ ACCESSES• ESD PROTECTION: INPUTS ARE DESIGNEDTO MEET 2.0 KV PER TEST METHOD 3015,MIL-STD 883• HIGHLY RELIABLE N-WELL CMOSTECHNOLOGY• DESIGNED FOR 10 YEAR DATA RETENTIONAFTER 10000 ERASEIWRITE CYCLE PERWORD• 0 TO + 70°C OPERATING AMBIENTTEMPERATURE RANGE.• -40TO +85°C EXTENDED TEMPERATURERANGEPDIP-8(PlastiC Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONSAO 1 8 ~(+5V)VOOA17 ~6 SCLDESCRIPTIONThe ST24C02 is a 2K EEPROM manufactured inSGS-THOMSON highly reliable CMOS technology.The key features of this device are + 5 volt onlyoperation and inter-integrated circuit bus compatibility.This revolutionnary bus provides the facilitiesof a local area network within a single systemor equipment. Each IC serves as both transmitterand receiver in the synchronous data transfer ofin the bus protocol. Up to eight ST24C02s may becapacitance).Chip select is accomplished by means of the threeaddress inputs Ao, A1 and A2. Each of these inputsmust be connected externally to either + 5Vor GND and each chip is then selected through softwareby placing its 3 bit chip select address on theserial data input the (SDA) at the appropriate timein the bus protocol. Up to eight TS24C02s may beconnected to the serial bus.June 19885 SDA5 -1 0578PIN NAMESAO-A,-A2 CHIP ADDRESS INPUTSVss GROUNDSOA SERIAL DATA/ADDRESS, INPUT/OUTPUTSCL SERIAL CLOCK INPUT, ERASEIWRITEVee + 5V POWER SUPPLY119229

ST24C02BLOCK DIAGRAMseL--~~--~-----'SOA --------,r----'AD Al A2Vee 0--­vsscr--5-10579ABSOLUTE MAXIMUM RATINGSSymbolVOOVITA(I}ISIGIIPower supply voltageCharacteristicVoltage on any input pinAmbient operating temperatureStorage temperature (unpowered and withoutdata retention)Current into any input pin10 Output currentSoldering temperature of leads (10 seconds)Min Typ Max Units-0.3 7 VVSS-0.8 Voo+0.8 V0 +70 °C-65 +150 °C100 i

ST24C02CHARACTERISTICS OF THE 2-WIRE BUSThis bus is intended for communication betweendifferent ICs. It consists of two bidirectional lines:one for data signals (SDA) and one for clock signals(SCL). Both the SDA and the SCL lines mustbe connected to a positive supply voltage via a pullupresistor.The following protocol has been defined:- Data transfer may be initiated only when the busis not busy.- During data transfer, the data line must remainstable whenever the clock line is HIGH. Changesin the data line while the clock line is HIGH willbe i nterpretated as control signals.Accordingly, the following bus conditions havebeen defined:Bus not busy: Both data and clock lines remainHIGH.Start Data Transfer: A change in the state of thedata line, from HIGH to LOW, while the clock isHIGH, defines the START condition.Stop data transfer: A change in the state of the dataline, from LOW to HIGH, while the clock is HIGH,defines the STOP condition.Data valid: The state of the data line representsvalid data when after a start condition, the data lineis stable for the duration of the HIGH period of theclock signal. The data on the line may be changedduring the LOW period of the clock signal. Thereis one clock pulse per bit of data.Each data transfer is initiated with a start conditionand terminated with a stop condition; the numberof the data bytes, transferred between the startand stop conditions is limited to eight bytes in theERASE + WRITE mode and is not limited in theREAD mode. The information is transmitted bytewiseand each receiver acknowledges with a ninthbit.Whithin the bus specifications a low speed mode(2 KHz clock rate) and a high speed mode (100 KHzclock rate) are defined. The ST 24C02 works in bothmodes By definition a device that gives out a messageis called "transmitter", the receiving devicethat gets the message is called "receiver". Thedevice that controls the message is called"master". The devices that are controlled by themaster are called "slaves".Acknowledge: Each byte of eight bits is followedby one acknowledge bit. This acknowledge bit isa low level put on the bus by the receiver whereasthe master generates an extra acknowledge relatedclock pulse.A slave receiver which is addressed is obliged togenerate an acknowledge after the reception ofeach byte. Also a master receiver must generatean acknowledge after the reception of each bytethat has been clocked out of the slave transmitter.The device that acknowledges has to pull down theSDA line during the acknowledge clockpulse insuch a way that the SDA line is stable LOW duringthe high period of the acknowledge related-·clock pulse. Of course, setup and hold times mustbe taken into account. A master receiver must signalan end of data to the slave transmitter by notgenerating an acknowledge on the last byte thathas been clocked out of the slave. In this case thetransmitter must leave the data line HIGH to enablethe master to generate the STOP condition.Figure 1 attached shows the typical manner inwhich the ST24C02 is interfaced to the bus. Forpurposes of illustration chip address, A2A 1 AO = 100is shown. This is only one of eight possible addressessince up to eight ST24C02s can be connectedto the bus of a single system. The erase/write cycletime of this device T EIW is determinated internally.FIG. 1 - TYPICAL INTERFACE+SV1...!.. AO,.1 Al- .2 A2..i Vss_.5-10580vccJ~~SDA~SDAscLJ!L.-3/9231~--~-~-~---~~--" --,-- --.-------------~-~~---- ----------~~-~-.-.-~--. ----------

ST24C02FIG. 2A· DATA TRANSFER SEQUENCE OF THE SERIAL BUSCLOCK~r---' iLL,---,HIGHI' I: :I IIII: IlII: - LOW\ 1 : I: I I : IDATA 1\' / Qgj P-4=HIGHI I I I I II I;__ LOW: I I I I I I __'__I ICHANGE OFt ___START CONDITION I 'DATA ALLOWED STOP CONDITIONDATA LINE STABLEDATA VALIDFIG. 2B . ACKNOWLEDGEMENTCLOCK PULSE FORSTART CONDITIONACKNOWL EDGEMENTSCLK FROMMASTERI ~:I ,IDATA OUTPUT I , ,BY TRANSMITTER ~ 1\/_ DATA 1X·DATA 2XJIIex /'I DATA 8~--~------~--~ ~-------- I I: I--------------il Ir-------\~ _ _'rDATA OUTPUTBY RECEIVER5 - 10582FIG. 2C . BUS TIMING REQUIREMENTSSCL~--~--~--~SDA-~II IL~JS - '1051934/9232

ST24C02ELECTRICAL CHARACTERISTICSStandard conditions (unless otherwise moted)VSS=OV (GND)VCC= +5 ±10% voltsAmbient Operating Temperature (TAl: O°C to+ 70°C (commercial) - 40°C to + 85°C (industrial)Data labeled "typical" is presented for designguidance only and is not guaranteed.SGS-THOMSON makes no warranty, expressed orimplied, as to the merchantability of fitness for aparticular purpose of this device or its software suppliedto the customer.DC ELECTRICAL CHARACTERISTICSSymbol Parameter Test Conditions100RloowMin.ValuesOperating supply currentREAD MODE 1 rnAOperating supply currentWRITE/ERASE Mode 3 rnA1000 Operating supply currentSTANDBY mode (CMOS input) 0.1 mAIlL10HVIHInput leakage current(Ao, At, A2, SCL pins) 10 pAOutput leakage currentHIGH 10 pASCL input and SDAinput/output pins:High level input voltage 3.0 Voo+0.8 VVIL Low level input voltage -0.3 I.S VVOL Low level output voltage 10L = 3mA Voo = 4.SV 0.4 VVIH High level input voltage (Ao, At, A2 pins) Voo-O.S VOO+O.S VVIL Low level input voltage (Ao, At, A2 pins) -0.3 O.S VTyp.Max.UnitS/9233

ST24C02ELECTRICAL CHARACTERISTICSAC CHARACTERISTICSSymbolParameterTest ConditionsValuesMin. Typ. Max.UnitfSCLSCL clock frequency0 100 KHztLOWThe LOW period of the clock4.7 1'5tHIGHtRtFtAAtHD:STAThe HIGH period of the clockSDA and SCL rise timeSDA and SCL fall timeSCL low to SDA data outSTART condition hold time.After this period the firstclock pulse is generated4.0 1'51 1'5300 1'50.3 1.5 3.5 1'54.0 I'stSU:STAtSU:DATtHD:DATTSU:STOtSUFTEJWSetup time for start condition(only relevant for a repeatedstart condition)Data set-up timeData hold timeSTOP condition set-up~Time the bus must be freebefore a new transmissioncan startEraselWrite cycle time(per word)4.7 "s250 ns0 "s4.7 I's4.7 I's10 msNEIWEndurance (number oferase/write cycles)EIW10000 cyclestsData retention time10 YearsCITIInput capacitance on SCL,SDANoise suppresion timeconstant at SCL and SDAinput7 pf0.25 0.5 1.0 "sNotes: 1. All values referred to VIH and VIL levels2. Note that a transmitter must internally provide at least time to bridge the undefined region (max. 300 ns) of the edge of SCl.6/9234

ST24C02INTER INTEGRATED CIRCUIT BUS PROTOCOLThe following is a condensed description of eachmode of operation.Chip address (slave address) allocation: The threechip address inputs of each ST24C02 (A2, A1, Ao)must be externally connected to either + 5V (Vee)or ground (Vss) thereby assigning to eachST24C02 a unique three-bit chip address. Up toeight ST24C02s may be connected to the serialbus. Chip selection is then accomplished thrcughsoftware by setting the least significant three bitsof the slave address to the corresponding hardwiredlogic levels of the selected ST24C02. The correctbus protocol is shown in figure 3.Erase/Write Mode:In this mode the master transmitter transmits to theST24C02 slave receiver. Bus protocol is shown infigure 4. Following the START condition and slaveaddress, a logic 0 (RIW = 0) is placed on the busand indicates to the addressed device that wordaddress An will follow and is to be written to theon-chip address pointer. The data word to be writtento the nonvolatile memory is strobed in next,and is loaded in the data register. Another 7 databytes may be strobed in following this in the dataregister. In the erase/write mode no more than 8successive data bytes may be strobed into theST24C02 (Fig. 4a). The ST24C02 slave receiver willsend an acknowledge bit to the master transmitterafter it has received the slave address and againafter it has received the word address and eachdata byte.After the STOP condition the EraseIWrite cyclestarts. Its duration is at most 10 ms per data byte.After the receipt of each word, the three low orderaddress bits are internally incremented by one. Thehigh order five bits of the word address remainconstant. If the master should transmit more thaneight words prior to generating the stop condition,the address counter will "roll over" and the previouslywritten data will be overwritten. As with the byte write operation, all inputs are disabled until completionof the internal write cycle. Refer to Figure6 for the address, acknowledge and data transfersequence.Read mode:In this mode the master reads the ST24C02 slaveafter setting the slave address. See figure 5. Followingthe write mode control bit (RIW = 0) and theacknowledge bit, the word address An is writtento the on-chip address pointer. Next the STARTcondition and slave address are repeated followedby the READ mode control bit (RIW = 1). At thispoint the master transmitter becomes the masterreceiver. The data byte which was addressed willbe transmitted and the master receiver will sendan acknowledge bit to the slave transmitter. Theaddress pointer is only incremented on receptionof an acknowledge bit. The ST24C02 slave transmitterwill now place the data byte at address An + 1on the bus, the master receiver reads and acknowledgesthe new byte and the address pOinteris incremented to An + 2.This cycle of reading consecutive addresses willcontinue until the master receiver send a STOPcondition to the slave transmitter.An alternate READ mode may also be implementedwhereby the master reads the ST24C02 slavewithout first writing to the (volatile) address pointer.The first address that is read is the last one storedin the pointer. See figure 6.FIG. 3 - SLAVE ADDRESS ALLOCATIONFIG. 4 - BYTE WRITEBUS ACTIVITY:MASTERSDA LINEBUS ACTIVITY:SSI SLAVE TR ADDRESS WORD ADDRESS DATA 0T --- -;::;:::;:::;::;:;:;::;~ ;:;;:¢;:::;:;:::;::;::; pfllil 0.1::::::: II::::::: IffA A II.C C CKKK5-106447/9235

ST24C02FIG. 4A· PAGE WRITEBUS ACTIVITY:MASTERSDA LINEBUS ACTIVITY:'SSI SLAVE TR ADDRESS WORD ADDRESS(n) DATA n DATA n ~ 1 DATA n + 7 gffiJ1 0 !I : : : : : : : II: : : : : : : II : : : :: : : ID~ : : : :: I RA A A A AC C C C CKKK KK5-10633FIG. 5· READ MODEBUS ACTIVITY:MASTERSDA LINEBUS ACTIVITY:SSI SLAVEI, SLAVER ADDRESS WORD ADDRESS" R ADDRESS, DATA" DATA" + 1T- T~~~~;;;;~~~~[llil D! 1::::::: I rsrmo II::::::: II::::::: II ..·AAAACC.CCKKKK'5- 10643ACKSDATAn+X 6p.... I:::::::IBFIG. 6· ALTERNATE READ MODEBUS ACTIVITY:MASTERSDA LINEBUS ACTIVITY:SSI SLAVE , TiI ADDRESS DATA n DATA "+1 DATA n + X gT--~----,~~;;;;~fllilOll::: :::: I """""1::'T'"I""T::A A ' AC C CKKK:-r-T"I:: I[_~~: ___ L:::::: 185-106428/9236

ST24C02ORDERING INFORMATIONPart Number Max Frequency Supply VoltageST24C02CPST24C02VP100 KHz100 KHz5V±10%5V±10%Temp. Range Packageo to + 70°CDIP-8-40 to +85°C DIP-8PACKAGE MECHANICAL DATAa-PIN PLASTIC DIPI4~-!- ~ ,~r- ~ [--II- - ~ 61. 1-1-- W>- i-!--z . z001SL~'~SL, ;-~- 1---, ,U LJILJ UPOO1.FI6m\ I /I- f.hl-EmmInchesDim.Min Typ Max Min Typ MaxA.1 0.70 0.0286 1.39 1.65 0.055 0.06561 0.91 1.04 0.036 0.041b 0.50 0.02bl 0.36 O.SO 0.Q15 0.020c0 9.80 0.36601E 6.9Q 0.350e 2.54 0.100,3 7.62 0.300e4F 7.10 0.260I 4.80 0.189L 3.30 0.130NZ 0.44 1.60 0.017 0.0639/9237----..-~---...- ..

TS59C111 K BIT SERIAL CMOS EEPROM• HIGHLY RELIABLE CMOS FLOATING GATETECHNOLOGY.• SINGLE 5-VOL T SUPPLY• EIGHT PIN PACKAGE.• 64x16 OR 12S.xS USER SELECTABLESERIAL MEMORY• COMPATIBLE WITH GENERALINSTRUMENT GI 5911• SELF TIMED PROGRAMMING CYCLE• WORD AND CHIP ERASABLE• 10,000 ERASEIWRITE CYCLES.• TEN YEARS DATA RETENTION• POWER-ON DATA PROTECTIONPDIP-8(Plastic Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONSPIN NAMESCSClKDIDOORGR/BVeeGNDCHIP SELECTCLOCK INPUTSERIAL DATA INPUTSERIAL DATA OUTPUTORGANIZATION INPUTREADY/BUSY OUTPUT+ 5V POWER SUPPLYGROUND....----......rcs 1 8~(.~)~CelK 2 7 ~ ROY/ii"Us"Y01 36~ORGDO 4S -106535 ~GNOPIN DESCRIPTIONNameNoCS 1 Chip SelectClK 2 Clock InputDI 3 Serial Data InputDO 4 Serial Data OutputGND 5 GroundDescriptionORG 6 Memory Array Organization Selection Input. When the ORG pin is connected to + 5, the64 x 16 organization is selected. When it is connected to ground, the 128 x 8 organizationis selected. If the ORG pin is left unconnected, then an internal pull up device will selectthe 64 x 16 organization.RDY/BUSY 7 Status OutputVee 8 + 5V Power SupplyJune 1988 1/8239

TS59C11BLOCK DIAGRAMVeeGNODO01L..l!~~j:=======---_ROVfBUSVeLKINSTRUCTION SETInstruction Start bit OpcodeAddressData128x8 64x16 128x8 64x 16CommentsREAD 1 1000 A6-AO As-Ao Read Address AwAoPROGRAM 1 x 100 A6-AO As-Ao DrDo D1S-Do Program Address AN-AOPEN 1 0011 0000000 000000 Program EnablePDS 1 0000 0000000 000000 Program DisableERAL 1 0010 0000000 000000 Erase All AddressesWRAL 1 0001 0000000 000000 DrDo D15-Do Program All Addresses01100: It is possible to connect the Data In andData Out pins together. However. with this configurationit si possible for a "bus conflict" to occurduring the "dummy zero" that precedes the readoperation, if AD is a logic high level. Under sucha condition the voltage level seen at Data Out isundefined and will depend upon the relative impedancesof Data Out and the signal source drivingAD. The higher the current sourcing capabilityof AD. the higher the voltage at the Data Out pin.POWER-ON DATA PROTECTION CIRCUITRY:During power-up all modes of operation are inhibiteduntil Vee has reached a level of between 2.8and 3.5 volts. During power-down the source dataprotection circuitry acts to inhibit all modes whenVee has fallen below the voltage range of 2.8 to3.5 volts.ABSOLUTE MAXIMUM RATINGSSymbolVceTSTGSupply voltageVoltage on any input pinParameterValueUnit+7 VGND -0.3 to + 7Voltage or any output pinVee +0.3VGND-0.3Storage temperature range-65 to + 150Lead temperature (Soldering: 10 seconds) +300·e·eV2/8240

TS59C11READ OPERATIONDC CHARACTERISTICSTamb=OoC to 70°C for CP, Tamb= -40 to +85°C for VP, VCC= 5V±100f0 (Unless otherwise specified)Symbol Parameter Test ConditionsValuesMin. Typ. Max.Vcc Operating voltage 4.5 5.5 VICCl Operating current Vcc=5.5V, CS=VIHCP range 4 rnAVP range 4ICC2 Standby current . Vcc=5.5V, CS=DI~SK=GND+0.1V) 100 ,.AVIL Input low voltage -0.1 0.8 VVIH Input high voltage 2.0 Vcc+ 1 VVOL Output low voltage IOL=2.1mA 0.4 VVOH Output high voltage IOH= -400~ 2.4 VILl Input leakage current Vin= 5.5V 10 ,.AILO Output leakage current Vout =5.5V, CS=O 10 ,.AUnitAC CHARACTERISTICS(Tamb= 0° to 70°C for CP, Tamb= -40 to+85°C for VP, VCC=5V±100f0 (Unless otherwise specified)Symbol Parameter Test ConditionsValuesMin. Typ. Max.SK max (Maximum frequency) 250 KHzSK duty cycle 25 50 75 %Tcss CS setup time 0.2 fLSTCSH CS hold time 0 fLsTOIS 01 Setup time 0.4 fLsTOIH Data input hold time 0.4 fLsTcpw ClK pulse width 2.0 fLsTpOl Data output delay Cl=100pF, VOL=0.8V,, VOH=2.0Vand 2.0 fLSTpoo VIH=2.4V, VIL=O.45V 2.0tpR Status low time 10 ms(programming time)Unit318241

TS59C11FIG. 1 • SYNCHRONOUS DATA TIMINGSClK01CSDO----~Io-IS~~SK max.. '1111 1~~i------;.::+J 1 1, 1 " 1 '~~~, ,10IH' 1 i~ICSH.1ro=-t ' ,I ,1 1 ' I---I:' :: '--~ICSS15- 106321 /:lp01 :-1 1FIG. 2 • READ MODE_------------------!I~I -------1(1-1 -------_(~!l_fL_,____ 0 ___ 0 ~:JG"\~----!l 'r-',______------------------~I~~S -10629418242

TS59C11The READ instruction is the only i~truction whichoutputs serial data on the DO pin. After a READisntruction is received, the instruction and addressare decoded, followed by data transfer from thememory register into a serial-out shift register. Adummy bit (logical "0") precedes the data outputstring. The output data changes during the highstates of the system clock.Organization128x864x 16ANONAs 07As 015FIG. 3 - PROGRAM MODECS-Ir--------------------~;~I------~!~I--~~~~mrn~~-------CLK01ROV/BUSY--------------------5-_'-06-3\----~:~7--------~!~p::rThe PROGRAM instruction is followed by eithereight or sixteen bits of data, which are to be writteninto the specified address.After the last data bit (DO) has been shifted intothe data register the contents of the specified addresswill be erased and the new data written tothe same address.Durin~ automatic erase/write. sequence theROY/BUSY output will go low for the duration ofthe automatic programming cycle as indicated bytp.During a program cycle the internal erase and writeoperations occur automatically and are self-timedon the device. A single memory location may alsobe erased by programming that address with all"1 's".Organization AN ON128x8 A6 0 764x 16 As 0155/8243

TS59C11FIG. 4 - PEN (Program enable) AND PDS (Program D!sab_le_) __________..,.-____--,CS ..JClK01______ J~~o ____ o~/~ ____ ~\~o ____ o ____ o ___ o ____ o ____ o __________5 ~ 10630PEN and PDS for 12BxB organizationCSJClK01ENABLE = 11OISABlE=OO______ J~~o ___ o __/~~._____\~_o__o ____ o ___ o __ o ___ o ____ o _____5-10640PEN and PDS for 64x16 organizationProgramming must be preceded once by aprogramming enable (PEN) instruction. Programmingremains enabled until a programming disable(PDS) instruction is executed.The programming disable instruction is providedto protect against accidental data disturb. Executionof a READ instruction is independent of bothPEN and PDS instructions.FIG. sa - ERAL (Erase all) MODE for 128x8 Organizationc~r--------------i! 1-1 ------.,; +-j --...'WOOO6&lIQ0("""

TS59C11FIG. 5b - ERAL (Erase all) MODE for 64 x 16 Organizationes-fr----------------------~:~!------~!~!--~~~~~~r---------elKOt ~o ori"\o ~~--------------------;~ , ~~RDY'Bi::iSV----------~:'~~!~,PJ5-10639 C:---lEntire chip erasing is provided for ease of clearingthe whole memory and is implemented with theERAL (erase all registers) instruction.Erasing the chip means that all registers in thememory array have each bit set to a 1.FIG. 6 - WRAL MODEes-fr------------------------!) !-!----I! !-!---nWtl:llNl'li::l""'"'":n"V''''''''rrT---------elKOtThe WRAL instruction is followed by either eight orsixteen bits of data. After the last data bit (Do) hasbeen shifted into the data register the contents ofall adresses will be erased an the new data writtento all adresses. The pre-erasing and writing of newdata occur automatically and are self-timed on-chip.During the automatic erase/write sequence theRDY/DUSY output will low for the duration of theautomatic programming cycle as indicated by tp.Organization AN-AO ON128x8 0000000 D764x 16 000000 D157/8245

TS59C11ORDERING INFORMATIONPart Number Max Frequency Supply VoltageTS59C11CPTS59C11VP250 KHz 5V±10%250 KHz 5V±10%Temp. Range Packageo to + 70°CDIP·8-40 to +85°C DIP·8PACKAGE MECHANICAL DATAa-PIN PLASTIC DIP1--'I\.L ~ ,I I II-I~- - f-e-- B1. I-- 1-"..1>- ~Z e ZDDI..n...Jl_',n.,n_,5-~- --c--1 4l.J UIU l.JPOO1-F/6P.rmIEII-..J>LmmInchesDim.Min Typ Max Min Typ MaxAa1 0.70 0.028B 1.39 1.65 0.055 0.065B1 0.91 1.04 0.036 0.041b 0.50 0.02b1 0.38 0.50 0.Q15 0.020cD 9.60 0.386D1E 8.90 0.350e 2.54 0.100e3 7.62 0.300e4F 7.10 0.280I 4.60 0.189l 3.30 0.130Nz 0.44 1.60 0.017 0.0638/8246

~ SGS-1HOMSONIt.. ~ L [j\I'A]O©OO@~OJ~©'iJ'OO@~O©~TS93C461 K BIT SERIAL CMOS EEPROM• HIGHLY RELIABLE CMOS FLOATING GATETECHNOLOGY.• SINGLE 5-VOL T SUPPLY• EIGHT PIN PACKAGE.• 64 x 16 OR 128 x 8 USER SELECTABLESERIAL MEMORY• COMPATIBLE WITH NATIONALSEMICONDUCTOR NMC 9346 and NMC 9306• SELF TIMED PROGRAMMING CYCLE.• WORD AND CHIP ERASABLE• 10,060 ERASEIWRITE CYCLES.• TEN YEARS DATA RETENTION• POWER-ON DATA PROTECTIONPDIP-8(Plastic Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONSPIN NAMESCSCHIP SELECTSKCLOCK INPUT01 SERIAL DATA INPUTDOSERIAL DATA OUTPUTORGORGANIZATION INPUTVee+ 5V POWER SUPPLYGNDGROUNDNCNO CONNECTCS 18 ~ VeeSK 2 7 ~NC01 36~ ORG00 14 5 ~ GNO5 10637PIN DESCRIPTIONNameNoCS 1 Chip SelectSK 2 Clock Input01 3 Serial Data InputDO 4 Serial Data OutputGND 5 GroundDescriptionORG 6 Memory Array Organization Selection Input. When the ORG pin is connected to '+ 5, the64 x 16 organization is selected. When it is connected to ground, the 128 x 8 organizationis selected. If the ORGpin is left unconnected, then an internal pull up device will selectthe 64 x 16 organization.Vee 8 + 5V Power SupplyJune 1988 117247

TS93C46BLOCK DIAGRAMVccGNOORGDO01CSSKINSTRUCTION SETAddressDataInstruction Start bit Opcode128x8 64x16 128x8 64x16CommentsREAD 1 10 As-Ao As-Ao Read Address AwAOERASE 1 11 As-Ao As-Ao Erase Address AN-AOWRITE" 1 01 As-Ao As-Ao D7"DO D15"DO Write Address AwAoEWEN 1 00 llxxxxx llxxxx Program EnableEWDS 1 00 OOxxxxx OOxxxx Program DisableERAL 1 00 10xxxxx 10xxxx Erase All AddressesWRAL 1 00 01xxxxx 01xxxx D7"DO DIS-Do Program All Addresses• Write instruction is a self timed program instruction. The selected byte (word) gets erased before being written.01100: It is possible to connect the Data In andData Out pins together. However, with this configurationit si possible for a "bus conflict" to occurduring the "dummy zero" that precedes the readoperation, if Ao is a logic high level. Under sucha condition the voltage level seen at Data Out isundefined and will depend upon the relative impedancesof Data Out and the signal source drivingAo. The higher the current sourcing capabilityof Ao, the higher the voltage at the Data Out pin.POWER-ON DATA PROTECTION CIRCUITRY:During power-up all modes of operation are inhibiteduntil Vee has reached a level of between 2.8and 3.5 volts. During power-down the source dataprotection circuitry acts to inhibit all modes whenVee has fallen below the voltage range of 2.8 to3.5 volts.ABSOLUTE MAXIMUM RATINGSSymbolParameterValueUnitVee Supply voltageVoltage on any input pinVoltage or any output pin+7GNO -0.3 to + 7Vee +0.3VVVGND -0.3TSTG Storage temperature range-65 to + 150 °eLead temperature (Soldering: 10 seconds) . +300 °e217248

TS93C46READ OPERATIONDC CHARACTERISTICS(Tamb = 0° to 70°C for CP, T amb = - 40 to + 85°C for VP, Vee = 5V ± 1 0%; Unless otherwise specified)Symbol Psrsmeter Test ConditionsValuesMin. Typ. Max.Vcc Operating voltage 4.5 5.5 VICCl Operating current Vcc=5.5V. eS=VIHep range 4 mAVP range 4ICC2 Standby current Vcc=5.5V, es=ol=. SK:GNO+0.1V) 100 p.AVIL Input low voltage -0.1 0.8 VVIH Input high voltage 2.0 Vcc+ 1 VVOL Output low voltage IOL=2.1mA 0.4 VVOH Output high voltage IOH = - 400,.A • 2.4 VILl Input leakage current Vin=5.5V 10 ,.AILO Output leakage current Vout =5.5V. es=o 10 ,.AUnitAC ELECTRICAL CHARACTERISTICS(Tamb=Oo to 70°C for CP Tamb= -40 to+85°C for VP, Vee=5V±10%; Unless otherwise specified)Symbol Parameter Test ConditionsValuesMin. Typ. Max.SK max (Maximum frequency) 250 KHzSK duty cycle 25 50 .. 75 %Tcss es setup time 0.2 ,.sTCSH es hold time 0 ,.sTDiS 01 Setup time 0.4 ,.sTOIH Data input hold time 0.4 ,.sTpOl Data output delay CL=100pF, VOL=0.8V,VOH=2.0Vand 2.0 ,.sTpoo VIH=2.4V, VIL=O.45V 2.0THZ Output delay to Hi Z 0.4 ,.sTE/W EraseiWrlte pulse width 10 msTcs Min. CS low time 1 ,.sTSKHI SK high time 1 ,.sTSKLOW SK low time 1 ,.sTsv Output delay to status valid 1 ,.sUnit317249

TS93C46DEVICE OPERATIONthe TS93C46 is a serial Eeprom memory featuringa software programmable organization:. 128 x 8bit or 64 x 16 bit. It has 7 instructions that allow itto read, erase or write.Each instruction consists of a start bit (logical "1"),an opcode field (2 bits), an address field (6 or 7 bits)and optionaly a data field (8 or 16 bits) - Addressand data fields length depending on organizationx8 or x 16.The DO pin is a multiplexed pin. It is used as dataout during the read mode. It can also be used asa ready/busy indicator in programming mode. Inall other modes, DO is tri-stated.During power-up, all modes of operation are disabled,and the device comes up in a programdisabledstate. An EWEN instruction has to be issuedbefore starting programming.READThe READ instruction reads the content of the addressedregister. It outputs data serially on the DOpin. After the instruction is decoded, a dummy bit(logical "0") precedes the output data string.ERASEIWRITE ENABLE AND DISABLEAfter power-up and before starting any programminginstruction, the EWEN instruction has to beissued. Once it has been issued, it will remain activeuntil an EWDS instruction takes place. TheEWDS instruction is provided to avoid any accidentalprogramming of the part. The read instructionis independent from the EWEN and EWDS instructions.ERASEAfter an ERASE instruction has been shifted in, CSis dropped low. This will set the beginning of theself timed erase sequence. If CS is then broughthigh (after observing TCS spec), the DO pin willact as a status indicator. It will remain low as longas the chip is programming. It willgo high after allthe bits of the addressed regi.ster have been setto al logical "1".WRITEAfter a WRITE instruction has been shifted in withthe corresponding 8 bits or 16 bits of data, CS isdropped low. This will set the beginning of the selftimed programming cycle. The addressed registerwill first be automatically erased and then the previouslyshifted data will be written in the register. IfCS is brought high during the programming time(after observing the rCS spec), theDO pin will actas a status indicator-it will remain Iowa long as thechip is programming. It will go high after all the bitsof the addressed register have been set to theproper value.ERASE ALLThis instruction is provided to erase the whole chip.It works the same way as the erase instruction does.WRITE ALLThis instruction is provided to write simultaneouslyall the registers. All the registers must be erasedbefore doing a WRAL operation. The WRAL instructionworks the same way as the write instructiondoes.SYNCHRONOUS TIMINGS5K01C5DOIPOO~~ ________________ --J ~~ ______________ __s - 106514/7250

TS93C46INSTRUCTION TIMINGSREADSK ~u--u-u-u-l.;n.rut.JLJL..JLJI~CS I(j~---~'~01 ~~------Jr-------J!;I-'DO+1-----tHZ__ ~rR~I~-S~r~Ar~E~ __________ ~~~CSI~--------------------~"WRITEDOTRI-STATESKEWENEWDSCS I''\, STANDBYo I )( If'u/I/////IIIlffIJ/ltIl!A( L' _____________ __ENABLE =11 ;-DISABLE =005 -'06545/7251

TS93C46INSTRUCTION TIMINGS (Continued)CS/r------------------~J~CHECK STATUSSTANDBVERASEDO./,...!T~RI""-S::cTA~T~E________...,' I-----iSKERALCSCHECK STATUS STANDBVDOTRI-STATESKt 5CS J CHECK STATUS STANDBVWRAL01 ON DODOTRI-STATE5-106556/7252

~TS93C46ORDERING INFORMATIONPart Number Max Frequency Supply VoltageTS93C46CPTS93C46VP250 KHz 5V±10%250 KHz 5V±10%Temp. Range Packageo to + 70°CDIP·S-40 to +S5°C DIP·SPACKAGE MECHANICAL DATAa-PIN PLASTIC DIP/- ..I-I~lI,L n.c=I I-IJl.1- BI,.-- ~ii.J>. ., z0OJ...fL~'IL...fL,5- ~- f--- -, ,U LJILJ UPOO1·F/6~m\ I II-- ..lU-EmminchesDim.Min Typ Max Min Typ MaxA.1 0.70 0.0288 1.39 1.65 0.055 0.06581 0.91 1.04 0.036 0.041b 0.50 0.02bl 0.38 0.50 0.015 0.020c0 9.80 0.38601E 8.90 0.350e 2.54 0.100,3 7.62 0.300.4F 7.10 0.280I 4.80 0.189l 3.30 0.130NZ 0.44 1.60 0.017 0.063717253

ST93C562K BIT (128 x 16) SERIAL CMOS EEPROMADVANCE DATA• 128 x 16 SERIAL EEPROM• SINGLE POWER SUPPLY =FROM 2.7 TO 5.5. VOLTS• 10 YEAR DATA RETENTION AFTER 100.000ERASEIWRITE CYCLES PER WORD• CMOS LOW POWER CONSUMPTION =3 MA MAX ACTIVE CURRENT AND 0.1 MAMAX STANDBY CURRENT• 4 BYTE WRITE MODE• SELF TIMED PROGRAMMING CYCLE (WITHAUTOERASE)• WRITE PROTECTION IN USER DEFINED SEC­TION OF MEMORY• SEQUENTIAL REGISTER READPMDIP-8S014(Plastic)(Plastic Micropackage)(Ordering Information at the end of the datasheet)PIN CONNECTIO~SCSSKDESCRIPTIONThe ST93C56 is a 2048 bit non-volatile sequentialaccess memory manufactured using SGS­THOMSON Single Floating Gate process.It is designed to operate from 3 to 5 Volts in orderto match telecommunications requirements.Moreover, a double cell per bit architecture will allowto guarantee 100K erase/write cycles.01DONCPIN NAMESCSSKDIDOGNDPEPREVeeNCCHIP SELECTSERIAL DATA CLOCKSERIAL DATA INPUTSERIAL DATA OUTPUTGROUNDPROGRAM ENABLEPROTECT REGISTER ENABLEPOWER SUPPLYNO CONNECTCSSKNC0100NC5-10641June 19881/2This is advance information on a new product now in davelopment or undergoing evaluation. Details are subject to change w~hout notice.255

ST93C56BLOCK DIAGRAMPROTECTREGISTER01DOCSSKOSCILLATORCHARGE PUMPPREPEs- 10645212256

ROM DEVICES257

M2316H16K-BIT READ ONLY MEMORY• SINGLE+5V ±10% POWER SUPPLY• ACCESS TIME 300 ns (MAX)• COMPLETELY STATIC OPERATION• INPUTS AND OUTPUTS TTL COMPATIBLE• THREE PROGRAMMABLE CHIP SELECTSFOR SIMPLE MEMORY EXPANSION ANDSYSTEM INTERFACE• THREE STATE OUTPUTS FOR DIRECT BUSINTERFACE• EPROMs ACCEPTED AS PROGRAM DATAINPUTSBDIP-24(Plastic Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe M2316H is a 16,384-bit static Read Only Memoryorganized as 2,048 by 8 bits.It is manufactured using SGS-THOMSON' highdensity N-channel Si-Gate MOS process and isideal for non volatile data storage applications suchas program storage. The three-state outputs andTTL input/output levels allow for direct interfacewith common system bus structures.The M2316H is available in 24-lead dual in line plasticor ceramic packages.A7vccASA8A5A9A4CS3/CS3A3CS1/CSIA2Al0AtCS2/C52AO 07DO 0601 0502 04GNo 03PIN NAMESAO-A1ODO-D7CS1-CS3ADDRESS INPUTSDATA OUTPUTSCHIP SELECT INPUTSJune 19881/4259

M2316HBLOCK DIAGRAMD0D102D3~05D6D7Al0A9A8A7A6A5A4A3A2::l!"16.384 BITCElL MATRIXCSICS2AIAOCS35-2319ABSOLUTE MAXIMUM RATINGSSymbolParameterVI Voltage on any pin with respect to groundPtot Total power dissipationTstg Storage temperature: ceramic packageplastic packageTop Operating temperatureValueUnit- 0.5 to + 7 V1 W-65 to + 150-55 to +125°C°C0 to + 70 °CStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.WAVEFORMS2/4260

M2316HSTATIC ELECTRICAL CHARACTERISTICS (Tamb=OoC to + 70°C, Vee=5V± 10% unless otherwisespecified)ValuesSymbol Parameter Test ConditionsMin. Typ. Max.UnitVOH Output High Voltage Vee=4.5V, IOH= -400 p.A 2.4 Vee VILO Output Leakage Current Chip deselectedVOUT=OV to Vee10 p.AVIL Input Low Voltage See Note 1 -0.5 O.B VVIH Input High Voltage 2.0 Vee VVOL Output Low Voltage Vee = 4.5V IOL=2.1 mA 0.4 VIII Input Load Current Vee=5.5V,OV';;VIN.;;5.5V 10 VIcc Power Supply Current Output unloaded, Chip enabledVee=5.5V, VINrVeeNote 1: Input levels that swing more negative than - O.SV will be clamped and may cause damage to the device.40 70 mADYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = O°C to + 70°C, VCC = 5V ± 10% unless otherwisespecified)Symbol Parameter Test ConditionsValuesMin Typ. MaxtAee Address Access Time Output load: 1 TTL load and 300 nsChip Select Delay100 pf100 nsteotOF Chip Deselect Delay Input transition time: 20 ns 100 nstOH Previous Data Valid After Timing reference levels: 10 nsAddress Change Delay Input: 1.5VOutput: O.BV and 2.0VUnitCAPACITANCE (Tamb=25°C, f= 1 MHz, see Note 2)Symbol Parameter Test Conditions Min. Typ. Max. UnitCIN Input Capacitance All pins except pin 7 pFunder test tied toCOUT Output Capacitance AC ground 10 pFNote 2: This parameter is sampled periodically and is not 100% tested.3/4261

M2316HORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageM2316HB1300ns5V±10%O· to + 70·CDIP·24PACKAGE MECHANICAL DATA24·PIN PLASTIC DIP24 ::>: ! 13-~--+----PO.3-N6i 12mmI. .1Dim.MinmmTypAa 1 0.63B 0.45b 1 0.23b 2 1.27CDE 15.20e 2.54e3 27.94e4FI 4.45L 3.30KlK2InchesMax Min Typ Max0.0240.0170.31 0.009 0.0120.05032.20 1.26716.68 0.598 0.6560.1001.10014.10 0.5550.1750.1294/4262

M2332M233332K-BIT READ ONLY MEMORY• M2332-2532 EPROM PIN COMPATIBLE• M2333-2732 EPROM PIN COMPATIBLE• SINGLE + 5V ± 10% POWER SUPPLY• ACCESS TIME 250ns (MAX)• COMPLETELY STATIC OPERATION• INPUTS AND OUTPUTS TTL COMPATIBLE• TWO PROGRAMMABLE CHIP SELECTS FORSIMPLE MEMORY EXPANSION ANDSYSTEM INTERFACE• 2716/253212732 EPROMs ACCEPTED ASPROGRAM DATA INPUTS.• THREE-STATE OUTPUTS FOR DIRECT BUSINTERFACEBDIP-24(Plastic Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe M2332 and M2333 are 32,768-bit static ReadOnly Memories organized as 4,096 by 8 bits. Theyare manufactured using our high density N-channelSi-Gate MOS process and are ideal for large, nonvolatiledata storage applications such as programstorage.The three-state outputs and TTL input/output levelsallow for direct interface with common systembus structures.The M2332 and M2333 are available in 24-leaddual-in-line plastic or ceramic packages..7M233223 A822 A921 CS21 CS21 D,C.ll:) CSlI ill! D.C.19 Al018 A1l11 0716 0615 0514 0413 03S""4892n2322 A921 A11;)IN NAMES!JI\JAQ-A11 ADDRESS INPUT00.07 DATA OUTPUTCS1·CS2 CHIP SELECT INPUTSAl 7AO 800 901 1002 11M233318 ,CS2IffiJo.c.VcePOWER SUPPLYGNO 12GNDGROUNDJune 19881/4263

M2332/M2333BLOCK DIAGRAMAO ..AlA2AJA4ASB::i0~A6 ~"Vee GNOi 1000102OJ04OS0607ABSOLUTE MAXIMUM RATINGSSymbolVIPtotTstgTapParameterVoltages on any pin with respect to groundTotal power dissipationStorage temperature: for ceramic packagefor plastic packageOperatirig temperatureValue- 0.5 to + 71-65 to +150-55 to + 1250 to + 70Stresses above those listed under "Absollite Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those Indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may. affect device reliability.UnitVWDCDCDCWAVEFORMSADDRESSINPUTSCHIPSELECTINPUTSDATAOUTPUTSHIGHIMPEDENCEHIGHIMPEDANCES-4895214264

M2332/M2333DC AND OPERATING CHARACTERISTICS (Tamb = O°C to + 70°C, Vee = 5V ± 10% unless otherwisespecified)ValuesSymbol Parameter Test ConditionsMin. Typ. Max.UnitIII Input Load Current Vee=5.5V,OV

M2332/M2333ORDERING INFORMATIONPart NumberM2332B1M2333B1Access Time250250Supply Voltage5V±10%5V±10%Temp. Range0° to + 70 0 e0° to + 70 0 ePackageDlp·24Dlp·24PACKAGE MECHANICAL DATA24-PIN PLASTIC DIPP043-A/61311mminchesDim.Min Typ Max Min Typ MaxAa I 0.630.024B 0.450.017b I 0.23 0.31 0.009 0.012b 2 1.270.050CD32.20 1.267E 15.20 16.68 0.598 0.656, 2.540.100e3 27.941.100,4F14.10 0.555I 4.45 0.175L 3.30 0.129KIK24/4266

~ SGS-11I0MSONA., L ~D©[Ri@~[lJ~©'[]'[Ri@[i\'!]D©~M236464K-BIT READ ONLY MEMORY• ACCESS TIME 250 ns (MAX)• COMPLETELY STATIC OPERATION• SINGLE +5V ±10% POWER SUPPLY• 8192x8 BIT ORGANISATION• INPUTS AND OUTPUTS TIL COMPATIBLE• PROGRAMMABLE CHIP SELECT• THREE-STATE OUTPUTS FOR DIRECT BUSINTERFACE• EPROMs ACCEPTED AS PROGRAM DATAINPUTSfIliP ,,',',"",,\,,~'i>t\\" '. "241BDIP-24(Plastic Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe M2364 is a 65,536-bit static Read Only Memoryorganized as 8,192 by 8 bits.It is manufactured using our high density N-channelSi-gate MOS process and is ideal for non-volatiledata storage a.pplications where high performance,large bit storage and simple interfacing are importantdesign considerations.The M2364 is available in 24-lead dual in-line plasticor ceramic package.A7veeA6A8ASA9A4A3eSfcsfD.e.A2A1AO 07060102PIN NAMESAO-A12 ADDRESS INPUTS00-07 DATA OUTPUTSCStCS-DC CHIP SELECT INPUTVCCPOWER SUPPLYGNDGROUNDJune 19881t4267

M2364BLOCK DIAGRAMVeeOND1 rAO 00AI 01A2 02A365536 BITROM03A. CELL ARRAV O.ASA. O.A12 07OsCSA7 A8 A9 A10 All s- 535511ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVI Voltages on any pin with respect to Ground +0.5 to - 7 VPtot Total power dissipation 1 WTstg Storage temperature: ceramic package -65 to +150 °cplastic package -55 to +125 °cTop Operating temperature o to + 70 DCStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.WAFEFORMSADDRESSINPUTSCHIPSELECTINPUTSDATAOUTPUTSHIGHIMPEDENCEHIGHIMPEDANCE5-48952/4268

M2364DC AND OPERATING CHARACTERISTICS (Tamb=O°C to + 70°C, VCC=5V ± 10% unless otherwisespecified)Symbol Parameter Test ConditionsIII Input Load Current Vcc=5.5V,OV";;'VIN,,;;,5.5VILO Output Leakage Current Chip deselectedVOUT=OV to VCCValuesMin. Typ. Max.Unit10 ~10 ~VIL Input Low Voltage See note 1 -0.5 0.8 VVIH Input High Voltage 2.0 Vee VVOL Output Low Voltage IOL=2.1 rnA 0.4 VVcc=4.5VVOH Output High Voltage IOH= -400 p.A 2.4 Vee VVcc=4.5VIce Power Supply Current Output unloaded, Chipenabled Vcc=5.5V,VIN=Vec 80 rnANote 1: Input levels that swing more negative than - O.SV will be clamped and may cause damage to the device.AC CHARACTERISTICSSymbolParameterTestM2364Conditions Min MaxtAce Address Access Time Output load: 1 TTL load 250 nsand 100 pFtco Chip Select Delay 100 nstOF Chip Deselect Delay Input transition time:20 ns 100 nstOH Previous Data Valid After Address Timing reference levels: 10 nsChange DelayInput: 1.5 VOutput: O.SV and 2.0VUnitCAPACITANCE (Tamb=25°C, f=1 MHz, see Note 2))Symbol Parameter Test Conditions Min. Typ. Max. UnitCIN Input CapaCitance All pins except pin7 pFunder test tied to ACgroundCOUT Output Capacitance10 pFNole 2: This parameter is sampled periodically and is not 100%, tested.3/4269.._--.----- .--..-~.-------------- ....' ---_._. ~~~-~

M2364ORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageM236481250n55V±100f00° to + 70°C DIP-24PACKAGE MECHANICAL DATA24-PIN PLASTIC DIP24P043·Al6"I,4Fc,ITi ~l-EDim.mminchesMin Typ Max Min Typ MaxAa 1 0.63 0.024B 0.45 0.017b 1 0.23 0.31 0.009 0.012b 2 1.27 0.050CD 32.20 1.267E 15.20 16.66 0.598 0.656, 2.54 0.100,3 27.94 1.100e4F 14.10 0.555I 4.45 0.175L 3.30 0.129KIK24/4270

M236564K-BIT READ ONLY MEMORY• PIN COMPATIBLE WITH M2764• ACCESS TIME 250 ns (MAX)• COMPLETELY STATIC OPERATION• SINGLE +5V±10% POWER SUPPLY• 8192x8 BIT ORGANISATION• INPUTS AND OUTPUTS TTL COMPATIBLE• PROGRAMMABLE CHIP SELECT• THREE-STATE OUTPUTS FOR DIRECT BUSINTERFACE• EPROMs ACCEPTED AS PROGRAM DATAINPUTSBDIP-28(Plastic Package)(Ordering Information at the end of the datasheet)PIN CONNECTIONSDESCRIPTIONThe M2365 is a 65,536-bit static Read Only Memoryorganized as 8,192 by 8 bits. It is manufactureduSi,ng our high density N-channel Si-gate MOS processand is ideal for non-volatile data storage applicationswhere high performance, large bitstorage and simple interfacing are important designconsiderations.The M2365 available in 28-lead dual in-line plasticor ceramic package.NCAI2A7A6ASA4A3A2~VCC27 CSI/CSI/NC26 CS2ICsZ/NC25 AS2' A923 All22 CS3/Csl/NC21 AIOPIN NAMESAO-A12CS1-CS4NCADDRESS INPUTCHIP SELECT INPUTSNO CONNECTIONAIAO 1000 1101 1202 13GNO "20 CS4/CS41 NC19 0718 0617 0516 0415 035-679300-07 DATA OUTPUTVeeGNDPOWER SUPPLYGROUNDJune 1988114271

M2365BLOCK DIAGRAMAOA1~VeeGND! rA2 is 0265536 8fT'3 aROM03A. D CELL ARRAY O.A'~OSA6 ~ 06A12 :? 0700cs (1t04)• 7••A9 AlO All 5·679411ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVI Voltages on any pin with respect to ground - 0.5 to + 7 VPtot Total power dissipation 1 WTstg Storage temperature: ceramic package -65 to + 150 ·Cplastic package -55 to + 125 ·CTop Operating temperature 0 to + 70 ·CStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.WAVEFORMSADDRESSINPUTSCHIPSELECTINPUTSDATAOUTPUTSHIGHIMPEDENCEHIGHIMPEDANCE5-108952/4272

M2365DC AND OPERATING CHARACTERISTICS (Tamb=O°C to + 70°C, Vee =5V± 10% unless otherwisespecified)Symbol Parameter Test ConditionsValuesMin. Typ. Max.III Input Load Current Vee=S.SV,OV";VIN";S.SV 10 pAILO Output Leakage Current Chip deselectedVOUT=OV to Veelee Power Supply Current Output unloaded, Chip enabledVee=S.SV, VIN=VeeUnit10 pA70 mAVIL Input Low Voltage See Note 1 -O.S 0.8 VVIH Input High Voltage 2.0 Vee VVOL Output Low Voltage Vee = 4.SV IOL=2.1 mA 0.4 VVOH Output High Voltage Vee=4.SV IOH= -400".A 2.4 Vee VNote 1: Input levels that swing more negative than - 0.5V will be clamped and may cause damage to the device.AC CHARACTERISTICSSymbolParameterTestM2365Conditions Min Typ. MaxtAee Address Access Time Output load: 1 TTL load and 2S0 nsteo Chip Select Delay100 pi100 nstOF Chip Deselect Delay Input transition time: 20 ns 100 nstOH Previous Data Valid After Timing reference levels: 10 nsAddress Change Delay Input: l.SVOutput: 0.8V and 2.0VUnitCAPACITANCE (Tamb = 25°C, f = 1 MHz, see Note 2)Symbol Parameter Test Conditions Min. Typ. Max. UnitCIN Input Capacitance All pins except pin 7 pFunder test tied toCOUT Output Capacitance AC ground 10, pFNote 2: This parameter is sampled periodically and is not 100% tested.3/4273

M2365ORDERING INFORMATIONPart NumberAccess TimeSupply VoltageTemp. RangePackageM23.65B1250n85V=10%O· to + 70·C DIP-28PACKAGE MECHANICAL DATA28-PIN PLASTIC DIP"FC-,TE~Dim.mmInc""Min Typ Max Min Typ IIuAa 1 0.63 0.025B 0.45 0.Q18I-- b 1 0.23 0.31 0.009 0.012b2 127 0.050C0 37.34 1.470E 15.20 16.88 0.598 0.657e 2.54 0.100e3 33.02 1.300e4F 14.10 0.555I 4.45 0.175L 3.30 0.130KIK24/4274

STATIC RAM DEVICES275

t== SGS-THOMSON.., L [R'A]o©oo@rn[brn©'U'~@~o©~MK48Z02/12(B)·12/15120/252K x 8 ZEROPOWERTM RAM• PREDICTED WORST CASE BATTERY LIFE OF11 YEARS @ ?OoC• DATA RETENTION IN THE ABSENCE OFPOWER• DATA SECURITY PROVIDED BY AUTOMATICWRITE PROTECTION DURING POWERFAILURE• +5 VOLT ONLY READIWRITE• CONVENTIONAL SRAM WRITE CYCLES• FULL CMOS-440 mW ACTIVE; 5.5 mW STANDBY.24-PIN DUAL IN LINE PACKAGE, JEDECPINOUTS• READ-CYCLE TIME EQUALS WRITE-CYCLETIME• LOW-BATTERY WARNING• TWO POWER-FAIL DESELECT TRIP POINTSAVAILABLEMK48Z02 4.75V~VPFD~4.50VMK48Z12 4.50V~VPFD~4.20VR/WPart Number Access Time Cycle TimeMK48ZX2-12 120 ns 120 nsMK48ZX2-15 150 ns 150 nsMK48ZX2-20 200 ns 200 nsMK48ZX2-25 250 ns 250 nsTRUTH T~BLE (MK48Z02/12)Vcc E ~ W MODE DQVIH 'X X Deselect High-ZVcc (Min) VIL VIL VIH Read DOUTVIL VIH VIH Read High-ZVSODeselectsVso X X X Battery High-ZBack-upPIN NAMESBDIP-24(Plastic with Battery Top Hat)FIGURE 1. PIN CONNECTIONSA7 1 24 VceA. 2 23 AsAs 3 22 A9A. 4 21 ViA3 5 20 GA2 6 19 Al0Al 7 18 EAo 8 17 0°7000 9 16 DO.0°1 10 15 DOsDQ2 11 14 DQ.GND 12 13 DQ3Ao' Al0 Address Inputs VccSystem Power (+5 V)E Chip Enable W Write EnableGND Ground G Output EnableDOo-D0 7 Data In/Data OutJune 19881/11277

MK48Z02N2(B)-12115/20/25DESCRIPTIONThe MK48Z02N2 is a 16,384-bit, Non-Volatile StaticRAM, organized 2K x 8 using CMOS and an integralLithium energy source. The ZEROPOWER'"RAM has the characteristics of a CMOS static RAM,with the important added benefit of data beingretained in the absence of power. Data retention currentis so small that a miniature Lithium cell containedwithin the package provides an energysource to preserve data. Low current drain has beenattained by the use of a full CMOS memory cell,novel analog support circuitry, and carefully controlledjunction leakage by an all implanted CMOSprocess. Safeguards against inadvertent data losshave been incorporated to maintain data integrityin the unce.rtain operating environment associatedwith power-up and power-down transients. TheZEROPOWER RAM can replace existing 2K x 8static RAM, directly conforming to the popular ByteWide 24-pin DIP package (JEDEC). MK48Z02N2also matches the pinning of 2716 EPROM and 2Kx 8 EEPROM. Like other static RAMs,there is nolimit to the number of write cycles that can be performed.Since the access time, read cycle, 'and writecycle are less than 250 ns and require only +5 volts,no additional support circuitry is needed for interfaceto a microprocessor.FIGURE 2. BLOCK DIAGRAMr -------IIIIII1VOLTAGE SENSE::LPOWERIAND Poi

MK48Z02/12(B)-12115/20/25OPERATIONRead ModeThe MK48Z02/12 is in the Read Mode wheneverIN (Write Enable) is high and E (Chip Enable) is low.providing a ripple-through access of data from eightof 16.384 locations in the static storage array. Thus.the unique address specified by the 11 Address Inputs(An) defines which one of 2.048 bytes of datais to be accessed.Valid data will be available to the eight data OutputDrivers within tAA after the last address input signalis stable. providin..9 that the E and 'G accesstimes are satisfied. If E or G access times are notmet. data access will be measured from the limitingparameter (tCEA or toEA>. rather than the address.The state of the eight Data 1/0 signals iscontrolled by the E and 'G control signals. The datalines may be in an indeterminate state between toHand tAA• but the data lines will always have validdata at tAA.FIGURE 3. READ-READ-WRITE TIMINGREADtRC=:) ~tRCREADtwcWRITED(C-rtCEAI -tAAi - j--tAS twRl1 -ItAW -,ViDOD-D07 -------......,.-{IAC ELECTRICAL CHARACTERISTICS (READ CYCLE TIMING)(O°C:sTA:s70°C) (Vcc (Max)~Vcc~Vcc (Min))MK4BZX2·12 MK4BZX2·15 MK4BZX2·20SYM PARAMETER MIN MAX MIN MAX MIN MAXtRC Read Cycle Time 120 150 200tAA Address Access Time 120 150 200tCEA Chip Enable Access Time 120 150 200tOEA Output Enable Access Time 75 75 80tCEZ Chip Enable Hi to High-Z 30 35 40toEZ Output Enable Hi to High-Z 30 35 40tOH Valid Data Out Hold Time 15 15 15MK4BZX2·25MIN MAX UNITS NOTES250 ns250 ns 1250 ns 190 ns 150 ns50 ns15 ns 1NOTE1. Measured using the Output Load Diagram shown in Figure 8.3/11279

MK48Z02112(B)-12115/20/25WRITE MODEThe MK48Z02/12 is in Write Mode whenever the Wand E inputs are held low. The start of a Write isreferenced to the latter occurring falling edge ofeither Wor E. A Write is terminated by the earlierrising edge of W or E. The ~dre~ses must be heldvalid throughout the cycle. W or E must return highfor a minimum of twa prior to the initiation ofanother Read or Write Cycle. Data-in must be validfor tos prior to the End of Write and remain validfor tOH afterward.Some processors thrash producing spurious WriteCycles during power-up, despite !!ppliQ!ltion of apower-on reset. Users should force W or E high duringpower-up to protect memory after Vee reachesVec (min) but before the processor stablizes.The MK48Z02/12 G input is a DON'T CARE in thewrite mode. G can be tied low and two-wire RAMcontrol can be implemented~ low on W will disablethe outputs tWEZ after W falls. Take care toavoid bus contention when operating with two-wirecontrol.FIGURE 4. WRITE-WRITE-READ TIMINGWRITEWRITEREADAC ELECTRICAL CHARACTERISTICS (WRITE CYCLE TIMING)(O°C:5TA:570°C) (Vee (Max)~Vee~Vee (Min»MK48ZX2·12 MK48ZX2·15 MK48ZX2·20 MK48ZX2·25SYM PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTEStwe Write Cycle Time 120 150 200 250 nstAS Address Setup Time 0 0 0 0 nstAW Address Valid to End of Write 90 120 140 180 nsteEw Chip Enable to End of Write 75 90 120 160 nstWEw Write Enable to End of Write 75 90 120 160 nstWR Write Recovery Time 10 10 10 10 nstos Data Setup Time 35 40 60 100. nstOH Data Hold Time 0 0 0 0 nstWEz Write Enable Low to High-Z 40 50 60 80 ns4111280

MK48Z02/12(B)-12/15/20/25DATA RETENTION MODEWith Vee applied, the MK48Z02112 operates as aconventional BYTEWIDE static ram. However, Veeis being constantly monitored. Should the supplyvoltage decay, the RAM will automatically powerfaildeselect, write protecting itself when Vee fallswithin the VpFD (max), VpFD (min) window. TheMK48Z02 has a VPFD (max) -VPFD (min) window of4.75 volts to 4.5 volts, providing very high data security,particularly when all of the other system componentsare specified to 5.0 volts plus and minus10%. The MK48Z12 has a VPFD (max) -VPFD (min)window of 4.5 volts to 4.2 volts, allowing users constrainedto a 10% power supply specification to usethe device.FIGURE 5. CHECKING THE BOK FLAG STATUSREAD DATAAT ANYADDRESSNote: A mid-write cycle power failure may corruptdata at the current address location, but does notjeopardize the rest of the RAM's content. At voltagesbelow VPFD (min), the user can be assured thememory will be in a write protected state, providedthe Vce fall time does not exceed tF. TheMK48Z02112 may respond to transient noise spikesthat reach into the deselect window if they shouldoccur during the time the device is sampling Vee.Therefore decoupling of power supply lines isrecommended.The power switching circuit connects external Veeto the RAM and disconnects the battery when Veerises above Vso. As Vee rises the battery voltageis checked. If the voltage is too low, an internal BatteryNot OK (BDK) flag will be set. The BOK flagcan be checked after power up. If the BOK flag isset, the first write attempted will be blocked. Theflag is automatically cleared after first write, and normalRA~ operation resumes. Figure 5 illustrateshow a B K check routine could be structured.Normal RAM operation can resume tREe after Veeexcee.!ls V.l!fD (Max). Caution should be taken tokeep E or W high as Vee rises past VPFD (Min) assome systems may perform inadvertent write cyclesafter Vee rises but before normal system operationbegins.WRITECOMPLIMENTDATA BACKTO SAMEADDRESSREAD DATAAT SAMEADDRESSAGAINWRITE ORIGINALDATA BACK TOSAME ADDRESSNOTIFY SYSTEMOF LOWeATTERY (DATA MAYBE CORRUPTED)5/11281

MK48Z02/12(B)-12/15/20/25FIGURE 6. POWER-DOWN/POWER"UP TIMINGVee -----"\VPFD (MAX) - -VPFD (MIN) - -t.EorWDC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TRIP POINT VOLTAGES)(O°C sT AS +70 "C)SYM PARAMETER MIN TYP MAXVpFD Power-fail Deselect Voltage (MK48Z02) 4.50 4.6 4.75VPFD Power-fail Deselect Voltage (MK48Z12) 4.20 4.3 4.50V,,,, Battery Back-up Switchover Voltage 3AC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TIMING)(O"C sT AS +70 "C)UNITSNOTESV 1V 1V 1SYM PARAMETER MINtpD E or ViI at V IH before Power Down 0tF VpFD (Max) to VpFD (Min) Vce Fall Time 300tFB VpFD (Min) to Vso Vce Fall Time 10tAB Vso to VPFD (Min) Vee Rise Time 1tA VpFD (Min) to VPFD (Max) Vee Rise Time 0tREe E or W at V IH after Power Up 2NOTES:1. All voltages referenced to GND.2. VPFD (Max) to VpFD (Min) fall times of less tF may result in deselectioniwriteprotection not occurring until 50 "'s after Vee passes VpFD (Min). VPFD(Max) to (Min) fall times of less than 10 "'s may cause corruption of RAM data.3. VPFD (Min) to VSO fall times of less than tFB may cause corruption of RAMdata.MAXUNITS NOTESnsp's 2p's 3p.Sp.SmsCAUTIONNegative undershoots below -0.3 volts are not allowedon any pin while in Battery Back-up mode.6111282

MK48Z02112(B)-12/15/20/25DATA RETENTION TIMEAbout Figure 7Figure 7 illustrates how expected MK48Z02/12 batterylife is influenced by temperature. The life of thebattery is controlled by temperature and is virtuallyindependent of the percentage of time theMK48Z02/12 spends in battery back-up mode.Battery life predictions presented in Figure 7 areextrapolated from temperature accelerated life-testdata collected in over 100 million device hou~s ofcontinuing bare cell and encapsulated cell batterytesting by SGS:rHOMSON. Obviously, temperatureaccelerated testing cannot identify non-temperaturedependent failure mechanisms. However, in viewof the fact that no random cell failures have beenrecorded in any of SGS-THOMSON's ongoing batterytesting since it began in 1982, we believe thelikelihood of such failure mechanisms surfacing isextremely poor. For the purpose of this testing, acell failure is defined as the inability of a cell stabilizedat 25"C to produce a 2.0 volt closed-circuit voltageacross a 250K ohm load resistance.A Special Note: The summary presented inFigure 7 represents a conservative analysis ofthe data presently available. While SGS­THOMSON is most likely in possession of thelargest collection of battery life data of this kindin the world, the results presented should notbe considered absolute or final; they can be expectedto change as yet more data becomesavailable. We believe that future read-points oflife tests presently under way and improvementsin the battery technology itself will result in a continuingimprovement of these figures.Two end of life curves are presented in Figure 7.They are labeled ''Average (tsOOAl)" and "(t,OAl)".These terms relate to the probability that a givennumber of failures will have accumulated by a particularpOint in time. If, for example, expected lifeat 70 °C is at issue, Figure 7 indicates that a particularMK48Z02/12 has a 1% chance of having a batteryfailure 11 years into its life and a 50% chanceof failure at the 20 year mark. Conversely, given asample of devices, 1% of them can be expected toexperience battery failure within 11 years; 50% ofthem can be expected to fail within 20 years.The t,% figure represents the practical onset ofwear-out, and is therefore suitable for use in whatwould normally be though of as a worst-case analysis.The t5O% figure represents "normal" or "average"life. It is, therefore, accurate to say that theaverage device will last "tSO%".Battery life is defined as beginning on the date ofmanufacture. Each MK48Z02/12 is marked with afour digit manufacturing date code in the formYYWW (Example: 8502 = 1985, week 2).Calculating Predicted Battery LifeAs Figure 7 indicates, the predicted life of the batteryin the MK48Z02l12 is a function of temperature.The back-up current required by the memory matrixin the MK48Z02/12 is so low that it has negligibleinfluence on battery life.Because predicted battery life is dependent upon applicationcontrolled variables, only the user can estimatepredicted battery life in a given design. As longas ambient temperature is held reasonably constant,expected life can be read directly from Figure 7. ifthe MK48Z02/12 spends an appreciable amount oftime at a variety of temperatures, the following equationsshould be used to estimate battery life.Predicted Battery life = _________-'-1_________[(TA,ITT)/BL,))+[(TA21TT)/BL2)+··· +[(TAnITT}/BLn))Where TA" TA2, TAn = Time at Ambient Temperature 1, 2, etc.TT = Total Time = TA, + TA2 + ... + TAnBL" BL2, BLn = Predicted Battery lifetime at Temp 1, Temp 2, etc. (see Figure 7).EXAMPLE PREDICTED BATTERY LIFE CALCULATIONA cash registerlterminal operates in an environmentwhere the MK48Z02/12 is exposed to temperaturesof 30°C (86°F) or less for 3066 hrslyr; temperaturesgreater than 25°C, but less than 40 °C (104 OF), for5256 hrs/yr; and temperatures greater than 40 o e,but less than 70 0 e (158°F), for the remaining 438hrslyr.Reading predicted typical life values from Figure 7; BL, = 456 yrs., BL2 = 175 yrs., BL3 = 11.4 yrs.Total Time (TT) = 8760 hrs.lyr. TA, = 3066 hrs.lyr. TA2 =5256 hrs.lyr. TA3 = 438 hrs.lyr.Predicted Typical Battery life ;:: 1[(3066/8769)/456)+[(5256/8760)/175)+[(438/8760)/11.4);:: 116.5 yrs.7111283

MK48Z02/12(B)-12/15/20/25FIGURE 7. MK48Z02/12 PREDICTED BATTERY STORAGE LIFE VS TEMPERATURE300200(J)10090807060504030a:w 20> '"10987620I30 40 50 60 70 8090DEGREES CELSIUS8111284

MK48Z02/12(B)-12/15/20/25~BSOWTE MAXIMUM RATINGS·Voltage On Any Pin Relative To GND ...................................... -0.3 V to +7.0 VAmb!ent Operating (Vce On) Temperature (TAl ................................. O:C to +70OCAmbient Storage (Vcc Off) Temperature .................................... -40 C to +85OCTotal Device Power Dissipation .................................................... 1 WattOutput Current Per Pin .......................................................... 20 mA·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.rhis is a stress rating only and functional operation of the device at these or any other conditions above those indicatedn the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.:AUTION: Under no conditions can the ''Absolute Maximum Rating" for the voltage on any pin be exceeded sincet will cause permanent damage. Specifically, do not perform the "standard" continuity test on any input or output pin,.e do not force these pins below -0;3 V DC.FtECOMMENDED DC OPERATING CONDITIONS:OOC~TA~70OC)SYMPARAMETERMINMAX UNITS NOTESVceSupply Voltage (MK48Z02)4.755.50 V 1VceSupply Voltage (MK48Z12)4.505.50 V 1GNDSupply Voltage00 V 1VIHLogic "1" Voltage All Inputs2.2Vcc + 0.3 V V 1VILLogic "0" Voltage All Inputs-0.30.8 V 1,2I)C ELECTRICAL CHARACTERISTICS:OOC~TA~+70°C) (Vcc (max)~Vcc~Vcc (min»SYMICClIcc2PARAMETERAverage V ce Power Supply CurrentTIL Standby Current (E = VIH)Icc3 CMOS Standby Current (E~Vec-0.2 V)IlLIOLVOHVOLInput Leakage Current (Any Input)Output Leakage CurrentOutput Logic "1" Voltage (lOUT = -1.0 mAlOutput Logic "0" Voltage (lOUT = 2.1 mAl::APACITANCE (T A = 25°C)SYM PARAMETERC I Capacitance on all pins (except 0/0)CO/QCapacitance on 010 pinsMIN-1-52.4MAX UNITS NOTES80 mA 33 mA1 mA+1 pA 4+5 pA 4V0.4 VMAX NOTES7 pF 510 pF 4,5.OTESI. All voltages referenced to GND.!. Negative spikes of -1.0 volts allowed for up to 10 ns once per cycle.I. ICC1 measured with outputs open.k Measured with GNDsVp;;VCC and outputs deselected.i. Effective capacitance calculated from the equation C = l.

MK48Z02112(B}-12115/20/25AC TEST CONDITIONSInput Levels:lI'ansition Times:Input and Output TimingReference LevelsAmbient TemperatureVce (MK48Z02)Vee (MK48Z12)0.6 V to 2.4 V5 ns0.8 V or 2.2 VOOC to 700C4.75 V to 5.5 V4.5 Vto 5.5 VFIGURE 8. OUTPUT LOAD DIAGRAM+SV1.8 KGDEVICEUNDERTESTl00.pF(INCWDING SCOPE AND JIG)ORDERING INFORMATION,MK48ZDEVICEFAMILYxVee RANGE2BPACKAGE-xxSPEEDL-12·15-20-25120 NS ACCESS TIME150 NS ACCESS TIME200 NS ACCESS TIME250 NS ACCESS TIMEBPLASTIC WITH BATTERYTOP HAT10111286

MK48Z02112(B)-12/15/20/25PACKAGE DESCRIPTIONB PACKAGE 24 PINDim.mmMin Max MinBATTERY 0 - 32.693 -ONLY Z 13.97 14.476 .550A 6.126 9.652 .320A2 7.62 9.144 .300E 13.462 13.97 .530B 0.361 0.533 .015B, 1.143 1.776 .045C 0.203 0.355 .00624 PIN Di - 32.256 -PLASTIC E 13.462 16.256 .530D.I.P. eA 15.24 17.78 .600ONLY ., 2.286 2.794 .090L 3.046 3.61 .120A 0.361 0.762 .0155 1.524 2.286 .060InchesMax1.295.570.360.360.550.021.070.0141.270.640.700.110.150.030.090Notes44132~-------E------~~11+--4 -.A---+I.INOTES:1. Overall length includes .010 in. flash on either end 01 the package.2. Package standoff to be measured per JEDEC requirements.3. Measured from centerline to centerline at lead tips.4. When the solder lead finish is specified, the maximum limit shaH be increasedby .003 in.11111287

MK48C02A/12A(K, N)·15/20/252K x 8 ZEROPOWERTM RAM• LON CURRENT (1 pi. @ 7O"C) BATTERY INPUTFOR DATA RETENTION IN THE ABSENCE OFPOWER• DATA SECURITY PROVIDED BY AUTOMATICWRITE PROTECTION DURING POWERFAILURE• +5 VOLT ONLY READIWRITE• CONVENTIONAL SRAM WRITE CYCLES• LOW POWER 440 mW ACTIVE; 5.5 mWSTANDBY~U.,NDIP-28(Plastic Package)KPLCC32(Plastic Chip Carrier)• READ-CYCLE TIME EQUALS WRITE-CYCLETIME• LOW-BATTERY WARNING• TWO POWER-FAIL DESELECT TRIP POINTSAVAILABLEMK48C02A 4.75V~VPFD~4.50VMK48C12A 4.50V~VPFD~4.20V• POWER FAIL INTERRUPT OUTPUTRIWPart Number Access Time Cycle TimeMK48CX2A-15 150 ns 150 nsMK48CX2A-20 200 ns 200 nsMK48CX2A-25 250 ns 250 nsFIGURE 1. PIN CONNECTIONSva 1 28 VeeN.C. 2 27 N.C.A7 3 26 INTA. 4 25 A.As 5 24 A.A. 6 23 ViA. 7 22 GA. 8 21 A,.A, 9 20 EA. 10 19 DQ7DQ. 11 18 DQ.DQ, 12 17 DQ.DQ. 13 16 DQ.GND 14 15 DQ.!C ~ ~ ~ ~ ~ II• • • , 32 31 30••A8PIN NAMESAr,- A,o Address Inputs VccSystem Power (+5 V)E Chip Enable W Write EnableGND Ground G Output EnableDOo-D0 7 Data In/Data Out VB Battery InputINTPower Fail Interrupt (Open Drain Type)14 15 16 17 18 19 20NCNo ConnectionJune 19881/10289

MK48C02AI12A(K,N)-15/20/25TRUTH TABLE (MK48C02AI12A)Vec" E ~ W MODE DQVIH X X Deselect High-Z." Vee (Min) VIL VIL VIH Read DourVIL VIH VIH Read High-ZVsoDeselectsVso X X X Battery High-ZBack-upDESCRIPTIONThe MK48C02N12A is a CMOS RAM with internalpower fail support circuitry for battery backup ap-plications. The fully static RAM uses an HCMQSsix transistor cell and is organized 2K x 8. Includedin the device is a feature to conserve batteryenergy and a method of providing data security duringVee transients. A precision voltage detectorwrite-protects the RAM to prevent inadvertent lossof data when Vee falls out of toleranc~. In thl! way,all input and output pins (including E and W) become"don't care". The device permits full functionalability of the RAM for Vee above 4.7SV(MK48C02A) and 4.SV (MK48C12A). Data protectionis provided for Vee below 4.SV (MK48C02A) and4.2V (MK48C12A),and maintains data in the absenceofVee with no addi.tional support circuitryother than a primary cell. The current supplied bythe battery during data retention is for junction leakageonly (typically less thanSna) because all powerconsumingcircuitry is turned off. The low batterydrain allows use of a long life Lithium primary cell.FIGURE 2. BLOCK DIAGRAMr------------,IIIIIIII2Kx8~~--~~----_, POWERRAMI VOLTAGE SENSECMOSINT~-----I AND i>oR CELL IISWITCHINGCIRCUITRY BOK IL _______________ ...1IDQO-DQ7EViiG2110290

MK48C02AI12A(K,N)-15/20/25OPERATIONRead ModeThe MK48C02A112A is in the Read Mode wheneverIN (Write Enable) is high and E (Chip Enable) is low,providing a ripple-through access of data from eightof 16,384 locations in the static storage array. Thus,the unique address specified by the 11 Address Inputs(An) defines which one of 2,048 bytes of datais to be accessed.Valid data will be available to the eight data OutputDrivers within tM after the last aQ.dress input signalis stable, providin.9 th~ the E and G accesstimes are satisfied. If E or G access times are notmet, data access will be measured from the limitingparameter (tCEA or tOEA>, rather than the address.The state of the eight Data 1/0 signals iscontrolled by the E and G control signals. The datalines may be in an indeterminate state between IoHand tM , but the data lines will always have validdata at tM .FIGURE 3. READ-READ-WRITE TIMINGREAOtRe~D(tAeREAD-rteEAI ~tAAI -'weWRITEI--t-tAS 'wR1lI tAW--jlXK=INt ! !DQ.-DQ 7---------{IAC ELECTRICAL CHARACTERISTICS (READ CYCLE TIMING)(0°CsTAs70°C) (VCC (Max}~Vcc~Vcc (Min))MK48CX2A·15 MK48CX2A·20 MK48CX2A·25SYM PARAMETER MIN MAX MIN MAXtRC Read Cycle Time 150 200tM Address Access Time 150 200tCEA Chip Enable Access Time 150 200tOEA Output Enable Access Time 75 80teEz Chip Enable Hi to High-Z 35 40tOEZ Output Enable Hi to High-Z 35 40tOH Valid Data Out Hold Time 15 15MIN MAX UNITS NOTES250 ns250 ns 1250 ns 190 ns 150 ns50 ns15 ns 1NOTE1. Measured using the Output Load Diagram shown in Figure 7.3/10291

MK48C02A/12A(K,N)-15/20/25WRITE MODEThe MK48C02A112A is in Write Mode whenever theWand E inputs are held low. The start of a Writeis refe~nee!!. to the latter occurring falling edge ofeither W or E.~ Wme is terminated by the earlierrising edge of W or E. The .l!9dr~ses must be heldvalid throughout the cycle. W or E must return. high,for a minimum of tWR prior to the initiation ofanother Read or Write Cycle. Data-in must be validfor tos prior to the End of Write and remain validfor tOH afterward.Some processors thrash producing spurious WriteCycles during power-up, despite !!ppli~tion of apower-on reset. Users should force W or E high duringpower-up to protect memory after Vee reachesVee (min) but before the processor stablizes.The MK48C02~12A G input is a DON'T CARE inthe write mode. G can be tied low and two-wire RAMcontrol can be implemented. A low on W will disablethe outputs tWEZ after W falls. Take care toavoid bus contention when operating with two-wirecontrol.FIGURE 4. WRITE-WRITE-READ TIMINGWRITEWRITEREADwVALIDINVALIDINVALIDOUTAC ELECTRICAL CHARACTERISTICS (WRITE CYCLE TIMING)(O°C:s;TA:s;70°C) (Vee (Max)2:Vec2:Vec (Min))MK4BCX2A·15 MK4BCX2A·2D MK4BCX2A·25SYM PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 150 200 250 nstAS Address Setup Time 0 0 0 nstAW Address Valid to End of Write 120 140 180 nstCEw Chip Enable to End of Write 90 120 160 nstWEW Write Enable to End of Write 90 120 160 nstWR Write Recovery Time 10 10 10 nst DS Data Setup Time 40 60 100 nstOH Data Hold Time 0 0 0 nstWEZ Write Enable Low to High-Z 50 60 80 ns4/10292

MK48C02A/12A(K, N)-15/20/25DATA RETENTION MODEWith Vee applied, the MK48C02A112A operates asa conventional BYTEWIDE static ram. However,Vee is being constantly monitored. Should the supplyvoltage decay, the RAM will automatically powerfaildeselect, write protecting itself when Vee fallswithin the VPFD (max), VPFD (min) window. TheMK48C02A has a VPFD (max) -VPFD (min) windowof 4.75 volts to 4.5 volts, providing very high datasecurity, particularly when all of the other systemcomponents are specified to 5.0 volts plus and minus10%. The MK48C12A has a VPFD (max) -VPFD(min) window of 4.5 volts to 4.2 volts, allowing usersconstrained to a 10% power supply specificationto use the device.Note: A mid-write cycle power failure may corruptdata at the current address location, but does notjeopardize the rest of the RAM's content. At voltagesbelow VpFD (min), the user can be assured thememory will be in a write protected state, providedthe Vee fall time does not exceed tF. TheMK48C02A112A may respond to transient noisespikes that reach into the deselect window if theyshould occur during the time the device is samplingVee. Therefore decoupling of power supply lines isrecommended.FIGURE 5. CHECKING THE BOK FLAG STATUSREAD DATAAT ANYAODRESSWRITECOMPLIMENTDATA BACKTO SAMEADDRESSREAD DATAAT SAMEADDRESSAGAINThe power SWitching circuit connects external Veeto the RAM and disconnects the battery when Veerises above Vso. As Vee rises the battery voltageis checked. If the voltage is too low, an internal BatteryNot OK (BOI

MK48C02AI12A(K,N)-15/20/25AC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TIMING)(OOC sT A s +70OC)SYM PARAMETER MIN MAXtF VPFD (Max) to VPFD (Min) Vee Fall Time 300tFB VpFD (Min) to Vso Vee Fall Time 10tRB Vso to VpFD (Min) Vee Rise Time 1tR VPFD (Min) to VPFD (Max) Vee Rise Time 0tREe E or W at V1H after VpFD (max) 120tpFX INT Low to Auto Deselect 10 40tpFH VPFD (Max) to INT High 120tFB VPFD (Min) to Vso 10UNITS NOTESfls 2flS 3fISflSflsflsfls 4flsDC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TRIP POINT VOLTAGES)(OOC sT A s+70OC)SYM PARAMETER MINVPFD Power-fail Deselect Voltage (MK48C02A) 4.50VPFD Power-fail Deselect Voltage (MK48C12A) 4.20Vso Battery Back-up Switchover VoltageTYP MAX4.6 4.754.3 4.503UNITS NOTESV 1V 1V 1NOTES:1. All voltages referenced to GND.2. VpFD (Max) to VPFD (Min) fall times of less tF may result in deselectioniwriteprotection not occurring until 40 ,.8 after Vee passes VpFD (Min). VpFD(Max) to (Min) fall times of less than 10,.s may cause corruption of RAM data.3. VPFD (Min) to VSO fall times of less than tFB may cause corruption of RAM~.4. INT may go high anytime after Vee exceeds VPFD (min) and is guaranteedto go high tpFH after Vee exceeds VPFD (max).CAUTIONNegative Undershoots Below -0.3 volts are not allowedon any pin while in Battery Back-up mode.6110294

MK48C02A112A(K,N)-15/20/25FIGURE 6. POWER DOWN/POWER-UP TIMINGV pFD (MAX)- -V.F• (MIN)- -ALL INPUTSAECOGNIZEDIIDON'T CARE--.It,,"K NOTE>-RECOGNIZEDALLVALIDOUTPUTS (PEA CON.TAOL INPUTI I}-------I t---- HIGH.zVALID(PEA CONTROL INPUT)NOTE:Inputs mayor may not be recognized at this time,Caution should be taken to keep E or W in the high state Vee rises pastVPFD (min), Some systems may perform inadvertant write cycles aiter Veerises but before normal system operation begins. Even though a power onreset is being applied to the processor a reset condition may not occur untilaiter the system clock is running.7/10295

M K48C02A/12A(K,N)-15/20/25ABSOWTE MAXIMUM RATINGS·Voltage On Any Pin Relative To GND ...................................... -0.3 V to +7.0 VAmbient Operating (Vee On) Temperature (TAl ................................. O°C to +70OCAmbient Storage (Vee( Off) Temperature ................................... -55°C to +125OCTotal Device Power Dissipation .................................................... 1 WattOutput Current Per Pin .......................................................... 20 mA·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stressrating only and functional operation of the device at these or any other conditions above those indicated in the operational section of thisspecification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.CAUTION: Under no conditions can the "Absolute Maximum Rating" for the voltage on any pin be exceeded since it will cause permanentdamage. Specifically, do not perform the "'standard" continuity test on any input or output pin, i.e do not force these pins below -0.3 V DC.RECOMMENDED DC OPERATING CONDITIONS(O°C

MK48C02A112A(K,N)-15/20/25AC TEST CONDITIONSFIGURE 7. OUTPUT LOAD DIAGRAMInput Levels:Transition Times:Input and Output TimingReference LevelsAmbient TemperatureVee (MK48C02A)Vee (MK48C12A)0.6 V to 2.4 V5 ns0.8 V or 2.2 VOOC to 700C4.75 V to 5.5 V4.5 V to 5.5 VDEVICEUNDERTEST+5Vt 1.8KO1.0 KO ':;0 ~ 100 pF~ (INCLlJDING SCOPE AND JIG)-=,FORDERING INFORMATIONMK48CDEVICEFAMILYXVee RANGE2A X -XXPACKAGESPEEDL-15 150 NS ACCESS TIME-20 200 NS ACCESS TIME-25 250 NS ACCESS TIMEKN32 PIN PLCC28 PIN DIPo1+10%/-5%+10%1-100/09/10297

MK48C02'Al12A(K,N~15/20125FIGURE 8.· MK48C02A112A PLASTIC LUDED CHIP CARRIER, 32 PIN (K TYPE)Dim.mmInche.Min Me. Min Ma.A 3.048 3.556 .120 .140Al 1.981 2.413 .078 .095B 0.330 0.533 .013 .021Bl 0.660 0.812 .026 .0320 12.319 12.573 .485 .49501 11.353 11.506 .447 .45302 9.906 10.922 .390 .430E 14.859 15.113 .585 .595El 13.893 14.046 .547 .553E2 12.446 13.462 .490 .530FIGURE 9. MK48C02A112A PLASTIC (N TYPE) DUAL-IN-LlNE, 28 PINS.!:!Q!§!I. OVERALL LENGTH INCLUOES:010 IN.FLASH ON EITHER END OF THE PACKAGE.2. PACKAGE STANDOFF TO BE MEASUREDPER ~EDEC REQUIREMENTS.3. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. IjHENSOLDER LEAD FINISH IS SPECIFIED.Dim.AAlA2BBlC001EEl01oALMin-0.3813.556mm0.3811.270.20336.5761.65115.2413.4622.26615.243.048InchesMa. Min Ma.Note.5.334 - .210 2- .015 - 24.064 .140 .1600.533 .015 .021 31.778 .050 .0700.304 .008 .012 337.338 1.440 1.470 12.159 .065 .08515.875 .600 .62514.224 .530 .5602.794 .090 .11017.78 .600 .700- .120 -10110298

MK48T02/12(B)-12/15120/252K x 8 ZEROPOWERTM/TIMEKEEPERTM RAM• INTEGRATED ULTRA LOW POWER SRAM,REAL TIME CLOCK, CRYSTAL, POWER-FAILCONTROL CIRCUIT AND BATTERY• BYTEWIDE'" RAM-LIKE CLOCK ACCESS• BCD CODED YEAR, MONTH, DAY, DATE,HOURS, MINUTES AND SECONDS• SOFTWARE CONTROLLED CLOCK CALIBRA­TION FOR HIGH ACCURACY APPLICATIONS• PREDICTED WORST CASE BATTERYSlORAGE LIFE OF 11 YEARS @ 700C• PIN AND FUNCTION COMPATIBLE WITHJEDEC STANDARD 2K x 8 SRAMS• AUTOMATIC POWER-FAIL CHIPDESELECTIWRITE PROTECTION• TWO POWER-FAIL DESELECT TRIP POINTSAVAILABLEMK48T02 4. 75V ~ V PFD ~ 4.50VMK48T12 4.50V~VPFD~4.20VRIWPart Number Access Time Cycle TimeMK48TX2-12 120 ns 120 nsMK48TX2-15 150 ns 150 nsMK48TX2-20 200 ns 200 nsMK48TX2-25 250 ns 250 nsTRUTH TABLE (MK48T02/12)Vee. E ~ W MODE DQVIH X X Deselect High-ZVec (Min) VIL VIL VIH Read DOUTVIL VIH VIH Read High-ZVsoDeselectsVso X X X Battery High-ZBack-upPIN NAMESBDIP-24(Plastic with Battery Top Alt)FIGURE 1. PIN CONNECTIONSA7 1 24 VeeAs 2 23 AsAs 3 22 AgA4 4 21 ViA3 5 20 GA2 6 19 A '0A, 7 18 EAo 8 17 OQ7OQo 9 16 OQ6OQ, 10 15 OQsOQ2 11 14 OQ4GNO 12 13 OQ3Ao- A'D Address Inputs Vee +5 VE Chip Enable W Write EnableGND Ground G Output Enable00 0 -00 7 Data In/Data OutJune 19881/14299

MK48T02/12(B)-12115/20/25DESCRIPTIONThe MK48T02/12 combines a 2K x 8 full CMOSSRAM, a BYTEWIDE accessible real time clock, acrystal and a long life lithium carbon mono-fluoridebattery, all in a single plastic DIP package. TheMK48T02/12 is a non-volatile pin and functionequivalent to any JEDEC standard 2K x 8 SRAM,such as the 6116 or 5517. It also easily fits into manyEPROM AND EEPROM sockets, providing the nonvolatilityof the PROMs without any requirement forspecial write timing, or limitations on the numberof writes that can be performed.Access to the clock is as simple as conventionalBYTEWIDE RAM access because the RAM and theClock are combined on the same die. As Figure 2indicates, the TIMEKEEPER registers are locatedin the upper eight locations of the RAM. Theregisters contain, beginning at the top; year, month,date, day, hour, minutes, and seconds data in 24Hour BCD format. Corrections for 28, 29 (LeapYear), 30 and 31 day months are made automati-cally. The eighth location is a Control register. Theseregisters are not the actual clock counters; they areBiPORT read/write Static RAM memory locations.The MK48T02/12 includes a clock control circuitthat, once every second, dumps the counters intothe BiPORT RAM.Because the Clock Registers are constructed usingBiPORT memory cells, access to the rest of theRAM proceeds unhindered by updates to theTIMEKEEPER registers, even if the TIMEKEEPERregisters are being updated at the very momentanother location in the memory array is accessed.The MK48T02/12 also has its own Power-fail Detectcircuit. The circuit deselects the device wheneverVcc is out of range, providing a high degree of datasecurity in the midst of unpredictable system operationsbrought on by low Vce.BiPORT, BYTEWIDE, TIMEKEEPER and ZEROPOWERare trademarks of SGS-THOMSON Microelectronics, Inc ..FIGURE 2_ BLOCK DIAGRAMTOP HATrl-r------------,I I:.f III~ II132768 Hz!YSTAUI CRIIII L ITHIUMIELL II Cl 4IIIIIIIT:OSCILLATION ANDCLOCK CHAINVOLTAGE SENSEANDSWITCHINGCIRCUITRYI\~POWERPOKBOK• 8X8\ BIPORTj SRAM ARRAY IV-A/II\2040 X 8 A ISRAM /ARRAY \'jIIIIIL _-L __ -I ------- - _..J- L-Ao-A 10~DQo-DQ 7V-EViG2114300

MK48T02/12(B)-12/15/20/25OPERATIONREAD MODEThe MK4ST02/12 is in the Read Mode wheneverW (Write Enable) is high and E (Chip Enable) is low.The device architecture allows ripple-through access(changing Addresses without removing ChipEnable) to any of the 2048 address locations in thestatic storage array. Valid data will be available atthe Data 1/0 pins within tAA after the I~t adQ!essinput signal is stable, providing that the E and G accesstimes are satisfied.If E or G access times are not yet met, valid datawill be available at the latter of Chip Enable AccessTime (tc;EA) or at Output Enable Access Time(tOEAl. The state of the ....!3ight three-state Data 1/0signals is controlled by E and G. If the Outputs areactivated before tAA, the data lines will be drivento an indeterminate state ..!Intil t~. If the Addressinputs are changed while E and G remain low, outputdata will remain valid for Output Data Hold Time(tOH) but will go indeterminant until the next tAA.FIGURE 3. READ-READ-WRITE TIMINGREADIRC~}(IRCREADIwcWRITE~C-rICEAi -IAAi -- r--- IAS l+-IWR::rlI IAW---1) ! !DOo-DO, ---------

MK48T02/12(B)-12/15/20/25WRITE MODEThe MK48T02/12 is in Write Mode whenever the Wand E inputs are held low. The start of a Write isreferenced to the latter occurring falling edge ofeither Wor E. A Write is terminated by the earlierrising edge of W or E. The ~dre~ses must be heldvalid throughout the cycle. W or E must return highfor a minimum of tWIl prior to the initiation ofanother Read or Write Cycle. Data-in must be validfor tos prior to the End of Write and remain validfor tOH afterward.Some processors thrash producing spurious WriteCycles during power-up, despite ~pli'2...ation of apower-on reset. Users should force W or E high duringpower-up to protect memory after Vcc reachesVcc (min) but before the processor stablizes.The MK48T0g[12 G input is a DON'T CARE in thewrite mode. G can be tied low and two-wire RAMcontrol can be implemented~ low on W will disablethe outputs tWEZ after W falls. Take care toavoid bus contention when operating with two-wirecontrol.FIGURE 4. WRITE-WRITE-READ TIMING~lAS ~IAWWRITEIWCWRITEREADwDa,,· Do.,VALIDINVALIDINIwEZ~rVALIDOUTAC ELECTRICAL CHARACTERISTICS (WRITE CYCLE TIMING)(O°CSTAS70"C) (Vcc (Max)~Vcc~Vcc (Min))MK48TX2·12 MK48TX2·15 MK48TX2·20 MK48TX2·25SYM PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 120 150 200 250 nstAS Address Setup Time 0 0 0 0 nstAW Address Valid to End of Write 90 120 140 180 nstCEw Chip Enable to End of Write 75 90 120 160 nstWEW Write Enable to End of Write 75 90 120 160 nstWA Write Recovery Time 10 10 10 10 nstos Data Setup Time 35 40 60 100 nstOH Data Hold Time 0 0 0 0 nstWEz Write Enable Low to High-Z 40 50 60 80 ns4/14302

MK48T02N 2(8)-12/15/20/25CLOCK OPERATIONSReading the ClockUpdates to the TIMEKEEPER registers should beHalted before clock data is read to prevent readingof data in transition. Because the BiPORTTIMEKEEPER cells in the RAM array are only dataregisters, and not the actual counters, updating theregisters can be halted without disturbing the clockitself.Updating is halted when a "1" is written into the"Read" bit, the seventh most significant bit in theControl register. As long as a "1" remains in thatpoSition, updating is halted. After a Halt is issued,the registers reflect the count, that is day, date, andtime that were current at the moment the Halt com-mand was issued. All of the TIMEKEEPER registersare updated simultaneously. A Halt will not interruptan update in progress. Updating is within a secondafter the bit is reset to a "0".Setting the ClockThe eighth bit of the Control register is the "Write"bit. Setting the Write bit to a "1", like the Read Bit,halts updates to the TIMEKEEPER registers. Theuser can then load them with the correct day, dateand time data in 24 Hour BCD format. Resettingthe Write bit to a "0" then transfers those valuesthe actual TIMEKEEPER counters and allows normaloperation to resume. The KS bit, FT bit and thebits marked with zeroes in Figure 5 must be writtenwith zeroes to allow normal TIMEKEEPER andRAM operation.FIGURE 5. THE MK48T02/12 REGISTER MAPADDRESSDATAFUNCTION7FF ------7FE 000---7FD 00-7FC OFTOOO-7FB KSO-7FA 07F97F8STWRSKEY: ST = STOP BITW = WRITE BITR = READ BITS = SIGN BITYEAR 00·99MONTH 01·12DATE 01-31DAY 01-07HOUR 00·23MINUTES 00-59SECONDS 00·59CONTROLFT = FREQUENCY TESTKS = KICK STARTCalibrating the ClockThe MK48T02I12 is driven by a quartz crystal controlledoscillator with a nominal frequency of 32768Hz.The crystal is mounted in the tophat along withthe battery. A typical MK48T02I12 is accurate within±1 minute per month at 25"C without calibration.The devices are tested not to exceed ± 35 ppm(Parl&Per Million) oscillator frequency error at 25"C,which comes to about ±1.53 minutes per month.Of course the oscillation rate of any crystal changeswith temperature. Figure 6 shows the frequency errorthat can be expected at various temperatures.Most clock chips compensate for crystal frequencyand temperature shift error with cumbersometrim capacitors. The MK48T02I12 design, however,employs periodic counter correction. The calibrationcircuit adds or subtracts count from the oscillatordivider circuit at the divide by 256 stage, asshown in Figure 7. The number of times pulses areblanked (subtracted, negative calibration) or split(added, positive calibration) depends upon thevalue loaded into the five bit Calibration byte foundin the Control register. Adding count speeds theclock up, subtracting counts slows the clock down.The Calibration byte occupies the five lower orderbits in the Control register. The byte can be set torepresent any value between 0 and 31 in binaryform. The sixth bit is a sign bit; "1" indicates positivecalibration, "0", indicates negative calibration.Calibration occurs within a 64 minute cycle. The first62 minutes in the cycle may, once per minute, haveone second either shortened or lengthened by 128oscillator cycles, that is one tick of the divide by 256stage. If a binary 1 is loaded into the register, onlythe first two minutes in the 64 minute cycle will bemodified; if a binary 6 is loaded, the first 12 will beaffected, and so on.5/14303

MK48T02112(B)-12/15/20/25FIGURE 6. THE MK48T02/12 OSCILLATOR FREQUENCY VS. TEMPERATURE20z 100:;..Jiffi ·10...~·20f;!; ·30II:~ ·40II:wr;·50zw:> ·6051II:"-·70·80v- --.....V /" "'- ...... ~'" '\'\.'\.\o 10 20 30 40 50 60 70TEMP CC)FIGURE 7. ADJUSTING THE DIVIDE BY 256 PULSE TRAINNORMALPOSITIVECALIBRATIONNEGATIVECALIBRATIONTherefore, each calibration step has the effect ofadding or subtracting 256 oscillator cycles for every125,829,120 (32768. x 60 x 64) actual oscillator cycles,that is 2.034 ppm of adjustment per calibrationstep; giving the user a ± 63.07 ppm calibrationrange. Assuming that the oscillator is in fact run·ning at exactly 32768 Hz, each of the 31 incrementsin the Calibration byte would represent 5.35 secondsper month.Two methods are available for ascertaining howmuch calibration a given MK48T02/12 may require.The first involves simply setting the clock, lettingit run for a month and comparing it to a known accuratereference (like WWV broadcasts). While thatmay seem crude, it allows the designer to give theend user the ability to calibrate his clock as his environmentmay require, even after the final productis packaged in a non-user serviceable enclosure.A" the designer has to do is provide a simple utility that accesses the Calibration byte. The utilitycould even be menu driven and made foolproof.The second approach is better suited to a manufacturingenvironment, and involves the use of sometest equipment. When the Frequency Test (FT) bit,the seventh-most Significant bit in the Day register,is set to a "1 ", and the oscillator is running at 32768Hz, the LSB (00 0) of the Seconds register will tog·gle at a 512 Hz. Any deviation from 512 Hz indicatesthe degree and direction of oscillator frequency shiftat the test temperature. For example, a reading of512.00512 Hz would indicate a +10 ppm(1-(512/512.00512» oscillator frequency error, requiringa -5 (000101v to be loaded into the CalibrationByte for correction. Note that setting orchanging the Calibration Byte does not affect theFrequency Test output frequency. The device mustbe selected and addresses must be stable at Address7F9when reading the 512 Hz on 00 0.6114304

MK48T02112(B)-12/15/20/25The FT bit must be set using the same method usedto set the clock, using the Write bit. The LSB of theSeconds register is monitored by holding theMK48T02/12 in an extended read of the Secondregister, without having the Read bit set. The FTbit MUST be reset to a "0" for normal clock operationsto resume.Stopping and Starting the OscillatorThe oscillator may be stopped at any time. If thedl'lvice is going to spend a significant amount of timeon the shelf, the oscillator can be turned off tominimize current drain from the battery. The "Stop"bit is the MSB of the Seconds register. Setting itto a "1" stops the oscillator. In order to make theoscillator as stingy with current as possible, the oscillatoris designed to require an extra "kick" to beginoscillation again. The extra kick is provided bythe Kick Start (KS) bit, the MSB of the Hoursregister. To start the oscillator, implement the followingprocedure.1. Set the Write Bit to "1".2. Reset the Stop Bit to "0".3. Set the Kick Start Bit to "1 ".4. Reset the Write Bit to "0".5. Wait 2 seconds.6. Set the Write Bit to "1".7. Reset the Kick Start Bit to "0".B. Set the Correct time and date.9. Reset the Write Bit to "0".Note: Leaving the KS bit set will cause the Clock todraw excessive current and will shorten batterylife.DATA RETENTION MODEWith Vee applied, the MK48T02/12 operates as aconventional BYTEWIDE static ram. However, Veeis being constantly monitored. Should the supplyvoltage decay, the RAM will automatically powerfaildeselect, write protecting itself when Vee fallswithin the VpFD (max), VPFD (min) window. TheMK48T02 has a VpFD (max) -VPFD (min) window of4.75 volts to 4.5 volts, providing very high data security,particularly when all of the other system componentsare specified to 5.0 volts plus and minus10%. The MK48T12 has a VpFD (max) -VPFD (min)window of 4.5 volts to 4.2 volts, allowing users constrainedto a 10% power supply specification to usethe device.Note: A mid-write cycle power failure may corruptdata at the currently addressed location, but doesnot jeopardize the rest of the RAM's content. At voltagesbelow VpFD (min), the user can be assuredthe memory will be in a write protected state, providedthe Vee fall time does not exceed tF. TheMK48T02/12 may respond to transient noise spikesthat reach into the deselect window if they shouldoccur during the time the device is sampling Vec.Therefore decoupling of power supply lines isrecommended.The power switching circuit connects external Vceto the RAM and disconnects the battery when Vcerises above Vso. As Vee rises the battery voltageis checked. If the voltage is too low, an internal BatteryNot OK (BOK) flag will be set. The BOK flagcan be checked after power up. If the BOK flag isset, the first write attempted will be blocked. Theflag is automatically cleared after first write, and normalRA~ operation resumes. Figure B illustrateshow a B K check routine could be structured.Normal RAM operation can resume tREe after Veeexceells V.eED (Max). Caution should be taken tokeep E or W high as Vee rises past VpFD (Min) assome systems may perform inadvertent write cyclesafter Vee rises but before normal system operationbegins.FIGURE 8. CHECKING THE BOK FLAG STATUSPOWER-UPtREAD DATAAT ANYADDRESS+WRITECOMPLIMENTDATA BACKTO SAMEADDRESSREAD • DATAAT SAMEADDRESSAGAIN~IS DATANOTIFY SYSTEMCOMPLIMENT NO OF LOWOF FIRSTBATTERY (DATA MAYREAD?BE CORRUPTED)YES(BATTERY OK)WRITE ORIGINALDATA BACK TOSAME ADDRESS(CONTINUE• )7/14305

MK48T02/12(B)-12/15/20/25FIGURE 9. POWER-DOWN/POWER-UP TIMINGVee -----"\V. FD (MAX)­V. FD (MIN) - -EorWDC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TRIP POINT VOLTAGES)(0°C:5T A:5+70°C)SYM PARAMETER MIN TYP MAXVpFD Power-fail Deselect Voltage (MK48T02) 4.50 4.6 4.75VPFD Power-fail Deselect Voltage (MK48T12) 4.20 4.3 4.50Vso Battery Back-up Switchover Voltage 3UNITS NOTESV 1V 1V 1AC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TIMING)(O°C :5T A:5 +70°C)SYM PARAMETER MINtPD E or W at V IH before Power Down 0tF VPFD (Max) to VpFD (Min) Vce Fall Time 300tFB VPFD (Min) to Vso Vee Fall Time 10tRB Vso to VpFD (Min) Vee Rise Time 1tR VPFD (Min) to VpFD (Max) Vee Rise Time 0tREe E or W at V IH after Power Up 2NOTES:1. All voltages referenced to GND.2. VpFD (Max) to VPFD (Min) fall times of less tF may result in deselectioniwriteprotection not occurring until 50 p,s after Vee passes VpFD (Min). VPFD(Max) to (Min) fall times of less than 10 p,s may cause corruption of RAMdata or stop the clock.3. VPFD (Min) to VSO fall times of less than tFB may cause corruption of RAMdata or stop the clock.MAXUNITS NOTESnsp's 2p's 3p.Sp'smsCAUTIONNegative undershoots below -0.3 volts are not allowedon any pin while in Battery Back-up mode.8/14306

MK48T02112(B)-12115/20/25PREDICTING BACK-UP SYSTEM LIFEThe useful life of the battery in the MK48T02I12 isexpected to ultimately come to an end for one oftwo reasons; either because it has been dischargedwhile providing current to an external load; or becausethe effects of aging render the cell uselessbefore it can actually be discharged. Fortunately,these two effects are virtually unrelated, allowingdischarge, or Capacity Consumption and the effectsof aging, or Storage Life to be treated as two independentbut simultaneous mechanisms, the earlierof which defines Back-up System life.The current drain that is responsible for CapacityConsumption can be reduced either by applyingVee or turning off the oscillator. With the oscillatoroff, only the leakage currents required to maintaindata in the RAM are flowing. With Vcc on, the batteryis disconnected from the RAM. Because theleakage currents of the MK48T02I12 are so low, theycan be neglected in practical Storage Life calculations.Therefore, application of Vr;c or turning offthe oscillator can extend the effective Back-up Systemlife.Predicting Storage LifeFigure 10 illustrates how temperature affectsStorage Life of the MK48T02112 battery. As long asVee is applied or the oscillator is turned off, the lifeof the battery is controlled by temperature and isvirtually unaffected by leakage currents drawn bythe MK48T02I12.A Special Note: The summary presented inFigure 10 represents a conservative analysisof the data presently available. While SGS­THOMSON is most likely in possession of thelargest collection of battery life data of this kindin the world, the results presented should notbe considered absolute or final; they can beexpected to change as yet more data becomesavailable. We believe that future read-pointsof life tests presently under way and improvementsin the battery technology itself will resultin a continuing improvement of these figures.Two end of life curves are presented in Figure 10.They are labeled '~verage" (t5Q%) and (t l%). Theseterms relate to the probability that a given numberof failures will have accumulated by a particularpOint in time. If, for example, expected life at 7O"Cis at issue, Figure 10 indicates that a particularMK48T02112 has a 1% chance of having a batteryfailure 11 years into its life and a 50% chance offailure at the 20 year mark. Conversely, given a sampleof devices, 1% of them can be expected to experiencebattery failure within 11 years; 50% of themcan be expected to fail within 20 years.The t l% figure represents the practical onset ofwear out, and is therefore suitable for use in whatwould normally be thought of as a worst-case analysis.The tsO% figure represents "normal" or "average"life. It is, therefore, accurate to say that theaverage device will last "tsO%".Battery life is defined as beginning on the date ofmanufacture. Each MK48T02112 is marked with afour digit manufacturing date code in the formYYWW (Example: 8625 = 1986, week 25).Storage Life predictions presented in Figure 10 areextrapolated from temperature accelerated life-testdata collected in over 100 million device hours ofcontinuing bare cell and encapsulated cell batterytesting by SGB-THOMSON. Obviously, temperatureaccelerated testing cannot identify non-temperaturedependent failure mechanisms. However, in viewof the fact that no random cell failures have beenrecorded in any of SGB-THOMSON's on going batterytesting since it began in 1982, we believe thechance of such failure mechanisms surfacing is extremelysmall. For the purpose of this testing, a cellfailure is defined as the inability of a cell stabilizedat 25"C to produce a 2.0 volt closed-circuit voltageacross a 250K ohm load resistance.calculating Predicted Storage Life of the BatteryAs Figure 10 indicates, the predicted Storage Lifeof the battery in the MK48T02I12 is a function of temperature.Because the ambient temperature profile is dependentupon application controlled variables, only theuser can estimate predicted Storage Life in a givendesign. As long as ambient temperature is heldreasonably constant, expected Storage Life can beread directly from Figure 10. If the MK48T02I12spends an appreciable amount of time at a varietyof temperatures, the following equation should beused to estimate Storage Life.Predicted Storage Life = __________ 1 _________ _[(TA1/TT)/SL11+[(TA~/SL21+··· +[(TAnITT)/SLnlWhere TAl' TA2, TAn = Time at Ambient Temperature 1, 2, etc.n = Total Time = TAl + TA2 + ... + TAnSL1, SL2, SLn = Predicted Storage Life at Temp 1, Temp 2, etc. (See Figure 10).9/14307

MK48T02112(B)-12115/20/25Example Predicted Storage life CalculationA cash registerlterminal operates in an environmentwhere the MK41IT02/12 is exposed to temperaturesof 300C (86°F) or less for 4672 hrslyr; temperaturesgreater than 25OC, but less than 40°C (104°F), for3650 hrslyr; and temperatures greater than 4OOC, butless than 700C (158°F), for the remaining 438 hrslyr.Reading predicted t1% values from Figure 10; SL1 = 456 yrs., SL2 = 175 yrs., SL3 = 11.4 yrs.Total Time (TTl = 8760 hrs./yr. TA1 = 4672 hrs./yr. TA2 =3650 hrs.lyr. TA3 = 438 hrs.lyr.Predicted Typical Storage Life ~ 1[(4672/8760)/456]+[(3650/8760)1175]+[(438/8760)/11.4]~ 126 yrs.FIGURE 10. MK48T02/12 PREDICTED BATTERY STORAGE LIFE VS. TEMPERATURE300200IJ)II:w1009080706050403020'" >109876520 40 50 60 70 8090OEGREES CELSIUS10114308

MK48T02112(B)-12/15/20/25~redlctlng Capacity Consumption Liferhe MK48T02112 interflal cell has a minimum rat-9d capacity of 35 mAh. The device places a nomi-1al combined RAM and TIMEKEEPER load of 1.2.A on a typical internal ':fT mAh lithium battery whenthe clock is running and the device is in BatteryBack-up mode. At that rate, the MK48T02I12 will consumethe cell's capacity in 29,166 hours, or about3.3 years. But, as Figure 11 shows, Capacity Consumptioncan be spread over a much longer periodof time.Because the ambient temperature profile is dependentupon application controlled variables, only theuser can estimate consumption rates in a given design.As long as ambient temperature is heldreasonably constant, expected Capacity Consumptionlife can be estimated by reading 0% Vcc DutyCycle Capacity Consumption life directly from Figure12, and dividing by the expected Vee Duty Cycle (Le.at 25"C with a 66% Duty Cycle, Capacity ConsumptionLife = 3.31(1-.66) = 9.5 years).Naturally, Back-up current varies with temperature. If the MK48T02/12 spends an appreciable amountAs Figure 12 indicates, the rate of Current Consumptionby the MK48T02I12 with the clock running tion provided in the previous Storage Life sectionof time at a variety of temperatures, the same equa­in Battery Back-up mode is a function of temperature.life.should be used to estimate Capacity ConsumptionExample Consumption Life CalculationTaking the same cash registerlterminal used earlier, let's assume that the high and low temperature periodsare the non-operating, Battery Back-up mode periods, and that the register is turned on 10 hours a dayseven days per week. The two points of interest on the curves in Figure 12 will be the 25°C and the70°C points.Reading Capacity Life values from Figure 12; CL1 = 3.3 yrs., CL2 = 3.55 yrs.Total Time (TT) = 8760 hrs./yr. TA1 = 4672 hrs./yr. TA2 = 438 hrs./yr.Capacity Life:2: _________ 1 ________ _:2: 5.69 yrs.Estimating Back-up System Life[(4672/8760)/3.3] + [(438/8760)/3.55]The procedure for estimating Back-up System I.ife issimple. Pick the lower of the two numbers. In the casecalculated in the examples, that would be 5.69 years.The fact is, since either mechanism, Storage Lifeor Capacity Consumption, can end the system's life,the end is marked by whichever occurs first.FIGURE 11. TYPICAL CAPACITY CONSUMPTION LIFE AT 25°C VS. Vcc DUTY CYCLE201025 50 75 100Vee ON (%)11114309

MK48T02112(B)-12/15/20/25FIGURE 12. CURRENT CONSUMPTION LIFE OVER TEMPERATURE WITH 0% Vcc DUTY CYCLEo 20 40 60 80DEGREES CELSIUSAPPLICATION NOTE:BINARY TO BCD, AND BCD TO BINARYCONVERSIONFIGURE 13. EQUIVALENT OUTPUT LOAD DIAGRAMThe MK48T02/12 presents and accepts TIMEKEEP­ER data in BCD format. Conversion to or from otherformats can be executed in a single line of code,as the following example BASIC program demonstrates.10 REM BINARY TO BCD20 DEF FNA (X)=INT (X/10)*16+X·INT(X/10)*1030 REM BCD TO BINARY40 DEF FNB (X)=INT (X/16)*10+(XAND15)AC TEST CONDITIONSInput Levels:Transition Times:Input and Output TimingReference Levels0.6 V to 2.4 V5 ns0.8 V or 2.2 VDEVICEUNDERTEST+sv~~ 1.8Kn,,100 pF~ 1.0 Kn?(INCLUDING SCOPE AND JIG)-=-~12114310

MK48TD2/12(B)-12115/20/25ABSOWTE MAXIMUM RATINGS'Voltage On Any Pin Relative To GND ...................................... -0.3 V to +7.0 VAmb!ent Operating (Vce On) Te.mperature (TA) ................................. O°C to +70OCAmbient Storage (Vcc Off, Oscillator Off) Temperature ........................ -20OC to +70OCTotal Device Power Dissipation .................................................... 1 WattOutput Current Per Pin .............. , ........................................... 20 mA'Stresses greater than. those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions forextended periods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(0°CsT A s70OC)SYMPARAMETERMINMAX UNITS NOTESVccSupply Voltage (MK48T02)4.755.50 V 1VccSupply Voltage (MK48T12)4.505.50 V 1GNDSupply Voltage00 V 1VIHLogic "1" Voltage All Inputs2.2Vcc + 0.3 V V 1VILLogic "0" Voltage All Inputs-0.30.8 V 1,2DC ELECTRICAL CHARACTERISTICS(0°CsT As+70°C) (Vcc (Max)~Vcc~Vcc (Min»SYMIcc1PARAMETERAverage V cc Power Supply CurrentIcc2 TTL Standby Current (E = VI H)ICC3 CMOS Standby Current (E = Vcc-0.2 V)IlL10LVOHVOLInput Leakage Current (Any Input)Output Leakage CurrentOutput Logic "1" Voltage (lOUT = -1D mA)Output Logic "0" Voltage (lOUT = 2.1 mA)MIN-1-52.4MAX UNITS NOTES80 mA 35 mA 43 mA 4+1 pA 5+5 pA 5V0.4 VCAPACITANCE (T A = 25°C)SYMCICOlOPARAMETERCapacitance on all pins (except D/O)Capacitance on D/O pinsMAX NOTES7 pF 610 pF 6,7NOTES1. All voltages referenced to GND.2. Negative spikes of -1.0 volts allowed for up to 10 ns once per cycle.3. ICC1 measured with outputs open.4. Measured with Control Bits set as follows: R ~ 1; W, ST, KS, FT ~ O.5. Measured with GNDsVI sVCC and outputs deselected.6. Effective capacitance calculated from the equation C ~ I~t with ~V ~ 3volts and power supply at 5.0 V.Vi:7. Measured with outputs deselected.13114311

MK48T02/12(B)-12/15/20/25PACKAGE DESCRIPTIONB PACKAGE 24 PINmm InchesDim. r---r--+---,-~--l NotesMin Max Min MaxBATTERY 0 - 32.893 - 1.295ONLY Z 13.97 14.478 .550 .570. A 8.128 9.652 .320 .380A2 7.62 9.144 .300 .360E, 13.462 13.97 .530 .5506 0.381 0.533 .015 .021 46, 1.143 1.778 .045 .070C 0.203 0.355 .008 .014 424 PIN 0, - 32.258 - 1.270 1PLASTIC E 13.462 16.256 .530 .640D.I.P. eA 15.24 17.78 .600 .700 3ONLY ., 2.286 2.794 .090 .110L 3.048 3.81 .120 .150A 0.381 0.762 .015 .030 2S 1.524 2.286 .OBO .0903. Measu.ed'rom centeflm8to cenlerlme at lead lips4. When the solder lead limsh 's spe

M K48Z08/18/09/19(B)·15/201258K x 8 ZEROPOWERTM RAM• PREDICTED WORST CASE BATIERY LIFE OF11 YEARS @ 7O"C• DATA RETENTION IN THE ABSENCE OFPOWER• POWER FAIL INTERRUPT OUTPUT(MK48Z09/19) OPEN DRAIN• EXTRA DATA SECURITY PROVIDED BY EAR·LY WRITE PROTECTION DURING POWERFAILURE (MK48Z08l09)• DIRECT REPLACEMENT FOR VOLATILE 8K x8 BYTE WIDE STATIC RAM• +5 VOLT ONLY READIWRITE• UNLIMITED WRITE CYCLES• JEDEC STANDARD 28 PIN MEMORY PINOUT• READ·CYCLE TIME EQUALS WRITE·CYCLETIME• TWO POWER·FAIL DESELECT TRIP POINTSAVAILABLEMK48Z08lO9: 4.75V

MK48Z08118/09119(B)-15/20/25PIN NAMESAo -A12 Address Inputs Vcc System Power (+5 V)E1, E2 Chip Enable W Write EnableGND Ground G . Output EnableDOo - D07 Data In/Data OutNCDESCRIPTIONNo ConnectINT Power Fail InterruptOutputThe MK48Z08/MK48Z181MK48Z09/MK48Z19 is a65,536-bit, Non-Volatile Stati.c RAM, organized 8Kx 8 using CMOS and an integral Lithium energysource. The ZEROPOWER'" RAM has the characteristicsof a CMOS static RAM, with the importantadded benefit of data being retained in the absenceof power. Data retention current is so small that aTRUTH TABLE MK48Z08I18Vee E G W MODE DQ POWERVcc VIL VI!. VIH Read DOUT Active(min)VIL VIH VIH Read High Z ActiveVSOsVSO X X X Deselect High Z BatteryBack-upMode""i:"';'

MK48Z08/18/09/19(B)-15/20/25OPERATIONRead ModeThe MK48Z08118/09119 is in the Read Modewhenever W (Write Enable) is high, E, (Chip Enable)is low, and E2 is high (MK48Z09/19), providinga ripple-through access of data from eight of 65,536locations in the static storage array. Thus, theunique address specified by the 13 Address Inputs(An) defines which one of 8,192 bytes of data is tobe accessed.Valid data will be available to the eight data OutputDrivers within tM after the last address input sig­!lal is stable, providing that the Chip Enable al1.QG access times are satisfied. If Chip Enable or Gaccess times are not met, data access will be measuredfrom the limiting parameter (tOEA or tCEA' ortCE'w, rather than the address. The state of theeight Data 1/0 signals is controlled by the Chip Enableand G control signals. The data linesmay be inan indeterminate state between tOH and tM , butthe data lines will always have valid data at tM .FIGURE 3. READ CYCLEE,READ CYCLEAC ELECTRICAL CHARACTERISTICS:O°C:5TA:5+70°C) (Vcc (min):5Vcc :5Vcc (max»MK48ZXX-15 MK48ZXX-20 MK48ZXX-2SSYM PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTESt RC Read Cycle Time 150 - 200 - 250 - nstM Address Access Time - 150 - 200 - 250 nstCEA1 E, Access Time - 150 - 200 - 250 nstCEA2 E2 Access Time - 150 - 200 - 250 nstOEA Output Enable to Output Valid - 75 - 100 - 125 nstCEL Chip Enable (E" E2) to 10 - 10 - 15 - nsOutput In Low-ZtOEL Output Enable to Output Low-Z 5 - 5 - 10 - nstCEZ Chip Enable (E" E 2) - 75 - 100 - 125 nsOutput In High-ZtOEZ Output Enable to Output High-Z - 60 - 80 - 100 nstOH Output Data Hold Time 20 - 20 - 25 - ns3/12315

MK48Z08/18/09/19(B)-15/20/25Write ModeThe MK48Z08/18/09/19 is in the Write Modewhenever the Vii and E, are low and E2(MK48Z09/19) is high. The start of a write is ~erencedto the latter occurring falling edge of W orE1, or the rising edge of E2 (MK48Z09119).~ writeis terminated by the earlier rising edge of W or E1or the falling edge of E2 (MK48Z09/19). The address~must be held valid throughout the cycle.E1 or W must return high or E2 (MK48Z09119) mustreturn low for a minimum of tWA prior to the initiationof another read or write cycle. Data-in must bevalid tos prior to the end of write and must remainvalid for tOH afterward.Because G is a Don't Care in Write Mode and a lowon Vii will return the outputs to High-Z, G can betied low and two-wire RAM control can be implemented.!-Alow on Vii will disable the outputstWEZ after W falls. Take care to avoid bus contentionwhen operating with two-wire control.FIGURE 4. WRITE CYCLE 1 (W CONTROLLED WRITE)Oq:O·OQ7COMMON 110D'N __________________ JFIGURE 5. WRITE CYCLE 2 (El CONTROLLED WRITE)00.-0°7COMMON 1/0OOUT------------~~~~--------~------------------4112316

MK48Z08118/09/19(B)-15/20/25AC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TIMING)(O"C sT AS +70"C)SYM PARAMETER MIN MAXtF VPFD (Max) to VpFD (Min) Vee Fall Time 300tFB VPFD (Min) to Vso Vee Fall Time 10tAB Vso to VpFD (Min) Vee Rise Time 1tR VpFD (Min) to VpFD (Max) Vee Rise Time 0tREe E1 or W at V1H or E2 at V1L after Power-Up 120tpFX INT Low to Auto Deselect 10 40tpFH VPFD (Max) to INT High 120tFB VPFD (Min) to Vso 10UNITS NOTES,.s 2,.s 3,.s,.s,.s,.s,.s 4,.sDC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TRIP POINT VOLTAGES)(O"C sT AS + 70 "C)SYM PARAMETER MIN TYPVPFD Power-fail Deselect Voltage (MK48Z08l09) 4.50 4.6VPFD Power-fail Deselect Voltage (MK48Z18119) 4.20 4.3Vso Battery Back-up Switchover Voltage 3MAX4.754.50UNITS NOTESV 1V 1V 1NOTES:1. All voltages referenced to GND.2. VpFD (Max) to VpFD (Min) fall times of less tF may result in deselectioniwriteprotection not occurring until 40 ,.s after Vee passes VpFD (Min). VpFD(Max) to (Min) fall times of less than 10 ¢l may cause corruption of RAM data.3. VpFD (Min) to VSO fall times of less than tFB may cause corruption of RAMdata.4. INT may go high anytime after Vee exceeds VpFD (min) and is guaranteedto go high tpFH after Vee exceeds VpFD (max).CAUTIONNegative Undershoots Below -0.3 volts are not allowedon any pin while in Battery Back-up mode.6112318

MK48Z08118/09119(B)-15/20/25FIGURE 7. POWER DOWN/POWER-UP TIMINGV". (MAX)- -V ... (MIN)- -VIO - -- ~t,.INT ~(MK48Z09119 ONLY) 1'-=-------f1lALL INPUTS RECOGNIZED DON'T CARE RECOGNIZEDALL VALID VALIDOUTPUTS (PER CONTROL INPUT) I}--------i f--HIGH.z---------(J (PER CONTROL INPUT)NOTE:Inputs mayor ml\X.Dot !2§ recognized at this time. Caution shouldbe taken to keep El or W In the high state or E2 tow as VCC risespast VpFD (min). Some systems may perform inadvertant,INritecycles after Vee rises but before normal system operation begins.Even though a power on reset Is being applied to the processora resa! cond~ion may not occur until alter the system clock Isrunning.Power Fall and Data RetentionWith Vee applied, the MK48Z08l18109J19 operatesas a static RAM. The Power-Fail Detect Circuit ofthe MK48Z08/18109J19 constantly monitors Vee.Because the reference voltage applied to the detectorlcomparatoris stabilized over temperature, thePower~Faii Detect trip pOint remains within theV PFD min/max window under all rated conditions.Once deselection has occurred, all inputs and outputsare "Don't Cares" alid may have anywherefrom -0.3 to 5.5 volts applied to them with absolutelyno effect upon the RAM.As Vee falls below approximately Vso volts, thepower switching circuit connects the lithium batteryto supply power to the RAM.The power switching circuit connects external Vecto the RAM and disconnects the battery when Veerises above approximately Vso volts. Normal RAMoperation can resume tREC after Vee reaches V PEQ(max). Caution should be taken to keep E 1, or Win the high state or E2 low as Vee rises past V PFD(min). Some systems may perform inadvertant writecycles after Vcc rises but before normal systemoperation begins.INTERRUPT FUNCTIONThe MK48Z09I19 provides a power-fail interrupt outputlabeled INT. The INT pin eliminates the needfor external power sensing components in applicationswhere an orderly shutdown of the system isnecessary: The INT pili is open drain for "wire or"applications and provides the user with 10 P.s to 40P.s advanced warning of an impending power-failwrite protect.7112319

MK48Z08118/09119(B)-15/20/25DATA RETENTION TIMEAbout Figure 8Figure 8 illustrates how expected MK48Z08l18109119battery life is influenced by temperature. The lifeof the battery is controlled by temperature and isvirtually independent of the percentage of time theMK48Z08/18/09/19 spends in battery back-up mode.Battery life predictions presented in Figure 8 areextrapolated from temperature accelerated life-testdata collected in over 100 million device hours pfcontinuing bare cell and encapsulated cell batterytesting by SGS.:rHOMSON. Obviously, temperatureaccelerated testing cannot identify non-temperaturedependent failure mechanisms. However, in viewof the fact that no random cell failures have beenrecorded in any of SGS-THOMSON's ongoing batterytesting since it began in 1982, we believe thelikelihood of such failure mechanisms surfacing isextremely poor. For the purpose of this testing, acell failure is defined as the inability of a cell stabilizedat 25"C to produce a 2.4 volt closed-circuit voltageacross a 250K ohm load resistance.A Special Note: The summary presented inFigure 8 represents a conservative analysisof the data presently available. While SGS­THOMSON is most likely in possession of thelargest collection of battery life data of this kindin the world, the results presented should notbe considered absolute or final; they can beexpected to change as yet more data becomesavailable. We believe that future read-pointsof life tests presently under way and improvementsin the battery technology itself will resultin a continuing improvement of these figures.Two end of life curves are presented in Figure 8.They are labeled ''Average (t50%)" and "(tl%)'"These terms relate to the probability that a givennumber of failures will have accumulated by a particularpoint in time. If, for example, expected lifeat 70°C is at issue, Figure 8 indicates that a particularMK48Z08/18/09/19 has a 1% chance of havinga battery failure 11 years into its life and a 50%chance of failure at the 19 year mark. Conversely,given a sample of devices, 1% of them can be expectedto experience battery failure within 11 years;50% of them can be expected to fail within 19 years.The t 1% figure represents the practical onset ofwear-out, and is therefore suitable for use in whatwould normally be though of as a worst-case analysis.The t50% figure represents "normal" or "average"life. It is, therefore, accurate to say that theaverage device will last "t50%'"Battery life is defined as beginning on the date ofmanufacture. Each MK48Z08/18/09/19 is markedwith a four digit manufacturing date code in the formYYWW (Example: 8502 = 1985, week 2).Calculating Predicted Battery LifeAs Figure 8 indicates, the predicted life of the batteryin the MK48Z08118/09119 is a function of temperature.The back-up. current required by thememory matrix in the MK48Z08/18/09119 is so lowthat it has negligible influence on battery life.Because predicted battery life is dependent uponapplication controlled variables, only the user canestimate predicted battery life in a given design. Aslong as ambient temperature is held reasonablyconstant, expected life can be read directly fromFigure 8. If the MK48Z08l18/09/19 spends an appreciableamount of time at a variety of temperatures,the following equations should be used toestimate battery life.Predicted Battery Life = __________ 1 ________ _[(TA1ITT)/BL1)]+[(TA2ITT)/BL2]+··· +[(TAn/TT)/BLn)]Where TAl, TA2, TAn = Time at Ambient Temperature 1, 2, etc.n = Total Time = TAl + TA2 + ... + TAnBL 1, BL2, BLn = Predicted Battery Lifetime at Temp 1, Temp 2, etc. (see Figure 8).EXAMPLE PREDICTED BATTERY LIFE CALCULATIONA cash registerlterminal operates in an environmentwhere the MK48Z08l18109/19 is exposed to temperaturesof 30°C (86°F) or less for 3066 hrs/yr; tem­peratures greater than 25°C, but less than 4O"C(104 OF), for 5256 hrs/yr; and temperatures greaterthan 40°C, but less than 70°C (158°F), for the remaining438 hrs/yr.Reading predicted t1% life values from Figure 8; BLI = 300 yrs., BL2 = 175 yrs., BL3 = 11.4 yrs.Total Time (TT) = 8760 hrs.lyr. TAl = 3066 hrs./yr. TA2 =5256 hrs./yr. TA3 = 438. hrs.lyr.Predicted Battery Life ~ 1[(3066/8760)/300)+[(5256/8760)/175]+[(438/8760)/11.4]~ 111.3 yrs.8/12320

MK48Z08118/09/19(B)-15/20/25FIGURE 8. MK48Z08118/09/19 PREDICTED BATTERY LIFE VS TEMPERATURE20 40 50 60 70 80 90DEGREES CELSIUS9/12321

MK48Z08118/09119(B)-15/20/25ABSOWTE MAXIMUM RATINGS·Total Power Dissipation ......................................................... 1.0 wattOutput Current Per Pin .......................................................... 10 mAVoltage On Any Pin Relative To GND ...................................... -0.3 V to +7.0 VAmb!ent Operating (V CQ. On) Temperature (T A) ................................. O°C to +70:CAmbient Storage (Vcc Off) Temperature .................................... -40OC to +85 C·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.CAUTION: Under no conditions can the ''Absolute Maximum Rating" for the voltage on any pin be exceeded sinceit will cause permanent damage. Specifically, do not perform the "standard" continuity test on any input or output pin,i.e do not force these pins below -0.3 V DC.RECOMMENDED DC OPERATING CONDITIONS(OOCsTAS70°C)SYM PARAMETERMIN MAXVcc Supply Voltage (MK48Z08l09)4.75 5.50Vcc Supply Voltage (MK48Z18119)4.50 5.50GND Supply Voltage0 0VIH Logic "1" Voltage All Inputs 2.2 IVcc + 0.3 VVIL Logic "0" Voltage All Inputs-0.3 0.8UNITS NOTESV 1V 1V 1V 1V 1,2DC. ELECTRICAL CHARACTERISTICS(OOCsT A s+70OC) (Vcc (min) sVcc sVcc (max»SYM PARAMETERICClICC2Average V cc Power Supply CurrentTTL Standby Current (El = VIH or E2 = VIJICC3 CMOS Standby Current (El

MK48Z08/18/09l19(B)-15/20/25AC TEST CONDITIONSFIGURE 9. OUTPUT LOAD DIAGRAMInput Levels:Transition Times:Input and Output TimingReference LevelsAmbient TemperatureVee MK48Z08/09Vce MK48Z18/190.6 V to 2.4 V5 ns0.8 V or 2.2 VO°C to 7Q°C4.75 V to 5.5 V4.5 V to 5.5 VDEVICEUNDERTEST+5V

MK48Z08/18/09/19(B)-15/20/25PACKAGE DESCRIPTIONB PACKAGE 28 PIN-M~v 'l.I' 'l.I' 'l.I'141f+-__ ~ ___ Dl~BATTERYONLYDIP-28PLASTICOJ.P.ONLYDim.0ZAA2E,66,C0,EeAe,LA,SmmInche.Min Max Min Max- 37.973 - 1.49513.97 14.478 .550 .5708.128 9.652 .320 .3807.62 9.144 .300 .36013.462 13.97 .530 .5500.361 0.533 .015 .0211.143 1.778 .045 .0700.203 0.355 .008 .014- 37.336 - 1.47013.462 16.256 .530 .64015.24 17.78 .500 .7002.265 2.794 .090 .1103.046 3.81 .120 .1500.361 0.762 .015 .0301.524 2.286 .060 .090~--------E-------~Notes44132NOTES:1. Lead finish is to be specified on the detail specifications.2. Overall length includes .010 in. flash on either end of the package.3. Package standoff'to be measured per JEDEC requirements.4. Measured from centerline to centerline at lead tips.5. When the solder lead finish is specified, the maximum limit shallbe increased by .003 in.12/12324

t=-: SGS-THOMSONIt., L ~O©OO@~[!,[~©'U'oo@~o©~MKI48Z02/12(B)-15/20/252K x 8 ZEROPOWERTM RAM• INDUSTRIAL TEMPERATURE RANGE -40°Cto +85°C• PREDICTED WORST CASE BATTERY LIFE OF6 YEARS @ 85 OC• DATA RETENTION IN THE ABSENCE OFPOWER• DATA SECURITY PROVIDED BY AUTOMATICWRITE PROTECTION DURING POWERFAILURE• +5 VOLT ONLY READIWRITE• CONVENTIONAL SRAM WRITE CYCLES• LOW POWER-440 mW ACTIVE; 5.5 mWSTANDBY• 24-PIN DUAL IN LINE PACKAGE, JEDEC 24 PINMEMORY PINOUT• READ-CYCLE TIME EQUALS WRITE-CYCLETIME• ON BOARD LOW-BATTERY WARNING CIR­CUITRY• TWO POWER-FAIL DESELECT TRIP POINTSAVAILABLEMK148Z02 4.75V~VPFD~4.50VMKI48Z12 4.50V~VPFD~4.20VR/WPart Number Access Time Cycle TimeMK148ZX2-15 150 ns 150 nsMK148ZX2-20 200 ns 200 nsMKI48ZX2-25 250 ns 250 nsBDIP-24(Plastic with Battery Top Alt)FIGURE 1_ PIN CONNECTIONSA7 1 24 VeeAs 2 23 AsAs 3 22 AgA4 4 21 ViA3 5 20 GA2 6 19 A,oA, 7 18 EAo 8 17 DQ7DQo 9 16 DQsDQ, 10 15 DQsDQ2 11 14 DQ4GND 12 13 DQ3TRUTH TABLE (MKI48Z02/12)Vcc E Cl W MODE DQVIH X X Deselect High-ZVee (Min) VIL VIL VIH Read DOUTVIL VIH VIH Read High-ZVsoDeselectsVso X X X Battery High-ZBack-upPIN NAMESAo - A10 Address Inputs Vee System Power (+5 V)E Chip Enable W Write EnableGND Ground G Output EnableDao-Da7 Data InlData OutJune 19881/11325

MKI48Z02112(B)-15/20/25DESCRIPTIONThe MKI48Z02112 is a 16,384-bit, Non-Volatile StaticRAM, organized 2K x 8 using CMOS and an integralLithium energy source. The ZEROPOWER"'RAM has the characteristics of a CMOS static RAM,with the important added benefit of data beingretained in the absence of power. Data retention currentis so small that a miniature Lithium cell containedwithin the package provides an energysource to preserve data. Low current drain has beenattained by the use of a full CMOS memory cell,novel analog support circuitry, and carefully controlledjunction leakage by an all implanted CMOSprocess. Safeguards against inadvertent data losshave been incorporated to maintain data integrityin the uncertain operating environment associatedwith power-up and power-down transients. TheZEROPOWER RAM can replace existing 2K x 8static RAM, directly conforming to the popular ByteWide 24-pin .DIP package (JEDEC). MKI48Z02/12also matches the pinning of 2716 EPROM and 2Kx 8 EEPROM. Like other static RAMs, there is nolimit to the number of write cycles that can be performed.Since the access time, read cycle, and writecycle are less than 250ns and require only +5 volts,no additional support circuitry is needed for interfaceto a microprocessor.FIGURE 2. BLOCK DIAGRAMrIIIIIIIII L __ _I LITHIUMCELLr---I-----I~---.... POWERVOLTAGE SENSEANDSWITCHINGCIRCUITRY2Kx8RAMCMOSCELL........... ----1_ _____ .J'--~_....JAD-Al0II EW~_-!..I_- GIDQO-DQ72111 ~ SCiS·DlOMSON. .., I ;,;]O©OO@~~~©"iiIiil@~O©$326

MKI48Z02/12(B)-15/20/25OPERATIONRead ModeThe MK148Z02/12 is in the Read Mode wheneverW (Write Enable) is high and E (Chip Enable) is low,providing a ripple-through access of data from eightof 16,384 locations in the static storage array. Thus,the unique address specified by the 11 Address Inputs(An) defines which one of 2,048 bytes of datais to be accessed.Valid data will be available to the eight data OutputDrivers within tAA after the last aQ..dress input signalis stable, providin.9 th~ the E and G accesstimes are satisfied. If E or G access times are notmet, data access will be measured from the limitingparameter (tCEA or tOEA)' rather than the address.The state"pf the eight Data I/O signals iscontrolled by the E and G control signals. The datalines may be in an indeterminate state between IoHand tAA, but the data lines will always have validdata at tAA.FIGURE 3. READ-READ-WRITE TIMINGREADIRe~ ~IReREAD'weWRITE--r-IeEAi -IAA-1 -- r-- lAS 'wR1l -I IAw---jCwDOo-D0 7 ---------

M KI48Z02112(B)-15/20J25WRITE MODEThe MK148Z02112 is in Write Mode whenever the Wand E inputs are held low. The start of a Write isreferen.£ed .!9 the latter occurring falling edge ofeither Wor E. A Wrl!e is terminated by the earlierrising edge of W or E. The addresses must be heldvalid throughout the cycle. W or E must return highfor a minimum of tWA prior to the initiation ofanother Read or Write Cycle. Data-in must be validfor tos prior to the End of Write and remain validfor tOH afterward.Some processors thrash producing spurious WriteCycles during power-up, despite l!Ppli~tion of apower-on reset. Users should force W or E high duringpower-up to protect memory after Vee reachesVec (min) but before the processor stablizes.The MKI48Z02/12 G input is a DON'T CARE in thewrite mode. G can be tied low and two-wire RAMcontrol can be implemented:.1\ low on W will disablethe outputs tWEZ after W falls. Take care toavoid bus contention when operating with two-wirecontrol.FIGURE 4. WRITE-WRITE-READ TIMINGWRITEWRITEREADtWEZhrOUTININVALIDOUTAC ELECTRICAL CHARACTERISTICS (WRITE CYCLE TIMING)(-40°C:s;TA:s;+85°C) (Vec (Max) 2: Vee 2: Vee (Min»MK148ZX2·15 MK148ZX2·20 MK148ZX2·25SYM PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 150 200 250 nstAS Address Setup Time 0 0 0 nstAW Address Valid to End of Write 120 140 180 nstCEW Chip Enable to End of Write 90 120 160 nstWEVI Write Enable to End of Write 90 120 160 nstWA Write Recovery Time 10 10 10 nstos Data Setup Time 40 60 100 nstOH Data Hold Time 0 0 0 nstWEZ Write Enable Low to High-Z 50 60 80 ns4111328

MKI48Z02112(B)-15/20/25DATA RETENTION MODEWith Vee applied, the MKI48Z02I12 operates as aconventional BYTEWIDE static ram. However, Veeis being constantly monitored. Should the supplyvoltage decay, the RAM will automatically powerfaildeselect, write protecting itself when Vee fallswithin the VPFD (max), VPFD (min) window. TheMK148Z02 has a VPFD (max) to VPFD (min) windowof 4.75 volts to 4.5 volts, providing very high datasecurity, particularly when all of the other systemcomponents are specified to 5.0 volts plus and minus10%. The MKI48Z12 has a VPFD (max) to VPFD(min) window of 4.5 volts to 4.2 volts, allowing usersconstrained to a 10% power supply speCificationto use the device.FIGURE 5. CHECKING THE BOK FLAG STATUSREAD DATAAT ANYADDRESSNote: A mid-write cycle power failure may corruptdata at the current address location, but does notjeopardize the rest of the RAM's content. N. voltagesbelow VPFD (min), the user can be assured thememory will be in a write protected state, providedtheycc_ ~all time does not exceed tF. TheMKI48Z02/12 may respond to transient noise spikesthat reach into the deselect window if they shouldoccur during the time the device Is sampling Vex;.Therefore decoupling of power supply lines ISrecommended.The power switching circuit connects external Veeto the RAM and disconnects the battery when Veerises above Vso' As Vee rises the battery voltageis checked. If the voltage is too low, an internal BatteryNot OK (Brn

MKI48Z02/12(B.)-15/20/25FIGURE.6. POWER-DOWNIPOWER-UP TIMINGVee --------..V. FO (MAX) - -V. FO (MIN) - -tAEorVVDC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TRIP POINT VOLTAGES)(-40°C :sTA:s +85°C)SYM PARAMETER MIN TYP MAXVpFD Power·fail Deselect Voltage (MK148Z02) 4.50 4.6 4.75VPFD Power-fail Deselect Voltage (MK148Z12) 4.20 4.3 4.50V"" Batte_ry Back-up Switchover Volt~e 3UNITS NOTESV 1V 1V 1AC ELECTRICAL CHARACTERISTICS (POWER-DOWN/POWER-UP TIMING)(-40°C :sT A:S +85 OC)SYM PARAMETER MINtpD E or W at V IH before Power Down 0tF VPFD (Max) to VpFD (Min) Vee Fall Time 300tFB VPFD (Min) to Vso Vee Fall. Time 10tRB Vso to VPFD (Min) Vee Rise Time 1tR VpFD (Min) to VpFD (Max) Vee Rise Time 0tREe E or W at V IH after Power Up 2NOTES:1. All voltages referenced to GND.2. VpFD (Max) to VPFD (Min) fall times of less tF may result in deselectionlwriteprotection not occurring until 50 I'S after Vee passes VpFD (Min). VpFD(Max) to (Min) fall times of less than 10,,5 may cause corruption of RAM data.3. VpFD (Min) to VSO fall times of less than tFB may cause corruption of RAMdala.MAXUNITS NOTESnsp's 2p's 3p.Sp'smsCAUTIONNegative undershoots below -0.3 volts are not allowedon any pin while in Battery Back-up mode.6/11330

MKI48Z02/12(B)-15/20/25DATA RETENTION TIMEAbout Figure 7Figure 7 illustrates how expected MKI48Z02/12 batterylife is influenced by temperature. The life of thebattery is controlled by temperature and is virtuallyindependent of the percentage of time theMKI48Z02/12 spends in battery back-up mode.Battery life predictions presented in Figure 7 areextrapolated from temperature accelerated life-testdata collected in over 100 million device hours ofcontinuing bare cell and encapsulated cell batterytesting by SGS.:rHOMSON. Obviously, temperatureaccelerated testing cannot identify non-temperaturedependent failure mechanisms. However, in viewof the fact that no random cell failures have beenrecorded in any of SGS.:rHOMSON's ongoing batterytesting since it began in 1982, we believe thelikelihood of such failure mechanisms surfacing isextremely poor. For the purpose of this testing, acell failure is defined as the inability of a cell stabilizedat 25"C to produce a 2.0 volt closed-circuit voltageacross a 250K ohm load resistance.A Special Note: The summary presented inFigure 7 represents a conservative analysis ofthe data presently available. While SGS­THOMSON is most likely in possession of thelargest collection of battery life data of this kindin the world, the results presented should notbe considered absolute or final; they can be expectedto change as yet more data becomesavailable. We believe that future read-points oflife tests presently under way and improvementsin the battery technology itself will result in a continuingimprovement of these figures.Two end of life curves are presented in Figure 7.They are labeled "Average (t50%)" and "(tl%)".These terms relate to the probability that a givennumber of failures will have accumulated by a particularpoint in time. If, for example, expected lifeat 80"C is at issue, Figure 7 indicates that a particularMK148Z02l12 has a 1% chance of having a batteryfailure 10 years into its life and a 50% chanceof failure at the 17 year mark. Conversely, given asample of devices, 1% of them can be expected toexperience battery failure within 10 years; 50% ofthem can be expected to fail within 17 years.The t 1% figure represents the practical onset ofwear-out, and is therefore suitable for use in whatwould normally be though of as a worst-case analysis.The t50% figure represents "normal" or "average"life. It is, therefore, accurate to say that theaverage device will last "t50%".Battery life is defined as beginning on the date ofmanufacture. Each MK148Z02/12 is marked with afour digit manufacturing date code in the formYYWW (Example: 8502 = 1985, week 2).Calculating Predicted Battery LifeAs Figure 7 indicates, the predicted life of the batteryin the MKI48Z02112 is a function of temperature.The back-up current required by the memorymatrix in the MKI48Z02/12 is so low that it hasnegligible influence on battery life.Because predicted battery life is dependent upon applicationcontrolled variables, only the user can estimatepredicted battery life in a given design. As longas ambient temperature is held reasonably constant,expected life can be read directly from Figure 7. Ifthe MK148Z02l12 spends an appreciable amount oftime at a variety of temperatures, the follOWing equationsshould be used to estimate battery life.Predicted Battery Life = _________ 1 _________[(TA 1/TT)/BL 1)]+[(TA2/TT)/BL2]+··· +[(TAn/TT)/BLn)]Where TAl' TA2' TAn = Time at Ambient Temperature 1, 2, etc.TT = Total Time = TAl + TA2 + ... + TAnBL 1, BL2, BLn = Predicted Battery Lifetime at Temp 1, Temp 2, etc. (see Figure 7).EXAMPLE PREDICTED BATTERY LIFE CALCULATIONA process control computer operates in an environmentwhere the MK148Z02/12 is exposed to temperaturesof 50°C or less for 3066 hrs/yr; temperaturesgreater than 25 "C, but less than 6O"C, for 5256hrs/yr; and temperatures greater than 4O"C, but lessthan 85°C, for the remaining 438 hrs/yr.Reading predicted typical life values from Figure 7; BLl = 275 yrs., BL2 = 95 yrs., BL3 = 32 yrs.Total Time (TT) = 8760 hrs./yr. TAl = 3066 hrs./yr. TA2 =5256 hrs./yr. TA3 = 438 hrs./yr.Predicted Typical Battery Life ~ _________ 1 ________ _[(3066/8760)/275] +[(5256/8760)/95] +[(43818760)132]~ 109.2 yrs.7/11331

MKI48Z02/12(B)-15/20/25FIGURE 7. MK148Z02/12 PREDICTED BATTERY STORAGE LIFE VS TEMPERATUREDEGREES CELSIUS8111332

MKI48Z02/12(B)-15/20/25ABSOWTE MAXIMUM RATINGS·Voltage On Any Pin Relative To GND ...................................... -0.3 V to +7.0 VAmbient Operating (VcQ. On) Temperature (T A) ........................•..... -40°C to +S5°CAmbient Storage (VQ.c Off) Temperature .................................... -40°C to +S5°CTotal Device Power Dissipation .................................................... 1 WattOutput Current Per Pin .......................................................... 20 mA'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This Is a stress rating only and functional operation of the device at these or any other conditions above those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.CAUTION: Under no conditions can the "Absolute Maximum Rating" for the voltage on any pin be exceeded sinceIt will cause permanent damage. Specifically, do not perform the "standard" continuity test on any input or output pin,I.e do not force these pins below -0.3 V DC.RECOMMENDED DC OPERATING CONDITIONS(-40OCsT As +S5OC)SYMPARAMETERMINMAX UNITS NOTESVeeSupply Voltage (MKI48Z02)4.755.50 V 1VccSupply Voltage (MKI48Z12)4.505.5 V 1GNDVIHSupply VoltageLogic "1" Voltage All Inputs02.20 V 1Vcc + 0.3 V V 1VILLogic "0" Voltage All Inputs-0.3O.S V 1,2DC ELECTRICAL CHARACTERISTICS(-40OCsT A s+S5OC) (Vcc (max);::Vcc;::Vcc (min»SYMICClIcc2PARAMETERAverage V cc Power Supply CurrentTTL Standby Current (E = VIH)ICC3 CMOS Standby Current (E;::Vcc -0.2 V)IlLIOLVOHVOLInput Leakage Current (Any Input)Output Leakage CurrentOutput Logic "1" Voltage (lOUT = -1.0 mA)Output Logic "0" Voltage (lOUT = 2.1 mA)CAPACITANCE (T A = 25°C)SYMPARAMETERCI Capacitance on all pins (except 0/0)COlOCapacitance on 0/0 pinsMIN-1-52.4MAX UNITS NOTESso mA 33 mA1 mA+1 pA 4+5 pA 4V0.4 VMAXNOTES7 pF 510 pF 4,5NOTES1. All voltages referenced to GND.2. Negative spikes of -1.0 volts allowed for up to 10 ns once per cycle.3. ICC1 measured with outputs open.4. Measl.!red with GNDsVISVCC and outputs deselected.5. Effective capacitance calculated from the equation C = l.1t with.1V = 3volts and power supply at nominal level. .1V9/11333

MKI48Z02112(B)-1S/20/2SAC TEST CONDITIONSInput Levels:Transition Times:Input and Output TimingReference LevelsAmbient TemperatureVee (MKI48Z02)Vee (MKI48Z12)0.6 V to 2.4 V5 ns0.8 V or 2.2 V-40"0 to+85"04.75 V to 5.50V4.5 V .to 5.50 VFIGURE 8. OUTPUT LOAD DIAGRAM+5V.(~ 1.BKODEVICEUNDERTEST1.0 Kll" f:; 100 pF~ (INCWDING SCOPE AND JIG)":.=-ORDERING INFORMATIONMKI48ZDEVICEFAMILYxVee RANGE2BPACKAGE-xxSPEEDL-15 150 NS ACCESS TIME-20 200 NS ACCESS TIME-25 250 NS ACCESS TIMEBPLASTIC WITH BATTERYlOP HATo +10%1-5%1 +10%1-10%MKI Industrial Temp. Range-40"0 to +85"010111334

MKI48Z02112(B)-15/20/25PACKAGE DESCRIPTIONB PACKAGE 24 PINDim.mmMin Max MinBATIERY D - 32.893 -ONLY Z 13.97 14.478 .550A 8.128 9.652 .320A2 7.62 9.144 .300E1 13.462 13.97 .5308 0.381 0.533 .01581 1.143 1.778 .045C 0.203 0.355 .00824 PIN D1 - 32.258 -PLASTIC E 13.462 16.256 .530D.I.P. eA 15.24 17.78 .600ONLY 61 2.286 2.794 .090L 3.048 3.81 .120A1 0.381 0.762 .015S 1.524 2.286 .060InchesMax1.295.570.380.360.550.021.070.0141.270.640.700.110.150.030.090Notes44132~-------E------~~Irr='~1~====~ I======:>J, A A,_1 l _'------Jo..-~NOTES:1. Overall length includes .010 In, flash on either end of the package.2. Package standoff to be measured per JEOEC requirements.3. Measured from centerline to centerline al lead lips.4. When the solder lead finish is specified, the maximum limit shall be increasedby .003 in.11/11335

~ SGS-THOMSON..""! L ~o©oo@rn[!J~©[],oo@[h'!]O©~ MK48T08 (8)-10/12/15/208K x 8 ZEROPOWERTIMEKEEPER RAMADVANCED DATAIII INTEGRATED ULTRA LOW POWER SRAM,REAL TIME CLOCK, CRISTAL, POWER-FAILCONTROL CIRCUIT AND BATTERY• BYTEWIDETM RAM-LIKE CLOCK ACCESS• BCD CODED YEAR, MONTH, DAY DATE,HOURS, MINUTES AND SECONDS• SOFTWARE CONTROLLED CLOCKCALIBRATION FOR HIGH ACCURACY APPLI­CATIONS• PREDICTED WORST CASE BATTERYSTORAGE LIFE OF 11 YEARS @ 70°C• PIN AND FUNCTION COMPATIBLE WITHJEDEC STANDARD 8K X8 SRAMs• AUTOMATIC POWER-FAIL CHIPDESELECTIWRITE PROTECTIONBDIP-28(Plastic with Battery Top Hat)PIN CONNECTIONSPart Number Access Time R/W Cycle TimeMK48T08-10 100 '1S 100 '1sN CveeA12ViA? NCA 6 4 ASMK48T08-12 120 '1S 120 '1SASA9MK48T08-15 150 '1S 150 '1sMK48T08-20 200 '1S 200 '1SA4 6 AllA3AI 8 Al0AlAOGEDO?PIN NAMESAO-A12EGNDNCVeeWGDOO-D07ADDRESS INPUTSCHIP ENABLEGroundNO CONNECTION+5 VOLTSWRITE ENABLEOUTPUT ENABLEDATA INIDATA OUT000 DOGDOlD02Da~GND DO 35.1067 1June 1988This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.1/13337

MK48T08 (8)-10/12/15/20TRUTH TABLE MK48T08Vcc E G W MODE DQ POWERVIH X X Deselect High-Z Standby

MK48T08 (8)-10/12/15/20READ MODEThe MK48T08 is the RE11id Mode whenever IN (WriteEnable) is high and E (Chip Enable) is low. Thedevice architecture allows ripple-through access toany of the 8192 address locations in the static storagearray. Valid data will be available at the Data1/0 pins within tAA after the last ~dres~nput signalis stable, providing that the E and G accesstimes are satisfied.If E or G access times are not yet met, valid datawill be available at the latter of Chip Enable AccessTime (tCEAl or at Output Enable Access Time(tOEAl. The state of the,Jlight !bree-state Data 1/0signals is controlled by E and G. If the Outputs areactivated before tAA, the data lines will be drivento an indeterminate stateJ,lntii tAA. If the Addressinputs are changed while E and G remain low, outputdata will remain valid for Output Data Hold Time(tOH) but will go indeterminate until the nextAddress Access.FIGURE 2. READ CYCLE TIMINGREAD READ WRITEt AVAVt AVAVI AVONr-··~ I IWHAXAVWLI AVWH ,:----------*-

MK48T08 (8)-10112115/20WRITE MODEThe MK48T08 is in the Write Mode whenever Viiand E control lines are low. The start of a write is~fereJJced to the latter occurring falling edge ofW or E. A wri~ is terminated by the earlier risingedge of W or E. The ac;Ldre~es must be held validthroughout the cycle. E or W must return high forminimum of tWR prior to the initiation of anotherread or write cycle. Data-in must be valid tos priorto the end of write and remain valid for tOH afterward.Because G is a Don't Care in the Write Mode anda low on Vii will return the outputs to High-Z, G canbe tied low and two-wire RAM control can be implemented.A low on Vii will disable the outputstWEz after W falls. Take care to avoid bus contentionwhen operating with two-wire control.FIGURE 3. WRITE CYCLE TIMINGWRITE WRITE READt AVAYt AVAVI AVAVt AVavt OLavI WHDXAC ELECTRICAL CHARACTERISTICS (WRITE CYCLE)(O°C:s; TA :s; +70°C, Vcc=5.0 V+10%/-5%)ALT. STD. MK4STOS-10 MK4STOS-12PARAMETERSYM. SYM. MIN MAX MIN MAXMK4STOS-15MK4STOS-20MIN MAX MIN MAXUNITS NOTEtwc tAVAV Write Cycle Time 100 120tAS tAVWL Address Setup Time Vii Low 0 0tAS tAVEL Address Setup Time E Low 0 0tCEw tELEH Chip Enable to End of Write 80 100tAW tAVWH Add. Valid to End of Write 80 100tAW tAVEH Add. Valid to End Write 80 100tWEw WLWH Write Pulse Width 50 70ttCEZ tEHQZ E Data Off Time 50 60tWEZ tWLQZ Vii Data Off Time 50 60150 200 ~s0 0 ~s0 0 ~s130 180 ~s130 180 ~s130 180 ~s100 150 ~s75 100 ~s57 100 ~s4/13'340

MK48T08 (8)-10/12/15/20AC ELECTRICAL CHARACTERISTICS (WRITE CYCLE) (Continued)(O°C:5 TA :5 +70oC, VCC=5.0 V+10%/-5%)ALT. STD. MK48T08·10 MK48T08·12 MK48T08·15PARAMETERSYM. SYM. MIN MAX MIN MAX MIN MAXMK48T08·20MINMAXUNITS NOTEtWR tWHAX W High to Address Change 10 10 10tWR tEHAX E High to Address Change 10 10 10tWR WHWL W High to W Low next Cycle 10 10 10tos tOVWH Data Setup Time to W High 50 60 70tos tOVEH Data Setup Time to E High 50 60 70tOH tWHOX Data Hold Time W High 5 5 5, tOH tEHOX Data Hold Time E High 5 5 510 1)S10 1)510 1)S80 1)580 1)55 1)55 1)5AC TEST CONDITIONSFIGURE 4. OUTPUT LOAD DIAGRAMInput Levels: O.6V to 2.4V+5VTransition Times: 5 ns rInput and Output TimingReference Levels: O.BV or 2.2V D.U.T.1.SKohms1K >100 pFohms4CAPACITANCESYMBOL PARAMETER MAX UNITS NOTESCI Capacitance on all pins (except DO) 7.0 pFCoo Capacitance on DO pins 10.0 pF5/13341

MK48T08 (8)-10112115/20FIGURE 5. POWER· UP 1 POWER-DOWN CONDITIONSVeeĒI BAnDATA RETENTION TIMEtORAC ELECTRICAL CHARACTERISTICS (POWER-UP/DOWN TIMING)(O°C ,;; TA ,;; + 70 0 C)SYMBOL PARAMETER MIN MAXUNITSNOTEStpD E or VIi at V,H before Power Down 0pStF VPFD (Max) to VPFD (Min) Vee Fall Time 300I'stFB VPFD (Min) to Vso Vee Fall Time 10I'StRB Vso to VpFD (Min) Vee Rise Time 1I'stR VPFD (Min) to VpFD (Max) Vee rise Time 0I'stREe E or VIi at V,H after Power Up 2msDC ELECTRICAL CHARACTERISTICS (POWER-UP/DOWN TRIP POINTS)(O°C ,;; TA ,;; + 70 0 C)SYMBOL PARAMETER MIN TYPMAXUNITSNOTESVPFD Power·fail Deselect Voltage 4.5 4.64.75VVso Battery Back-up Switchover Voltage 3.0VtDR Expected Data Retention Time (Oscillator On) 5YEARSCAUTIONNegative undershoots below - 0.3 volts are not allowedon any pin while in the Battery Back-up mode.6/13342

MK48T08 (8)-10/12/15/20CLOCK OPERATIONSReading the ClockUpdates to the TIMEKEEPER registers should behalted before clock data is read to prevent readingof data in transition. Because the BiPORT TIME­KEEPER cells in the RAM array are only data registers,and not the actual counter, updating theregisters can be halted without disturbing the clockitself.Updating is halted when a "1" is written into the"Read" bit, the seventh most significant bit in theControl Register. As long as a "1" reamins in thatpOSition, updating is halted. After a Halt is issued,the registers reflect the count, that is day, date, andtime that were current at the moment the Halt commandwas issued.All of the TIMEKEEPER register are updated simultaneously.A Halt will not interrupt an update in progress.Updating is within a second after the bit isreset a "0".Setting the ClockThe eight bit of the Control register is the "Write"bit. Setting the Write bit to a "1 ", like the Read bit,halts updates to the TIMEKEEPER registers. Theuser can then load them with the correct day, dateand time data in 24 Hour BCD format. Resettingthe Write bit to a "0" then transfers thosevalues to the actual TIMEKEEPER counters andallows normal operation to resume.Stopping and Starting the OscillatorThe oscillator may be stopped at any time. If thedevice is going to spend a significant amount oftime on the shelf, the oscillator can be turned offto minimize current drain from the battery. The"Stop" bit is the MSB for the Seconds Register.Setting it to a "1" stops the oscillator.FIGURE 6. THE MK48T08 REGISTER MAPADDRESS07 06 0 5 0 41FFF - - - -1FFE X X X -1FFD X X - -1FFC X FT X X1FFB X X - -1FFA X - - -1FF9 ST - - -1FF8 W R S -DATA03---X----02 01 DoFUNCTION- - - YEAR 00-99- - - MONTH 01-12- - - DATE 01-31- - - DAY 01-07- - - HOUR 00-23- - - MINUTES 00-59- - - SECONDS 00-59- - - CONTROLST = STOP BITW=WRITE BITR=READ BITS=SIGNBITFT = FREQUENCY TESTX=UNUSED7/13343

MK48T08 (8)-10/12/15/20Calibrating the ClockThe MK48T08 is driven by a quartz controlled oscillatorwith a nominal frequency of 32768 Hz. Thecrystal is mounted in the tophat along with the battery.A typical MK48T08 is accurate within ± 1 minuteper month at 25°C without calibration. Thedevices are tested not to exceed 35 PPM (parts permillion) oscillator frequency error at 25°C, whichcomes to about ± 1.53 minutes per month. Of coursethe oscillation rate of any crystal changes withtemperature. Figure 6. shows the frequency errorthat can be expected at various temperatures.Most clock chips compensate for crystal frequencyand temperature shift error with cumbersometrim capacitors. The MK48T08 design, however,employs periodic counter correction. The calibrationcircuit adds or subtracts counts from the oscillatordivider circuit at the divide by 128 stage, asshown in figure 7. The number of times pulses areblanked (subtracted, negative calibration) or split(added, positive calibration) depends upon the valueloaded into the five bit Calibration byte foundin the Control Register. Adding counts speeds theclock up, subtracting counts slows the clock down.FIGURE 7. ADJUSTING THE DIVIDE BY 128NORMAL ~POSITIVE n n n n nCLAIBRATION.J L.J U L.J L.J LNEGATIVE n n nCALIBRATION .J ~ L.J LThe Calibration byte occupies the five lower orderbits in the Control register. This byte can be setto represent any value between 0 and 31 in binaryform. The sixth bit is a sign bit; "1" indicates positivecalibration, "0" indicates negative calibration.Calibration occurs within a 64 minute cycle. Thefirst 62 minutes in the cycle may, once per minute,have one second either shortened or lengthenedby 256 oscillator cycles, that is one tick of thedivide by 128 stage of the clock chain. If a binary"1" is loaded into the register, only the first 4minutes in the 64 minute cycle will be modified; ifa binary 6 is loaded, the first 24 will be affected andso on.Therefore, each calibration step has the effect ofadding or subtracting 512 oscillator cycles for every125,829, 120 actual oscillator cycles, that is 4.068PPM of adjustment per calibration step gin the user126.14 PPM calibration range. Assuming that theoscillator is in fact running at exactly 32768 Hz,each of the 31 increments in the Calibration bytewould represent 10.7 seconds per month.Two methods are available for ascertaining howmuch calibration a given MK48T08 may require.The first involves simply setting the clock, lettingit run for a month and comparing it to a known accuratereference (like WWV broadcasts). While thatmay seem crude, it allows the designer to give theend user the ability to calibrate his clock as his environmentmay require, even after the final productis packaged in a non-user serviceable enclosure.All the designer has to do is provide a simple utilitythat accessed the Calibration byte. The utilitycould even be menu driven and made foolproof.The second approach is better suited to a manufacturingenvironment, and involves the use of sometest equipment. When the Frequency Test (FT.)bit, the seventh-most significant bit in the day Register,is set to a "1", and the oscillator is runningat 32768 Hz, the LSB (DOO) of the Seconds Registerwill toggle at a 512 Hz. Any deviation from 512Hz indicates the degree and direction of oscillatorfrequency shift at the test temperature. For example,a reading of 512.01024 Hz would indicate a+ 20 PPM oscillator frequency error, requiring a-5 (000101) to be loaded into the Calibration Bytefor correction. Note that setting or changing the CalibrationByte does not affect the Frequency Testoutput frequency. The device must be selected andaddresses must stable at Address 1 FF9 when readingthe 512 Hz on DOO.The FT. bit must be set using the same methodused to set the clock, using the Write bit. The LSBof the Seconds Register is monitored by holdingthe MK48T08 in an extended read of the SecondsRegister, without having the Read bit set. The FT.bit MUST be reset to a "0" for normal clock operationsto resume.8/13344

MK48T08 (B)-10112/15/20FIGURE 8. FREQUENCY ERROR WITHOUT CALIBRATIONFREQUENCY ERROR (PPM)20 ,--------------------------------,10·10·20·3040·50·60·70·80 '-'-----'-----'----'----"-----'-----'-----'--'10 20 30 40 50 60 70TEMPERATURE (DEGREES CELCIUS)DATA RETENTION MODEWith Vee applied, the MK48T08 operates as aconventional BYTEWIDE static RAM. Should thesupply voltage decay, the RAM will automaticallypower-fail deselect, write protecting itself whenVee falls within the VPFo(max), VPFO(min) window.The MK48T08 has a VPFD(max)-VpFD(min)window of 4.75 volts to 4.5 volts, allowing usersconstrained to a 10% power supply specificationto use the device.Note: A mid-write cycle power failure may corruptdata at the currently addressed location, but doesnot jeopardize the rest of the RAM's content. Atvoltages below VPFO(min), the user can be assuredthe memory will be in a write protected state,provided the Vee fall time does not exceed tF. TheMK48T08 may respond to transient noise spikesthat reach into the deselect window if this shouldoccur during the time the device is sampling Vee.Therefore decoupling of the power supply lines isrecommended.The power switching circuit connects external Veeto the RAM and disconnects the battery when Veerises above Vso. Normal RAM operation can resumetREe after Vee exc~eds..YPFO(max). Cautionshould be taken to keep E or W high as Vee risespast VPFD(min) as some systems may perfominadvertent write cycles after Vee rises but beforenormal system operation begins.PREDICTING BACK-UP SYSTEM LIFEThe useful life of the battery in the MK48T08 is expectedto ultimately come to an end for one of tworeasons; either because it has been discharged wileproviding current to an external load; or becausethe effects of aging render the cell useless beforeit can actually be discharged. Fortunately, thesetwo effects are virtually unrelated, allowing discharge,or Capacity Consumption and the effectsof aging, or Storage Life to be treated as twoindependent but simultaneous mechanisms, theearlier of which defines Back-up System life.The current drain that is responsible for CapacityConsumption can be reduced either by applyingVee or turning off the oscillator. With the oscillatoroff, only the leakage currents required to maintaindata in the RAM are flowing. With Vee on, thebattery is disconnected from the RAM. Because theleakage currents of the MK48T08 are so low, thencan be neglected in practical Storage Life calculations.Therefore, to extent the life of components that arejust sitting on the shelf (not in system use) the oscillatorshould be turned off.9/13345

MK48T08 (8)-10/12/15/20FIGURE 9. MK48T08 PREDICTED BATTERY STORAGE LIFE VS. TEMP.(J)a:3002001009080706050403020"" LU>-~ ~~~~"-"'- ~'" '"""~tl0/~~t 50% (AVERAGE)109876 "-5 "-'"'""'-~120 30 40 50 60 70 80 90DEGREES CELSIUSPredicting Storage LifeFigure 9 illustrates how temperature affects StorageLife of the M K48T08 battery. As long as Veeis applied or the oscillator is turned off, the life ofthe battery is controlled by temperature and is virtuallyunaffected by leakage currents drawn by theMK48T08. ..Storage Life predictions presented in Figure 9 areextrapolated from temperatu(e accelerated life-testdata collected in over 100 million device hours ofcontinuing bare cell and encapsulated cell batterytesting by SGS-THOMSON. Obviously, temperatureaccelerated testing cannot identify nontemperaturedependent failur mechanisms. However,in view of the fact that no random cell failureshave been recorded in any of SGS-THOMSON'son going battery testing since it began in 1982, webelieve the chance of such failure mechanisms surfacingis extremely small.For the purpose of the testing, a cell failure is definedas the inability af a cell stabilized a 25°C toproduce a 2.0 volt closed-circuit voltage across a250K load resistance.A Special Note: The summary presented in Figura9 represents a conservative analysis of the datapresently available. While SGS-THOMSON ismost likely in possession of the largest collectionof battery life data of this kind in the world, the resultspresented should not be considered absoluteor final; they can be expected to change as yetmore data becomes available. We believe thatfuture read point$ of life test presently under wayand improvements in the battery technology itselfwill result in a continuing improvement of thesefigures.Two end of life curves are presentedih Figure 9.They are labeled "Average" (t5001ol and (t1O/0). Theseterms relate to the probability that a given numberof failure will have accumulated by a particularpoint in time. If, for example, expected life at 70°Cis at issue, Figure indicates that a particularMK48T08 has a1 % chance of having a battery failure11 years into its life and a 50% chance of failureat the 20 year mark. Conversely, given asample of device, 1 % of them can be expected toexperience battery failure within 11 years; 50% ofthem can be expected fail within 20 years.10/13346

MK48T08 (8)-10/12/15/20rhe t 10/0 figure represents the practical onset ofNear out, and is therefore suitable for use in whatNould normally be thought of as a worst-case anaysis.The t50% figure represents "normal" or'average" life. It is, therefore, accurate to say that:he average device will last "t50%".Battery life is defined as beginning at the date ofllanufacture. Each MK48T08 is marked with a four:ligit manufacturing date code in the form YYWW:example: 8625= 1986, week 25).Calculating Predicted "Storage Life of theBatteryAs Figure 9 indicates, the predicted Storage Lifeon the battery in the MK48T08 is a function of temperature.Because the ambient temperature profile is dependentupon application controlled variable, only theuser can estimate predicted Storage Life in a givendesign. As long as ambient temperature is heldreasonably constant, expected Storage Life can beread directly from Figure 9. If the MK48T08 spendsan appreciable amount of time at a variety of temperatures,the following equation should be usedto estimate Storage Life.Predicted Storage Life = 1 + [((TA1 ..;. TT)..;. SL11 + [TA2";' TT)..;. SL21 + ... + [(TAN";' TT)..;. SLNIIWhere TA1, TA2, TAN, = Time at Ambient Temperature 1, 2, ectTT= Total Time= TA1+TA2+ ... +TANSL1, SL2, SLN = Predicted Storage Life at Temp. 1, Temp. 2, ect. (See Figure 9)Example Predicted Storage Life Calculation1\ cash registerlterminal operates in an environmentNhere the MK48T08 is exposed to temperatures of30°C (86°F) or less 4672 hrs./yr.: temperaturesgreater than 25°C, but less than 40°C (104°F), for3650 hrs./yr.; and temperatures greater than 40°C,but less than 70°C (158°F), for the remaining 438hrs./yr.Reading Predicted t1O/0 values from Figure 10; SL1 = 456 yrs., SL2 = 175 yrs. SL3 = 11.4 yrs.Total Time (TT) =8760 hrs./yr. TA1 =4672 hrs./yr. TA2 = 3650 hrs./yr. TA3=438 hrs./yr.Predicted Typical Storage Life ~ 1 ..;. {[(4672..;. 8760)..;. 4651 + [3650 + 8760) ..;.1751 + [(438..;. 8760)..;. 11.411Predicted Typical Storage Life ~ 126 years11113347

MK48T08 (8)-10/12/15/20ABSOLUTE MAXIMUM RATINGS·Voltage On Any Pin Relative to GND _______________ - 0.3 V to + 7.0VAmbient Operating (VCC On) Temperature (TAl O°C to + 70°CAmbient Storage (VCC Off, Oscillator Off) Temperature _________ - 20°C to + 70°CTotal Device Power Dissipation ______________________ 1 WattOutput Current Per Pin20 mA• Stresses grater than those under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other conditions beyond those indicated in the opertional section of this specificationis not implied. Exposure to absolute maximum rating conditions for extended periods of time may' affect reliability.RECOMMENDED DC OPERATING CONDITIONS(OOC ,;;; TA ,;;; + 70°C)SYMBOLVCCGNDVIHVILPARAMETERSupply voltageSupply VoltageLogic "1" Voltage All InputsLogic "0" Voltage All InputsMIN MAX UNITS NOTES4.75 5.5 V0 0 V2.2 VCC+ 0.3 V-0.3 0.8 VDC ELECTRICAL CHARACTERISTICS(O°C ,;;; TA ,;;; + 70°C) (Vcc (Max) ,;;;Vcc,;;;Vcc(Min))SYMBOLICC1Icc2ICC3IlLIOLVOHVOLPARAMETERAverage VCC Power Supply CurrentTTL Standby Current (E = VIH)CMOS Standby Current (E = VCC - 0.2V)Input Leakage Current (Any Input)Output Leakage CurrentOutput Logic "1" Voltage (lOUT = - 1.0 mAlOutput Logic "0" Voltage (lOUT = 2.1 mAlMIN MAX UNITS NOTES80 mA5 mA3 mA-1 +1 p.A-5 +5 p.A2.4 V0.4 V12/13348

MK48T08 (8)-10/12/15/20PACKAGE DESCRIPTION--r~AA • •'v''v''v'( (B PACKAGE 28 PIN"'Dim.mmInchesMin MIx Min MaxNotesA 8.128 9.852 .320 .380 2Al 0.381 0.752 .015 .030 2A2 7.82 9.144 .300 .3808 0.381 0.533 .015 .021 381 1.143 1.778 .045 .070C 0.203 0.304 .008 .012 3A A A A 0 - 37.973 - 1.495 1E 13.482 16.258 .530 .640'v''v''v''v'I ~ .i~Lim_~~~,• c IItEl 13.482 13.97 .530 .550El 13,97 14.478 .550 .570el 2.286 2.794 .090 .110eA 15.24 17.78 .600 .700L 3.048 3.81 .120 .150S 1.524 2.54 .060 .1001. - ","===iI \~ ,,--.. _- =:j ..• 1 •• D1.(T.N.A.INOTES1. OVERAU.l.ENGTH INCLUDES FLASHAND PRQEC11ONSON ErnER EN)OFPACKAQE.I. PACKAGE SfANOOFF rolE MEASUREDPERJEDEC REQUIREMENTS.3. nE MAXIULN UMT 8tW.L IEINCREASED BY .G031N. 'MiENSOLDER lEAD FINSH IS SPE~FIEO.13113349

MK48Z30 (8)-10/12/1532K X 8 ZEROPOWER RAMADVANCED DATA• DATA RETENTION IN THE ABSENCE OF Vee• DATA IS AUTOMATICALLY PROTECTED DU­RING POWER LOSS• DIRECTLY REPLACES 32Kx8 VOLATILESTATIC RAM OR EEPROM• UNLIMITED WRITE CYCLES• CMOS - LOW POWER OPERATION• STANDARD 28-PIN JEDEC PINOUT• READ CYCLE TIME EQUALS WRITE CYCLETIME• FULL 10% OPERATING RANGE• LITHIUM ENERGY SOURCE IS ELECTRICAL­L Y DISCONNECTED TO RETAIN FRESHNESSUNTIL POWER ISAPPLIED THE FIRST TIMETRUTH TABLE MK48Z30Vcc E G W MODE DQ POWERVIH X X Deselect High-Z Standby

STATIC RAM DEVICESCACHE TAG RAM353

~ SGS-1HOMSON~ ~ L [jiVA]D©OO@rn[1,rn©'iJ'OO@~D©~MK41H80(N,P)-20/25/354K x 4 CMOS TAGRAMTM• 4K x 4 SRAM WITH ONBOARD 4 BIT COM­PARATOR• 20, 25, AND 35ns ADDRESS TO COMPARE AC­CESS TIME• 12, 15, AND 20ns TAG DATA TO COMPARE AC­CESS TIME• EQUAL ACCESS, READ AND WRITE CYCLETIMES• FLASH CLEAR FUNCTION• 22-PIN, 300 MIL PLASTIC AND CERAMIC DIP• ALL INPUTS AND OUTPUTS ARE TTL COMPAT­IBLE, LOW CAPACITANCE, AND PROTECTEDAGAINST STATIC DISCHARGE• WORD WIDTH EXPANDABLETRUTH TABLEWE OE CLR MATCH MODEH H H Valid Compare CycleL X H Invalid Write CycleH L H Invalid Read CycleX X L Invalid Flash Clear CycleX = Don't CareDESCRIPTIONThe MK41H80 is a member of SGS.:rHOMSON's4K x 4 CMOS Static RAM family featuring fully staticOPlilflition requiring no external clocks or timingstrobes. Cycle Time and Compare Access Time areequal. The MK41H80 is powered by a single +5V±10% power supply and the inputs and outputs arefully TTL compatible.The MK41H80 features an onboard 4 bit comparatorthat compares RAM contents and current inputdata. The result is an active high match on theMATCH pin or an active low miss on the MATCHpin. The MATCH pins of several MK41H80's can benanded together to provide enabling or acknowledgingsignals to the data cache or processor.Tag data can be read from the data pins by bringingOutput Enable (OE) low. This will allow dataJune 1988.••. ~.~ ....... ~,NDIP-22(Plastic Package)22PDIP-22(Ceramic Package)FIGURE 1. PIN CONNECTIONSA.AsA.A7AsA.A,oA11OEWEvssPIN NAMESAo - A11DQo - DQ 3MATCHWEOECLRVeeVss123456789101122 vee21 A.20 A.19 A,18 Ao17 CLR16 CQ.15 CQ.14 CQ,13 CQo12 MATCH- Address Inputs- Data Input/Output- Comparator Output- Write Enable- Output Enable- Flash Clear- Power (+5V)- Groundstored in the memory array to be displayed at theOutputs (DQo-DQa).Flash Clear operation is provided on the MK41H80via the (CLR) pin. A low applied to the CLR pinclears all RAM bits to a logic zero.1/10355

MK41 HSO(N, P)-20/25/35FIGURE 2. COMPARE AND WRITE CYCLEADDRDO'Wl/J/iq C- IRe.IjllilliCOMPARE CYCLEWRITE CYCLEIe Ie~IADDRESSVALIDADDRESSVALID1- --J ICCH ~~~~~~,%'W\'0,\0I ~IA'-' _10.+-IDeA-~.~~tAW tAH I ..tRCH ...... r---tWEW-.f-IOH"VALIDVALIDDATA INDATA IN--:...."§--~ tAtHMATCH ~COMPARE ~'AVOID METASTABLE INPUTSFIGURE 3. WRITE AND READ CYCLEWRITE CYCLEt==leREAD CYCLE~ Ie ~ADDRDO'IADDRESSVALID- ..-IWEW_~+-t ~~1-I I II ~\\\\\\\\\\~_ 10H ~~OEL~ ~ r---IWEZ_ 10• ~ IOEA ~VALID DATA INIAA l(I---+lIOEZ ~~IOH ~VALIDDATA OUTMATCHINVALID'AVOID METASTABLE INPUTS2/10356

MK41H80(N,P)-20/25/35COMPARE, WRITE AND READ TIMINGThe MK41H80 employ!! three signals for device control.The Write Enable (WE) pin enables a Write Cycleif low and either a Compare Cycle or a ReadCycle when high. The OE pin enables a Read Cycleif low or a Compare Cycle if high. The CLR pinenables a Flash Clear Cycle when brought low.The MK41H80 begins a Compare Cycle with the applicationof a valid address (see Fi~ 2). A validMATCH is enabled when DE and WE go high inconjunction with their respective Set Up and Holdtimes. MATCH will occur tACA after a valid address,and tDCA after valid Data In. MATCH will then go invalidtACH after the address changes.The MK41H80 starts a Write Cycle with stable address~seeFigure 2). OE may be in either logicstate. WE may fall with stable addresses, and mustremain low until tAW with a duration of tWEW ' Datain must be held valid tos before and tOH after WEgoes high. MATCH will be invalid during this cycle.The MK41H80 begins a Read Cycle with stable addressesand WE high (see Figure 3). DO becomesvalid t.M.. after a valid address, and tOEA after thefall of OE. DO outputs become invalid tOH after theaddress becomes invalid or tOEZ after OE isbrought high. Ripple thro.l:!gh data access may beaccomplished by holding OE active low while strobingaddresses Ao-All' and holding CLR and WEhigh. The MATCH output will be invalid during theRead cycle.ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(O°C:5T A :570°C) (Vcc = 5.0V ±10%)·20 ·25 ·35SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStc Cycle Time 20 25 35 nstccs Compare Command Set Up Time 7 8 10 nstCCH Compare Command Hold Time 0 0 0 nstRCS Read Command (WE) Set Up Time 0 0 0 nstRCH Read Command (WE) Hold Time 0 0 0 nstAS Address Set-up Time 0 0 0 nstAW Address Stable to End of Write 16 20 30 nsCommand (WE)tAH Address Hold Time after End of Write 0 0 0 nstWEW Write Command (WE) to End of Write 16 20 30 nstos Data Set Up Time 12 13 14 nstOH Data Hold Time 0 0 0 nstOCA Data Compare AcC'llss Time 12 15 20 ns 3tACA Address Compare Access Time 20 25 35 ns 3tACH Address Compare Hold Time 5 5 5 ns 3tOCH Data Compare Hold Time 3 3 3 ns 3tOEA Output Enable (OE) Access Time 10 12 15 ns 3tOH Valid Data Out (~O) Hold Time 5 5 5 ns 3tM Address Access Time 20 25 35 ns 3tOEZ Output Enable (OE) to High-Z 7 8 10 ns 4tOEL Output Enable (OE) to Low-Z 2 2 2 ns 4tWEZ Write Enable (WE) to High-Z 8 10 13 ns 4tWEL Write Enable (WE) to Low-Z 5 5 5 ns 43/10357

MK41H80(N,P)-20/25/35APPLICATIONThe MK41H80 operates from a 5.0 volt supply. It iscompatible with all standard TTL families on all inputsand outputs. The device should share a solidground plane with any other devices interfaced withit, particularly TTL devices. Additionally, becausethe outputs can drive rail-to-rail into high impedanceloads, the MK41H80 can also interface to 5 voltCMOS on all inputs and outputs. Refer to the normalizedperformance curves that follow.The MK41H80 compares contents of addressedRAM locations to the current data inputs. A logicone (1) output on the MATCH pin indicates that theinput data and the RAM contents match. Conversely,a logic zero (0) on the MATCH pin indicates atleast one bit difference between the RAM contentsand input data generating a miss.The MATCH output is always at either an active highor low logic level, and does not exhibit a threestateor high impedance characteristic. Since thecomparator circuitry is always enabled, metastabledata input levels can result in excessive MATCH output activity. Therefore, the use of pull-up or pulldownresistors is recommended on the data bus.A pull-up resistor is also recommended for the CLRinput. This will ensure that any low going systemnoise, coupled onto the input, does not drive CLRbelow V 1H minimum specifications.Because high frequency current transients will beassociated with the operation of the MK41H80, powerlines inductance must be minimized on the circuitboard power distribution network. Power andground trace gridding or separate power planes canbe employed to reduce line inductance.Though often times not thought of as such, thetraces on a memory board are basically unterminated,low impedance transmission lines. As suchthey are subject to signal reflections manifested asnoise, undershoots and excessive ringing. Seriestermination in close proximity to the TTL drivers canimprove driver/signal path impedance matching.While experimentation most often proves to be theonly practical approach to selection of series resistors,values in the range of 10 to 33 ohms oftenprove most suitable.FIGURE 4. BLOCK DIAGRAM141I Ao~~~SS I I ROW IDECODERl BUFFER JICLEARBUFFERI l WRITE WRITEENABLE II BUFFERCONTROLDATA INPUTBUFFERI4 1MEMORYCELL ARRAY128 ROWS32x4 COWMNS44 4·BITCOLUMN 4 COMPARATORI/OMATCH5-I ;~D~:'SNS II BUFFER I5 COLUMNDECODER·1OUTPUTENABLEBUFFER4~DATAOUTPUTBUFFER44110358

MK41H80(N,P)-20/25/35FLASH CLEAR CYCLEA Flash Clear Cycle begins as CCR is brought low(see Figure 5). A Flash Clear sets all 16,384 bits inthe RAM to logic zero. Control Inputs will not berecognized from n after CLR falls to teR after CCRis brought high. OE and WE are Don't Cares andDO is High-Z. MAlCH will be invalid while CLR is low.AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(OOCsT As70OC) ('Icc = 5JN ±100Al)·20 ·25 ·35SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStFCC Flash Clear Cycle Time 40 50 70 nslex Clear (CLR) to Inputs Don't Care 0 0 0 nsteR End of Clear (CLR) to Inputs 0 0 0 nsRecognizedteLP Flash Clear (C[R) Pulse Width 36 44 60 nsFigure 5, Read-Flash Clear-Write CycleREAD CYCLE CLEAR CYCLE WRITE CYCLE14---- e ----I~f---- tFee--_~---le ----I~ADDRADDRESS ADDRESS ~XXX~ ADDRESS___..II\.__......::VA:::L:::ID:"""_-'I\...,!!VA:::L:::ID'.....,J r\MXXlVALID00'II IDEA:}leLPI~...!......!....I __I.--I Aw_I leR j.---'" I--- ... _ Lf-r-· ----J-+l .-- -I IDS j.---___ -.:..~_I_.A__ VALID £:

MK41H80(N,P)-20/25/35ABSOWTE MAXIMUM RATINGSVoltage on Any Terminal Relative to V ss ...................................... -1.OV to + 7.OVOperating Temperature TA (Ambient) .......................................... O"C to +7O"CStorageTemperature (Ceramic) ........................................... -65"C to +150"CStorage Temperature (Plastic) ............................................. -55"C to +125"CPower Dissipation ............................................................... 1 WattOutput Current per Pin .......................................................... 50 mAStresses greater than those ,listed under '~Iute Maximum Ratings" may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at these or any other conditions above those indicated in theoperation sectiohs of this specification is not implied. Exposure to absolute maximum rating conditions for extended periodsof time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(O'CsTAs +70 "C)SYMBOL PARAMETERVee Supply Voltage (Referenced to V ss>VssV1HV1LGroundss>Input High (Logic 1) voltage, All Inputs (Referenced to VInput Low (Logic 0) voltage, All Inputs (Referenced to V ss>DC ELECTRICAL CHARACTERISTICS(O"CsTAs+70"C) (Vee = 5IN ±10%)MIN4.5OD2.2-0.3TYP MAX UNITS NOTES5.0 5.5 VOD OD VVee +0.3 V0.8 VSYMBOL1CC1I" IL10lVOHVOLPARAMETEROperating Current • Average Power SupplyOperating CurrentInput Leakage Current, Any inputOutput Leakage CurrentOutput High (Logic 1) voltage Referenced to Vss;IOH = -4mAOutput Low (Logic 0) voltage Referenced to Vss;IOL = +8mAMIN MAX UNITS ~OTES120 mA 1-1 1 pA 5-10 10 pA 62.4 V0.4 VAC ELECTRICAL CHARACTERISTICS(TA = 25"C, f = 1D MHz)C 1C2SYMBOLPARAMETERCapacitance on any Input PinCapaCitance on any Output PinTYP MAX UNITS NOTES4 5 pF 28 10 pF 26110360

MK41H8O(N,p)-20125135~ TEST CONDITIONSInput Levels .............................................................. GND to 3.0 VTransition Times .................................................................. 5 nsInput and Output Signal Timing Reference Level ........................................ 1.5 VAmbient Temperature ........................................................ O"C to 7O"CVee ................................................................ 5.0 V ± 10 percentFIGURE 6. OUTPUT LOAD CIRCUITS+5.0 V +5.0 V470 OHMS 470 OHMSDEVICEUNDERTESTDEVICEUNDERTEST240 OHMS == 240 OHMS =~- '-- GND -• INCWDES SCOPE AND TEST JIG.L..... GND(A)NOTES1. lee1 is measuAld as !he average PC curren! willi Vee = Vee(max) and w~h !he oulpulS open circuit. t C)'CIe = min duty C)CIe100%.2. CapaciIances are sampled and not 100% tested.3. MeasuAld willi load shown in FoguAl 6(A).4. MeasuAld willi load shown in FoguAl 6(8).5. Input leakage current specfficaIions "'" valid lor all VIN suchCW

MK41 H80(N ,P)-20/25/35NORMALIZED DC AND AC PERFORMANCE CHARACTERISTICSNORMALIZED SUPPLY CURRENT VS.CYCLE TIME Vee = S.OV T. = 2S"CNORMALIZED ACCESS TIME VS.SUPPLY VOLTAGE T. = 2S'CUII!~'"filI0.990.98,0.970."0.950.940.930.920,910.'0.890.8'0.870.88VV0.8522 26 30 34 38 42••VVVv501.15~ 1.11.05~I 0.95; 0.9M50.8t'-CYCLE FAEQUE,,",ev (MHz)SUPPLY VOLTAGE (V)!II1=~"!i/I~I.'1.31.21.1NORMALIZED ACCESS TIME VS.AMBIENT TEMPERATURE V cc = S.OV,/0.'0.8V0.7 -80 -40 -20 20 40 60 80 100 120,/,/AMBIENT TEMPERATURE ("C)NORMALIZED ACCESS TIME VS.OUTPUT LOADING Vee = S.OV T. = 2S"C'.5-j--~-t---+-r--+--t-+--+-b"'lV3.5 -·-t~F~--+-f--·3 1----1-.. v~t-+--+2.5 _. -.~I-- - 1-- _.2 /1.57~·li7~-+--+-t--+-r--+-+--·+---0.5+---+-+--+-+-+-f--+-+-f--I200 .00 BOO BOO 1000CAPACITANCE (pF)I.'LOGIC THRESHOLD VOLTAGE VS.AMBIENT TEMPERATURE Vee = S.OV1.81.71.B1.5I.'1.31.2 .--_.------_.---_._._._.-._-----1.1-BO -.0 -20 20 40 80 80 100 120AMBIENT TEMPERATURE (OC).>LOGIC THRESHOLD VOLTAGE VS.SUPPLY VOLTAGE T. = 2S'C2.2.-rr-,-",-.,--rr-,-",-,-rr-,,,...,2.1+-H++-+-++-H++-+-++-H-+8.-11,·+-H++-+-++-H+H,.-f'''!-H-++-+-ju+-l-++-H++-+·C!--1"'H++-+-++-H-11.7+-+-++-H,.f

MK41H8O(N,p)-2OI25/35NORMALIZED DC AND At; PERFORMANCE CHARACTERISTICSNORMALIZED SOURCE AND SINK CURRENTS VS.OUTPUT VOLTAGE Vee = 5.GY. T. = 250C1.31.2 ........... =1.1 t-- •.............I 1 -- 7

MK41H8O(N,P),-2OI2513522 PIN "P" PACKAGE, SIDE BRAZED CERAMIC DIP[1[:]1]I 0 ~DI~1. PACKAGE STANDOFF TO BE MEASUREDPER JEOEC REQUIREMENTS.2. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. WHENSOLDER LEAD FINISH IS SPECIFIED.Dim.AAlA2BBlC001EEl.1eALQlmmInchesNotesMin Max Min Max- 4.445 - .175 10.508 - .020 - 12.032 2.794 .080 .1100.381 0.533 .015 .021 20.965 1.447 .038 .0570.203 0.304 .008 .012 227.559 28.321 1.085 1.1250.889 1.551 .035 .0557.493 8.255 .295 .3257.112 7.874 .280 .3102.286 2.794 .090 .1107.366 9.271 .290 .3853.048 - .120 -0.127 - .005 -ORDERING INFORMATIONPART NUMBER ACCESS TI~E PACKAGE TYPEMK41HSON-20 20 ns 22 pin Plastic DIPMK41HSON-25 25 ns 22 pin Plastic DIPMK41HSON-35 35 ns 22 pin Plastic DIPMK41 HSOP-2O 20 ns 22 pin Ceramic DIPMK41 HSOP-25 25 ns 22 pin Ceramic DIPMK41HSOP-35 35 ns 22 pin Ceramic DIPTEMPERATURE RANGEO"C to 70 "CO"C to 70 "CO"C to 70 "CO"C to 70 "CO"C to 70 "CO"C to 70 "CMKNI~_-Speed gradePackage TypeN: Plastic DIPP: Ceramic DIPDevice family andidentification numberSGS.:rHOMSONprefix10110364

MK4202(Q)-202048 x 20 CMOS TAGRAMTM• 2048 x 20 CMOS SRAM WITH ONBOARDCOMPARATOR• MATCH ACCESS TIME = 20n6 (MAX)• READ ACCESS TIME = 25n6 (MAX)• RESET CYCLE = 25n6 (MAX)• Icc (OUTPUTS DESELECTED) = 225mA (MAX)• STANDBY = 70mA (MAX)• FLASH CLEAR VALID BIT FUNCTION• TARGET APPLICATION:68020-25,68030-33 AND 80386 CACHEQPLCC68(Plastic Chip Carrier)ADVANCED DATAFIGURE 1. PINOUT FOR 68 PIN PLCC PACKAGE (PRELIMINARY)P, P, P, Po E, E, E, Eo Vee Ao A, A, A, A. A, A, V ••PIN NAMESVee. Vss +5 Yoh Supply. Ground09 08 07 06 05 04 03 02 01 68 67 66 65 64 63 62 61veea. VSSQ +5 YoI' Output Supply. Ou'·Rs 10 60 A,o put GroundVeeo 11 59 VeCQ Ao·AIQ Indell Address InputCDOo 12 58 DO,sCO~ Clearable Tag Oata 11000,·00,9 Tag Oata 110DO, 13 57 DO .. Eo·E, Chip Enable IProgrammableV ••• 14 56 V •••Ae'i .. low or Highlpo'p, Chip Enable ProgramDO, 15 55 DO" InputsDO, 16 54 Rs Reset Input (Active low)DO"SChip Solec' Input IActive lowlVeeo 17 53 Veeo i Write Enable (Active low)DO. 18 52 DO,. ii Data Output Enable (ActivelowlDO. 19 51 DO,.Co Compa,. 0 Output 13·StatelV •• o 20 50 Hit = High. Miss = lowV •• oC, Compo,. 1 Output 13·Stat.1DO, 21 49 DO"Hit = High. Miss = LowDO, 22 48 DO" HoForce Hit 0 Input (Active low)Veeo 23 47 ~Force Hit 1 Input (Active Low)VeeoMoForce Miss 0 Input (ActiveDO, 24 46 DO" lowlM, Force Miss 1 Input (Active001 25 45 DO"lowlV •• o 26 44 V •• o CGo Compa,. 0 Output Enable27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 IActive lowlCG, Compare 1 Output EnableA, AI As •• M, If, CG, "if, ~ CGo Veeo C, Co IAetivelowlif Vee W S VJune 1988 1118This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice365

MK4202(Q)-20TRUTH TABLERS S E WHi - X -Hi - X -Hi - X -Hi X F XG---XMx Hx CGx MODELo X X Force MissHi Lo X Force HitHi Hi Hi Comp DisableHi Hi X StandbyCx DC NOTESLow - 1High - 1Hi-Z - 1Hi-Z Hi-ZHi X T HiHiHi Hi Hi CompareHi-ZDinHi X T HiHiHi Hi Lo CompareHi or LoD inHi Hi T LoXHi Hi Lo HitHighHi-ZHi Hi T XLoHi Hi Lo HitHighHi-ZHi Lo T LoXHi Hi Lo WriteHighD inHi Lo T HiLo Hi X XLo X F XLo X X HiLo X X HiLo Lo T LoLo X T HiLoXXHiLoXHiHi Hi Lo Read- - - Reset- - - Reset- - - Reset- - - Reset- - - Not AllowedHi Hi Lo ResetHighD Out- Hi-Z- Hi-Z- Hi-Z- Lo-Z- Hi-Z 2Lo Din 3Key: X = Don't CareHx = Ho or H,Mx = Mo or M,CGj( = CGo or CG,FT= (False) Eo-E3 pattern DOES NOT match P O -P3 pattern.= (True) Eo-E3 pattern DOES match P O-P3 pattern.= Not related to identified mode of operation.NOTES1. Force hit/miss operations independent of other RAMoperations.2. May disrupt Reset, will not damage device.3. Reset will force Cx low during a valid compare whenCOOO is 0 in = Hi.2118366

MK4202(Q)-20FIGURE.2. MK4202 BLOCK DIAGRAMc,w-··_r---,IiGDQ3118367

MK4202(Q)-20DEVICE DESCRIPTION AND FEATURESThe MK4202 is designed to be connected DIRECT­LY to a high performance 32 bit microprocessor, allowingthe elimination of the logic delays associatedwith collecting HIT or Miss outputs into a subsequentgate or the RC delays associated with wired­OR open collector match outputs.The MK4202 TAG RAM has four major features thatallow direct connection:1. Wide enough for almost any TAGRAM applicationwithout requiring multiple chip width expansionand the delays that would result.2. Four (4) programmable CHIP ENABLE inputs,allowing DEPTH EXPANSION without any ofthe attendant chip enable decode delays thatwould otherwise be required.P O-P 3 should be tied directly to Vee or Vss, orthrough pull-up or pull-down resistors. TheMK4202 is selected when Eo-E3 equals P O-P 3in a binary match.(Example: Eo-El = 0110, P O-P 3 = 0110.)3. 3-STATE COMPARE OUTPUTS, allOWing allCompare outputs to be bused together so theAddress~to-Compare access time for a depthexpanded application is identical to that of asingle device. The Programmable Chip Enablesprevent bus contention by assuring thatonly one TAGRAM at a time drives each Comparebus when in Compare mode.4. DUAL COMPARE OUTPUTS (Co and C 1) andFORCED HIT (Hn and Ff;') and FORCEDMISS

MK4202(Q)-20The net effect Is that the Address-to-Compare accesstime demonstrated by the MK4202 is all of thedelay the user must consider. The alternative approach,using narrow TAG RAMs with open collectoroutputs or narrow TAGRAMs with 2-state outputsand a 10ns programmable logic device, requiresthat the narrow TAG RAMs demonstrate a 10nsAddress-to-Compare access time to yield the sameperformance in a user's system that the MK4202provides.POWER DISTRIBUTIONThe MK4202, being a 20 output device, obviouslyrequires the use of good power bussing techniques.MK4202 has been designed in such a way as to allowthe user to minimize the effects of switchingtransients on overall circuit operation. Of particuFIGURE 4. APPLICATION BLOCK SCHEMATICI P = 0001INDEX11P = 0000A. A,.lar interest is the separate bussing of the Vcc andVss lines to the output drivers. The advantageprovided by these separate power pins .. designatedVcca and VSSQ, is that voltage sags and groundbumps seen on these pins are not reflected into theother portions of the chip, particularly the inputstructures. As a result, switching noise in the supplyhas much less effect on input levels, providingthe user with more noise margin than would otherwisebe available.Of course Vss and Vssa must always be at thesame DC potential. Vcc and Vcca must match aswell. Differences between them due to AC effectsare expected, but must be minimized through theuse of adequate bussing and bypassing. All specificationsand testing are done with V ss = V ssa ±10mV RMS, Vcc = Vcca ± 10mV RMS with instantaneouspeak differences not exceeding 50mV.32 BIT .p1INDEX Eo E,TAG19DO, DO,.VALIDCDO.SELECTSWRITEWREAD G C.BUS ERR M.HALT M, C,c·nc'nVeeQ~>BERRHALTH.H,CG.>~?VeeCG,5118369

MK4202(Q)-20READ MODEThe MK4202 is in the Read mode whenever W isHIGH, and G is LOW provided Chip Select (5) isLOW and a true Chip Enable pattern (Eo-Ea) is applied.The 11 address inputs (Ao-A1O) define aunique index address giving access to 20 of 40,960bits of data in the static memory array. Valid datawill be present at the 20 output pins within tAVOVof the last stable address provided ChlQ Enable,Chip Select (5), and Output Enable (G) accesstimes have been met. "If Chip Enable, 5, OF Gaccess times are not met, data access will be measuredfromthe latter falling edge or limitingparameter (tEvov, tSlOV, or tGlOV)' The state QitMtag ~a 1/0 pins is controlled by the (Eo-Ea), S, G,and W input pins. The data lines may be indeterminateat tEVQX, tSlOX, or tGlOX' but will alwayshave valid data at tAVOV'READ CYCLE TIMINGElectrical Characteristics and Recommended AC Operating Conditions(O"CsTAs70°C) (Vce = 5.0 ± 10%)STDALTSYM SYM PARAMETER MIN MAX UNITS NOTEStAVAV te Cycle Time 25 nstAVQV tAA Address Access Time 25 nstAXOX tAOH Address Output Hold Time 5 nstEVQV tEA Chip Enable Access Time 25 nstEXOX tEOH Chip Enable Output Hold Time 4 nstEVax tELZ Chip Enable TRUE to Low-Z 4 nstEXOZ. tEHZ Chip Enable FALSE to High-Z 8 nstSLaV tSA Chip Select Access Time 10 nstsHox tSOH Chip Select Output Hold Time 2 nstSlOX tSLZ Chip Select to Low-Z 3 nstSHOZ tSHZ Chip Select to High-Z 4 nstGlOV tGA Output Enable Access Time 10 nstGHOX tGOH Output Enable Output Hold Time 2 nstGlOX tGLZ Output Enable to Low-Z 2 nstGHOZ tGHZ Output Enable to High-Z 5 nsWRITE MODETheMK4202 is in the Write mode whenever W isLOW provided Chip Select (5) is LOW and a trueChip Enable pattern (Eo-Ea) is applied (G may bein either logic state). Addresses must ~ heJ.g validthroughout a write cycle, with either W.9.r S inactiveHIGH during address transitions. W may fallwith stable address, but must remain valid fortWUol/H' Since the write..!;!egins with the concurrenceof Wand 5, should W become active first, thentSlSH must be satisfied. Either W or 5 can terminatethe write cycle, therefore tOVWH or tOVSHmust be satisfied before the earlier rising edge, andtWHOX or tSHOX after the earlier rising edge. If theoutputs are active with ~ and 5 asserted LOWand with true Chip Enable, then W will return theoutputs to high impedance within tWlHZ of its failingedge.6118370

MK4202(Q)-20WRITE CYCLE TIMINGElectrical Characteristics and Recommended AC Operating Conditions(0°C~TA~70"C) (Vcc = 5.0 ± 10%)STD ALTSYM SYM PARAMETER MINtAVAV tc Cycle Time 25tAvwL tAS Address Set-up Time to W LOW 0tWHAX tAH Address Hold Time from W HIGH 0tAVSL tAS Address Set-up Time to 5 LOW 0tSHAX tAH Address Hold Time from 5 HIGH 0tEVWL tES Chip Enable Set-up Time to W LOW 5tWHEX tEH Chip Enable Hold Time from W HIGH 0tEVSL IES Chip Enable Set-up Time to 5 LOW 5tSHEX tEH Chip Enable Hold Time to 5 HIGH 0tWLWH tww Write Pulse Width 15tSLSH tsw Chip Select Pulse Width 16tOVWH tos Data Set-up Time to W HIGH 10tWHOX tOH Data Hold Time from W HIGH 0tOVSH tos Data Set-up Time to S HIGH 10tSHOX tOH Data Hold Time from 5 HIGH 0tWLOZ twz Outputs Hi-Z from W LOWtwHOX tWL Outputs Low-Z from W HIGH 5MAX UNITS NOTESnsnsnsnsnsnsnsnsnsnsnsnsnsnsns8 nsnsCOMPARE MODEThe ~K4202 is in the Compare mode whenever Wand G are HIGH provided a true Chip Enablepattern (Eo-E3) is applied. Chip Select (5) is regardedas a don't care since the user is not concernedwith the data outputs....Q.ut only with the Compare(C,u outputs. Mx and Hx must be HIGH, and CGxactive LOW to enable the Compare outputs for avalid compare hit or miss.The 11 index address inputs (Ao-AlO) define aunique location in the static RAM array. The datapresented on the Data Inputs (00,-00'9 andCDOo) as Tag Data is compared to the internalRAM data as specified by the index. If all bits areequal (match) then a hit condition occurs(Cx = HIGH). If at .Ieast one bit is not equal, thena miss occurs (Cx = LOW).The Compare output will be valid tAVCV from stableaddress, or tovcv from valid tag data provided ChipEnable is true, and CGX is active LOW. Should theaddress be stable with valid tag data, and Chip Enablefalse, then compare access will be within tEVCVfrom true Chip Enable. When executing a write-tocomparecycle fiJ = LOW, and G = LOW or HIGH),Cx will be v~d tIQ/HCV or tGHCV from the latter risingedge of W or G respectively. Finally, whe~ingthe Cx output in the compare mode with CGx,the compare output will be valid tCGL-cv from thefalling edge of CGx.7118371

MK4202(Q)-20COMPARE CYCLE TIMINGElectrical Characteristics and Recommended AC Operating Conditions(O°C:sTA:s70°C) (Vcc = 5.0 ± 10%)STD ALTSYM SYM PARAMETER MINtAVCV tACA Address Compare Access TimetAXCX tACOH Address Compare Output Hold Time 5tovcv tOCA Tag Data Compare Access Timetoxcx tOCH Tag Data Compare Hold Time 2tWLCH tWCH W LOW to Compare HIGHtWHCX tWCOH W Compare Output Hold Time 3tWLCX tWCLZ W to Compare Low-Z 3twHCV twcv W to Compare ValidtGLCH tGCH G LOW to Compare HIGHtGHCX tCGOH G Compare Output Hold Time 3tGLCX tGCLZ G to Compare Low-Z 3tGHCV tGCV G to Compare ValidtEVCV tECA E True to Compare Access TimetEXCX tECOH E False Compare Hold Time 4tEVCX tECLZ E True 10 Compare Low-Z 4tEXCZ tECHZ E False to Compare High-ZtCGL·CV tCGA CGX to Compare Access TimetCGH·CX tCGOH CGx Compare Hold Time 2tCGL·CX tCGLZ CGX LOW to Compare Low-Z 2tCGH-CZ tCGHZ CGX HIGH to Compare High-ZMAX UNITS NOTES20 nsns16 nsns10 nsnsns8 ns10 nsnsns8 ns20 nsnsns8 ns8 nsnsns8 nsNOTE: E = Enable Inputs (EO-E3).RESET MODEThe MK4202 allows an asynchronous resetwhenever AS is LOW regardless of the logic stateon the other input pins. Reset clears all internalRAM bits in CDOo (2048 bits) to a logic zero. Thisoutput can be used as a valid tag bit to ensure a validcompare miss or hit condition. It should be notedthat a valid write cycle is not allowed during a resetcycle (W = LOW, S = LOW, RS = LOW, and ChipEnable is true). The state of the data outputs is delermJrles!by th~nput control logic pins: Chip Enable,S, G, and W (see truth table). Should a resetoccur during a valid compare cycle, and the CDOovalid tag bit is set to a logic (1), then C.JL!Vill goLOW at tRSL-CL from the falling edge of RS.8/18372

MK4202(Q)-20RESET CYCLE TIMINGElectrical Characteristics and Recommended AC Operating Conditions(O"CsTAs70"C) (Vcc = 5.0 ± 10%)STD ALTSYM SYM PARAMETER MINtRLSL-AV tRsc Reset Cycle Time 25tRSL-RSH tRSW Reset Pulse Width 25tRSL-CL tRSCL AS LOW to Compare Output LOWtRSH-AV tRSR Address Recovery Time 0tRSH-EV tRSR Chip Enable Recovery Time 0MAX UNITS NOTESnsns25 nsnsnsFORCE HIT AND FORCE MISSThe MK4202 can force either a miss or hit conditionon the Cx output by asserting Mx or Hx LOW.A Force Miss overrides a Force Hit condition andis not dependent upon Compare Output Enable(CGX> (see truth table). The Cx output will go HIGHwithin tHLCH from the falling edge of Hx, or Cx willgo LOW within tMLCL from the falling edge of Mx.All Mx and Hx inputs must be HIGH during a validcompare cycle.FORCE HIT OR MISS CYCLE TIMINGElectrical Characteristics and Recommended AC Operating Conditions(O"CsTAs70"C) (Vcc = 5.0 ± 10%)STD ALTSYM SYM PARAMETER MINtHLCH tHA Hx to Force Hit Access TimetHHCZ tHHZ Hx to Compare High-ZtHL-CGX tHS Force Hit to CGx Don't Care 2tHH-CGH tHR Force Hit to CGX Recognized 2tMLCL tMA Mx to Force Miss Access TimetMHCZ tMHZ Mx to Compare to High-ZtML-CGX tMS Force Miss to CGx Don't CaretMH-CGH tMR Force Miss to CGx Recognized 2tMLHX tMHS Force Miss to Hx Don't Care 2tMHHH tMHR Force Miss To Hx Recognized 2MAX UNITS NOTES8 ns5 nsnsns8 ns5 ns2 nsnsnsns9/18373

MK4202(Q)-20FIGURE 5. W WRITE CYCLEt"VAYADDRESS-t"vWL\II1\VALID ADDRESStWHAX I--TRUE CHIP ENABLE PATTERN\~-------IW~H------~DOr~ '- t_IOV_W_:A_;.:_,._IN __ IW_H ......FIGURE 6. ~ WRITE CYCLEADDRESSVALID ADDRESSTRUE CHIP ENABLE PATTERN~-------ISLSH-------o-lDOE--'-~·:C r----------------1- DATA IN10/18374

MK4202(Q)-20FIGURE 7. READ CYCLEDOFIGURE 8. ADDRESS READ CYCLEFIGURE 9. CHIP ENABLE READ CYCLEEo·E.{TRUE CHIP ENABLE PATTERN1\=--= .~V- IEXQZ r-~iDQ DATA OUT :-11/18375

MK4202(Q)-20FIGURE 10. CHIP SELECT READ CYCLEDOFIGURE 11. OUTPUT ENABLE READ CYCL-EDOFIGURE 12. FORCE HIT AND FORCE MISSVALID HITVALID MISS~ __ --'I VOL376

MK4202(Q)-20FIGURE 13. SUMMARY COMPARE CYCLEADDRESS \It VALID ADDRESS 'VIII\.DOt"YAY'AVCV-- r-\1/TRUE CHIP ENABLE PATTERN-- F'EVCVt EVCX11\ 11\----1/DATA IN1-'ovcvr-'CG~'CGL-ex ~-'AXex\1/FALSE CHIP ENABLEI'EXC> j---'EXex- r-t~~JI\.-tVIr--DXCXH-J~'CGH-CX ......:---HIT/MISS VALIDNOTE:Wand G are both assumed to be HIGH.Hx and Mx are both assumed to be HIGH.FIGURE 14. COMPARE CYCLEADDRESS __________________ VALID ADDRESS---J\~~ ______________________ VALID ADDRESS_DODATA IN___________________ V_A_L_ID_H_I_TI_M_IS_S ____________--'~~____V_A_LI_D_H_IT_'_M_IS_S _____NOTE:Wand G are both HIGH, CGX is lOW, and a true Chip Enable pattern ispresent. Hx and Mx are both assumed to be HIGH.13/1837:7

MK4202(Q)-20FIGURE 15. LATE WRITE· HIT CYCLETRUE CHIP ENABLE PATTERN~INOTE:G is HIGH and a Valid Address is present. HX and Mx are both assumedto be HIGH.FIGURE 16. COMPARE· WRITE HIT· COMPARE CYCLEHITCOMPARENOTE:G is HIGH and a Valid Address is present. Hi and Mx are both assumedto be HIGH, with CGX LOW.FIGURE 17. LATE READ· HIT CYCLETRUe CHIP ENABLE PATTERNI-INOTE:W IS HIGH and a Valid Address is present. HX and Mxare both assumed10 be HIGH14118378

MK4202(Q)-20FIGURE 18. COMPARE - READ HIT - COMPARE CYCLEVALID COMPAREHITNOTE,W is HIGH and a Valid Address IS present HX and MX are both assumedto be HIGH, with CGX lOWFIGURE 19. EARLY WRITE - HIT CYCLENOTE,G IS HIGH and a Valid Address IS present, with (EO-E3l - True. HX and MXare both assumed to be HIGHFIGURE 20. EARLY READ - HIT CYCLEt=~'1 ---1,~ r­-------') ~~ ~ t-'".a }~ __________ V-,O","Hr- HIT ~I.j _______NOTE,W is HIGH and a Valid Address is present, with (EO-E3l = True. HX and Mxare both assumed to be HIGH.15/18379

MK4202(Q)-20FIGURE 21. RESET CYCLEr ___ --'WRITE______ ~r't t AVAV ---------------------~ ~--------------~ADDRESSVALID ADDRESSb10YSH~ ISHDXtWHDXtOVWHDQDATA INNOTE:Reset during an active write cycle is not allowed A write cycle may disruptReset, but will not damage device.FIGURE 22. VALID COMPARE - RESET~"~"1__ ~ C __ IRSL._CLVALID COMPARE_______________ _NOTE: CDQo is presumed 10 be HIGH.16/18380~ SGS-THOMSON. .., I ii10©oo@rn~rn©vOO@illO~

MK4202(Q)-20ABSOLUTE MAXIMUM RATINGSVoltage on any pin relative to Vs$. ......................................... -1.5 to 7.0 voltsAmbient Operating Temperature (T,J ............................................ 0 to 700CAmbient Temperature under Bias .......................................... -55°C to 1250CAmbient Storage Temperature (Plastic) ..................................... -55°C to 1250CTotal Device Power Dissipation ................................................. 2.5 WattsRMS Output Current per Pin ...................................................... 25mAStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at these or any other condition above those indicatedin the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods may affect device reliability.RECOMMENDED DC OPERATING CONDITIONS(TA = 0 to 70°C)SYMVccVssVIHVILPARAMETERSupply VoltageSupply VoltageLogic 1 InputLogic 0 InputLIMITSMIN TYP MAX UNITS NOTE4.5 5.0 5.5 V0 0 0 V2.2 Vcc+0.3 V 5-0.3 0.8 V 5NOTE: All voltages referenced to V SS.DC ELECTRICAL CHARACTERISTICS(TA = 0 to 70°C, Vcc = ± 10%)SYMIccPARAMETERAverage Power Supply CurrentICCA Active Power Supply Current (f = 0)ICCDIS61IlLIOLVOHVOLDynamic Power Supply Current per MHzTTL Standby CurrentInput Leakage CurrentOutput Leakage CurrentLogic 1 Output Voltage (lOUT = -4mA)Logic 0 Output Voltage (lOUT = 8 rnA)NOTES1. Measured with outputs open. VCC max.2. Measured with VIN = O.OV to Vcc.3. Measured at CDQO, DQ1-DQ19, Co and C1'CAPACITANCE[TA = 25°C, f = 1.0 MHz)LIMITSMIN TYP MAX UNITS NOTE225 rnA 1150 rnA 11.2 mNMHz 170 rnA 1-1 +1 pA 2-10 +10 pA 32.4 V 40.4 V 44. All voltages referenced to VSSQ.5. Inputs (PO-P3l require VIH min. = 4.5 volts and VIL max.= 0.5 volts.LIMITSSYMCICoPARAMETERInput CapacitanceOutput CapacitanceNOTESI. Sampled, not 100% tested. Measured at 1MHz.TYP MAX UNITS NOTE4 4 pf 18 10 pf 1,22. Measured at all data 1I0's, CO and C1.17118381

MK4202(Q)-20AC TEST CONDITIONSInput Levels ............................................................... 0 to 3 VoltsTransition Times ................................................................. 5 nsInput and Output Reference Levels .............................................. 1.5 VoltsAmbient Temperature ........................................................ 0· to 7O"CV CC' •.•.•..............•.•......•.................................... 5.0 Volts ± 10%FIGURE 23. EQUIVALENT OUTPUT LOAD CIRCUIT+5V +5V470 OHMS 470 OHMSDUT ---41-------,DUT240 OHMS30pf·240 OHMS5pf·(A)(B)• INCLUDES SCOPE AND TEST JIG.ORDERING INFORMATIONPART NUMBER ACCESS TIME CYCLE TIME PACKAGE TYPE TEMPERATUREMK4202(Q)·20 20ns 25ns 68 pin PLCC O"C to 7O"CTAGRAM is a trademark of SGS:rHOMSON Microelectronics, Inc.18118382

• 8K x 8 CMOS SRAM WITH ON BOARD 8-BITCOMPARATOR• ADDRESS TO COMPARE ACCESS 35/45155ns• FAST CHIP SELECT TO COMPARE ACCESS20/2513On8• MATCH OUTPUT (OPEN DRAIN) WITH FASTTAG DATA TO COMPARE ACCESS OF25130135ns (MAX.)• STATIC OPERATION - NO CLOCKS OR TIMINGSTROBES REQUIRED• ALL INPUTS AND OUTPUTS ARE FULLY TTLCOMPATIBLE• FULL CMOS FOR LOW POWER OPERATION• FLASH CLEAR FUNCTION• THREE-STATE OUTPUT• STANDARD 28-PIN PACKAGE IN 600 MIL DIPAND 32-PIN LCC• HIGH SPEED ASYNCHRONOUS RAM CLEAR(CYCLE TIME = 2 x tAVAV)PIN NAMESAo - A12DQo - DQ 7SWGVee~MATCHMK48H74 TRUTH TABLE- Address Inputs- Data InpuUOutput- Chip Select- Write Enable- Output Enable- +5V- GroundReset Flash ClearMatch OutputMK48H74(N, P, E)-35/45/5564K (SK x S-BIT) CMOS TAGRAMTMNDIP-28(Plastic Package)FIGURE 1. PIN CONNECTIONSADVANCED DATARS 1 28 VeeA12 2 27 WA7 3 26 MATCHAS 4 25 ASAS 5 24 A9A4 6 23 AllA3 7 22 GA2 8 21 Al0AI 9 20 SAO 10 19 D0 7DOo 11 18 D0 6DO, 12 17 DOsD0 2 13 16 D0 4Vss 14 15 D0 3VI S G RSX X X LX H X HH L H HH L H HH L L HL L X HMODEReset ClearDeselectMiss-NOmatchMatchReadWriteDOMATCH- HighHigh-ZHighDINLowDINHighQ OUTHighDINHighJune 19881/11This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.383

MK48H74(N,P,E)·35/45/55DESCRIPTIONThe MK48H74 is a 65,636-bit fast static cache TA­GRAM organized as 8K x 8 bits. It is fabricated usingSGB-THOMSON's low power, high performance,CMOS technology. The MK48H74 faatur8s fully staticoperation requiring no external clocks or timingstrobes, and equal address access and cycle times.The device requires a single +5V ±10 percent sup­. ply, and is fully TTL compatible.The MK48H74 has a fast Chip Select control for highspeed operation to Match Compare valid, anddevice selectldeselect operations. Additionally, theMK48H74 provides a Reset Clear, and Match comparepin. The Reset Clear input provides an asynchronousRAM clear control which clears all internalRAM bits to zero in only two cycles. The MATCHoutput features an open-drain for wired OR operation.During a match compare cycle, an on-board8-bit comparator compares the Data Inputs (8-bitTAG) at the specified address index (A()"A1~ to theinternal RAM data. If a match exists, the MATCHoutput issues a HIGH match valid signal. If a misscondition exists, where at least one bit of TAG datadoes not match the internal RAM, then the MATCHoutput issues a LOW miss signal.OPERATIONSREAD MODEThe MK46H74 is in the read mode whenever WriteEnable f!N) is HIGH with Output Enable (G) LOW,and Chip Select (5) is active. This provides accessto data from eight of 65,536 locations in the staticmemory array. The unique address specified by the13 Address Inputs defines which one of the 81928-bit bytes is to be accessed.Valid data will be available at the eight Output pinswithin tAvov after the last stable address, providingG is LOW, and 5 is LOW. If Chip Select or OutputEnable access times are not met, data access willbe measured from the limiting parameter (t~LQ\L or~LQV) rather than the address. The state of tne DQpins is controlled by the 5, G, and W control signals.Data out may be indeterminate at tslox andtGlOX' but data lines will always be valid at tAvov'READ CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O"CsTAs70"C) (Vee = 5.0 ±10%)SYMBOLS 48H74·35 48H74·45 48H74·55ALT. STD. PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTESt~c tAVAV Read Cycle Time 35 45 55 nstM tAVOV Address Access Time 35 45 55 ns 1tcSA tSlQV Chip Select Access Time 20 25 30 nstOEA ~lQV Output Enable Access 20 25 30 ns 1TimeteSl tSlOX Chip Select to Output 5 5 5 nsLow-ZtoEl ~LOX Output Enable to Low-Z 0 0 0 nstesz tSHQZ Chip Select to High-Z 15 20 25 nstoEZ ~HQZ Output Enable to High-Z 15 20 25 ns 2toH tAXQX Output Hold From Address 3 3 3 ns 1Change2N1384

MK48H74(N, P, E)-35/45/55FIGURE 2. READ TIMING NO. 1 (ADDRESS ACCESS)14--------- tAVAY ---------~ADDRESS~----- I AVOV -----~t AxaxDO PREVIOUS DATA DATA VALIDNOTE: Chip Select and Output Enable are presumed valid, W = VIH'FIGURE 3. READ TIMING NO.2 (W = VADDRESSDO3111385

MK48H74(N,P,E)-35/45/55WRITE MODEThe MK48H74 is in the Write mode whenever theVIi and 8 pins are LOW. Chip Select or VIi must beinactive during Address transitions. The Write beginswith !he concurrence of Chip Select being activewith W LOW. Therefore address setup timesare referenced to Write Enable and Chip Select astAvwL and tAVSL' and is determined to the latter occurringedge. The Write cycll!.can~e terminatedby the earlier rising edge of S or W.!Dhe Output is enabled (8 = LOW, G = LOW), thenW will return the outputs to high impedance withintWLQZ of its falling edge. Care must be taken toavoid bus contention in this type of operation. Datainmust be valid fortovwH to the rising edge ofWrite Enable, or to the rising edge of S, whicheveroccurs fi~t, a'l9 remain valid tWHOX after the risingedge of S or W.WRITE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O°C:sTA:s70°C) (Vee = 5.0 ±10%)SYMBOLS 48H74-35 48H74-45 48H74-55ALT. STD. PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStwe tAVAV Write Cycle Time 35 45 55 nstAS tAVWL Address Set-up Time to 0 0 0 nsWrite Enable LowtAS tAVSL Address Set-up Time to 0 0 0 nsChip SelecttAW tAVWH Address Valid to End 25 35 45 nsof WritetWEW tWLWH Write Pulse Width 25 35 45 nstAH tWHAX Address Hold Time after 0 0 0 nsEnd of Writetesw tSLSH Chip Select to End 25 35 45 nsof WritetWR tSHAX Write Recovery Time 0 0 0 nsto Chip Deselecttow tOVWH Data Valid to End of 25 30 30 nsWritetOH tWHDX Data Hold Time 0 0 0 nstWEL tWHOX Write High to Output 0 0 0 ns 2Low-Z (Active)tWEZ tWLQZ Write Enable to Output 15 20 25 ns 2High-Z4111386

MK48H74(N, P, E)-3S/4S/SSFIGURE 4. WRITING TIMING NO. 1 (W CONTROL)14----------- tAVA" -----------t~ADDRESS1-------- 'AVWH ---------.ji'INS''SLSH --------t-- tE1HAXtGHQZ----"'iDQDATA IN VALIDFIGURE 5. WRITING TIMING NO.2 (5 CONTROL)~ V-ADDRESS---.Ji'--'-t,wWH ISHU ....\IstlllI--'~,-~t WLWHDO_-----IE-tOVWMDATA·IN VALID" .tWHD~Jc5/11387

MK48H74(N, P, E)-35/45/S5COMPARE MODEThe MK48H74 is in the Compare mode wheneverWand G are HIGH provided Chip Select (8) is activeLOW. The 13 index address inputs (Ao-A12l definea unique location in the static RAM array. Thedata presented on the Data Inputs (DOo-D0 7) asTag Data is compared to the internal RAM data asspecified by the index. If all bits are equal (match)then a hit condition occurs (MATCH = HIGH). Whenat least one bit is not equal, then MATCH will goLOW signifying a miss condition.The MATCH output will be valid tAVMV from st~bleaddress, or tTVMV from valid Tag Data when S isLOW .. Should the address be stable with valid TagData, and the device is deselected (8 = HIGH), thenMATCH will ~e valid tSLMV from the falling edge ofChip Select (S). When executing a write-to-comparecycle 0N = LOW, and G = LOW or HIGH), MATCHwill be v!illd tw,tlMV or tGHMV from the latter risingedge of W or G respectively.MATCH COMPARE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O·CsTAs70OC) fYcc = 5.0 ±10%)SYMBOLS 48H74-35 48H74-45 48H74-55ALT STD PARAMETER MINtAMA tAVMV Address to MATCH Valid -tcSM tSLMV Chip Select to MATCH -ValidtCSMH tSHMH Chip Deselect to MATCH -HightOMA tTVMV Tag Data to MATCH Valid -tOEM tGHMV G High to MATCH Valid -tOEMH tGLMH G Low to MATCH High -tWEM tWHMV W High to MATCH Valid -tWEMH tWLMH W Low to MATCH High -tMHA tAHMV MATCH Hold From 5AddresstMHO tOHMV MATCH Hold From Tag 5DataMAX MIN MAX MIN MAX UNITS NOTES35 - 45 - 55 ns 2,320 - 25 - 30 ns 2,320 - 25 - 30 ns 2,325 - 30 - 35 ns 2,325 - 35 - 45 ns 325 - 35 - 45 ns 325 - 35 - 45 ns 325 - 35 - 45 ns 3- 5 - 5 - ns 3- 5 - 5 - ns 3RESET MODEThe MK48H74 allows an asynchronous reset clearwhenever RS is LOW regardless of the logic stateon the other input pins. Reset clears all internalRAM bits (65536 bits) to a logic zero as long astRSL-RSH is satisfied. The state of the out!1..ut~s determinedby the control logic input pins S, W, andG during reset (see truth table). The MATCH outeM!will go HIGH tRSL-MH from the falling edge ofRS, and all inputs will not be recognged untiltRSH-AV from the rising edge of reset (RS).6111388

MK48H74(N,P,E)-35/45/55RESET CLEAR CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O·CSTAs70"C) (Vee = 5.0V ±10%)SYMBOLS-35 ·45 ·55ALT STD PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStRC tRSC Flash Clear Cycle Time 70 90 110 nstRs>< tRSL.AX Reset Clear (AS) to InputsDon't Care 0 0 0 nstRSV tRSH.AV AS to Inputs Valid 5 10 10 nstRSP tRSL.RSH Reset (AS) Pulse Width 65 85 100 nstRSM tRSL-MH Reset (AS) to MATCH 25 35 45 nsHighFIGURE 6. MATCH COMPARE TIMINGADDRESSf. tAVMv---l 3.'// / / / / / / / ~ ..... ~ I\.Ii LlLi Lj~, I \ \ \ \ \ \ \ \fDQt MXAX:-"'"1~-1~tGLMH-If=~-1tSLMV ..-II>=f ,~~,~~ 3XXXXXX:,~. t ~n r=-MATCHMATCH VALID7111389

MK48H74(N,P,E)-35/45/55APPLICATIONThe MK48H74 operates from a 5.0 volt supply. It iscompatible with all standard TTL families on all inputsand outputs. The device should share a solidground plane with any other devices interfaced withit, particularly TTL devices. A pull-up resistor is alsorecommended for the AS input. This will ensure thatany low going system noise, coupled onto the input,does not drive RS below V 1H minimumspecifications. This will enhance proper deviceoperation, and avoid possible partial flash clear cycles.Additionally, because the outputs can driverail-to-rail into high impedance loads, the MK48H74can also interface to 5 volt CMOS on all inpClts andoutputs.The MK48H74 provides the system designer with64K fast static memory, a MATCH output, and aBYTEWYDE'" on-board comparator - all in onechip. The MK48H74 compares contents of addressedRAM locations to the current data inputs.A logic one (1) output on the MATCH pin indicatesthat the input data and the RAM contents match.Conversely, a logic zero (0) on the MATCH pin indicatesat least one bit difference between the RAMcontents and input TAG data generating a miss. TheMATCH output is constructed with an open drain arrangement.This provides easy wired-OR implementationwhen generating a composite MATCH signal.In a cache subsystem, the MATCH signal providesthe processor or CPU with the necessary informationconcerning wait state conditions. The purposeof a cache subsystem is to maintain a duplicate copyof a portion of the main memory. When a validmatch occurs, the system processor uses data fromthe fast cache memory, and· avoids longer cyclesto the main memory. Therefore, implementing cachesubsystems with the MK48H74, and providing goodhit or match ratio designs will enhance overall systemperformance.Because high frequency current transients will beassociated with the operation of the MK48H74, powerlines inductance must be minimized on the circuitboard power distribution network. Power andground trace gridding or separate power planes canbe employed to reduce line inductance. Thoughoften times not thought of as such, the traces ona memory board are basically unterminated, low impedancetransmission lines. As such they are subjectto signal reflections manifested as nOise,undershoots and excessive ringing. Series terminationin close proximity to the TTL drivers can improvedriver/signal path impedance matching. Whileexperimentation most often proves to be the onlypractical approach to selection of series resistors,values in the range of 10 to 33 ohms often provemost suitable.FIGURE 7. RESET TIMINGCOMPARERESET CLEAR~------------~~-------t~c--------~ADDRESSMATCHMATCH VALID ~XifNOTE: G = HIGH FOR THIS EXAMPLE8111390

M K48H74(N, P, E)-35/45/55ABSOWTE MAXIMUM RATINGSVoltage on any pin relative to GND ....................................... -1.0 V to +7.0 VAmbient Operating Temperature (TA> ......................................... O°C to +70'CAmbient Storage Temperature (Plastic) .................................... -55°C to +125'CAmbient Storage Temperature (Ceramic) .................................. -65°C to +150'CTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 50 mAStresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or other conditions beyond those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(OOC sTA s70OC)SYMPARAMETERMINTYP MAX UNITS NOTESVccSupply Voltage4.55.0 5.5 V 4VssSupply Voltage00 0 V 4VIHLogic 1 Voltage, All Inputs2.2Vcc+0.3 V 4VilLogic 0 Voltage, All Inputs-0.30.8 V 4DC ELECTRICAL CHARACTERISTICS(OOCsTAs70°C) (Vcc = 5.0 V ± 10 percent)SYMPARAMETERMIN MAX UNITS NOTESIcci Average Power Supply Current f = min cycle 125 mA 5Icc2 Average Power Supply Current f = 0 60 mA 6III Input Leakage Current (Any Input Pin) -1 +1 pA 7IOl Output Leakage Current (Any 0 Output Pin) -10 +10 pA 8VOH Output Logic 1 Voltage (lOUT = -4 mAl 2.4 V 4VOL Output Logic 0 Voltage (lOUT = +8 mAl 0.4 V 4VOL Match Output Logic 0 Voltage (lOUT = 18 mAl 0.4 V 4CAPACITANCE(TA = 25OC, f = 1.0 MHz)SYMC IC2NOTESPARAMETERCapacitance on input pinsCapacitance on DO pinsTYP MAX UNITS NOTES4 5 pF 98 10 pF 91. Measured with load shown in Figure 8(A).2. Measured with load shown in Figure 8(B).3. Measured with load shown in Figure 8(C).4. All voltages referenced to GND.5. ICCtis measured as the average AC current with VCC= VCC (max) and with the outputs open circuit. tAVAV= tAVAV (min) duty cycle 100%.6. ICC2 is measured with outputs open circuit.7. Input leakage current specifications are valid for all VINsuch that 0 V

MK48H74(N,P,E)-35/45/55AC TEST CONDITIONSInput Levels ............................................................. GND to 3.0 VTransition Times ................................................................. 5 nsInput and Output Signal Timing Reference Level ...................................... 1.5 VAmbient Temperature ....................................................... O°C to 7QoeVee ............................................................... 5.0 V ± 10 percentFIGURE 8. OUTPUT LOAD CIRCUITS+5.Q V+5.Q V470 OHMS 470 OHMSDEVICEUNDERTEST240 OHMS --1~~.DEVICEUNDERTEST,~- ! ...-::L-- GND- -(A)• INCLUDES SCOPE AND TEST JIG._'-- GND(8)+5.0 V--RL300nDEVICEUNDERTESTMATCH30 pF-'--I~(C)10/11392

MK48H74(N,P,E)-35/45/55ORDERING INFORMATIONPART NUMBER ACCESS TIME PACKAGE TYPE TEMPERATURE RANGEMK48H74N-35 35 ns 28 pin Plastic DIP O"C to 7O"CMK48H74N-45 45 ns 28 pin Plastic DIP O"C to 70 "CMK48H74N-55 55 ns 28 pin Plastic DIP O·C to 7O"CMK48H74P-35 35 ns 28 pin Ceramic DIP O·C to 7O"CMK48H74P-45 45 ns 28 pin Ceramic DIP O"C to 7O"CMK48H74P-55 55 ns 28 pin Ceramic DIP O"C to 7O"CMK48H74E-35 35 ns 32 pin LCC O"C to 7O"CMK48H74E-45 45 ns 32 pin LCC O"C to 70 "CMK48H74E-55 55 ns 32 pin LCC O"C to 70 "CMKNSpeed gradePackage TypeL-_________________ N: Plastic DIPP: Ceramic DIPE: Ceramic LCCL-____________________ Device family andidentification numberSGS.:rHOMSON'-------------------------- prefixTAG RAM is a trademark of SGS.:rHOMSON Microelectronics, Inc.BYTEWYDE is a trademark of SGS-THOMSON Microelectronics, Inc.11/11393

STATIC RAM DEVICESFIFO395

MK4501(N,K)-65/80/10/12/15/20512 x 9 CMOS BiPORT FIFO• FIRST-IN, FIRST-OUT MEMORY BASEDARCHITECTURE• FLEXIBLE 512 x 9 ORGANIZATION• LOW POWER HCMOS TECHNOLOGY• ASYNCHRONOUS AND SIMULTANEOUSREADIWRITE• BIDIRECTIONAL APPLICATIONS• FULLY EXPANDABLE BY WORD WIDTH ORDEPTH• EMPTY AND FULL WARNING FLAGS• RETRANSMIT CAPABILITY• HIGH PERFORMANCENDIP-28(Plastic Package)KPLCC32(Plastic Chip Carrier)FIGURE 1. PIN CONNECTIONSR/WPart No. Access Time Cycle TimeMK4501-65 65 ns 80 nsMK4501-80 80 ns 100 nsMK4501-10 100 ns 120 nsMK4501-12 120 ns 140 nsMK4501-15 150 ns 175 nsMK4501-20 200 ns 235 nsPIN NAMESW = Write XI = Expansion InR = Read XO = Expansion OutRS = Reset FF = Full FlagFLIRT = First Load/ EF = Empty FlagRetransmit Vee = 5 VoltsD = Data In GND= GroundQ = Data OutDESCRIPTIONVi 108 203 302 401 5DO 6Xi 7FF 800 901 1002 1103 1208 13GNO 1411428 vee27 0426 0525 0624 D723 FURl22 As21 EF20 Xci19 0718 0617 0516 0415 R! l:t ~ >'d o is3 2 . 323130132 Pin PLCCTop ViewThe MK4501 is a member of the BiPORT'" MemorySeries, which utilizes special two-port cell techniques.Specifically, this device implements a First­In" .First-Out algorithm, featuring asynchronousreadlwrite operations, full and empty flags, and unlimitedexpansion capability in both word size anddepth. The main application of the MK4501 is as14151617181920a c >'D. ~ IIX: ;:; 8June 19881115397

MK4501(N,K)-65/80/10112115/20a rate buffer, sourcing and absorbing data at different.rates, (e.g., interfacing fast processors and slowperipherals). The full and empty flags are providedto prevent data overflow and underflow. The datais loaded and emptied on a First-In, First-Out (FIFO)baSis, and the latency for the retrieval. of data is approximatelyone load cycle (write). Since the writesand reads are internally sequential;- thereby requiringno address information, the pinout definition willserve this and future high.

MK4501 (N ,K)-65/80/10/12/15/20WRITE MODEThe MK4501 initiatesa Write Cycle (see Figure 3A)on t~ falling edge of the Write Enable control input(W), provided that the Full Flag (FF) is not asserted.Data set-up and hold-time requirements!!lust be satisfied with respect to the rising edge ofW. The data is stored sequentiall~nd independentof any ongoing Read operations. FF is asserted duringthe last valid write as the MK4501 becomes full.Write operations begun with FF low are inhibited.FF will go high tRFF after completion of a validREAD operation. FF will again go low tWFF fromthe beginning of a subsequent WRITE operation,provided that a second READ has not been completed(see Figure 4A). Writes beginning tFFW afterFF goes high are valid. Writes beginn.l!!.9 afterFF goes low and more than tWPI before FF goeshigh are invalid (ignored). Writes beginning lessthan tWPI before FF goes high and less than tFFWlater mayor may not occur (be valid), dependingon internal flag status.FIGURE 3A. WRITE AND FULL FLAG TIMINGLAST VALIDWRITEINVALIDWRITEIN DETERMINANTWRITEFIRST VALIDWRITEAC ELECTRICAL CHARACTERISTICS(O°C:sTA:s +70°C) (Vee = +5.0 volts ± 10%)4501·65 4501·80SYM PARAMETER MIN MAX MIN MAXtwe Write Cycle Time 80 100WP'W Write Pulse Width 65 80tWR Write Recovery Time 15 20tos Data Set Up Time 20 25tOH Data Hold Time 10 10tWFF W Low to FF Low 60 75tFFW FF High to Valid Write 10 10tRFF R High to FF High 60 75tWPI Write Protect Indeterminant 35 354501·10 4501·12 4501-15 4501·20MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES120 140 175100 120 150235 ns200 ns 120 20 25 35 ns35 40 50 65 ns10 10 10 10 ns95 115 145 195 ns 210 10 10 10 ns 295 110 140 190 ns 235 35 35 35 ns 23115399

MK4501 (N, K)-65/80/1 0112/15/20READ MODEThe MK4501 initiates a Read Cycle (see Figure ~)on the falling edge of Read Enable control input (R),provided that the Empty Flag (EF) is not asserted.In the Read mode of operation, the MK4501 providesa fast access to data from 9 of 4608 locationsin the static storage array. The data is accessed ona FIFO basis indee,endent of any ongoing WRITEoperations. After R goes high, data outputs willreturn to a high impedance condition until the nextRead operation.In the event that all data has been read from theFIFO, the EF will go low, and further Read opera-tions will be inhibited ~ data outputs will remainin high impedance). EF will go high tWEF aftercompletion of a valid Write operation. EFwill again go low tAEF from the beginning a subsequentREAD operation, provided that a secondWRITE has not been completed ~e Figure 4B).Reads beginning tEFA after ELgoes highare valid. Reads begun after.-£F goes lowand more than t API before EF goes highare invalid Q9.nored). Reads beginning less thantAP I before EF goes high and less than tEFA latermayor may not occur (be valid) depending on internalflag status.FIGURE 3B. READ AND EMPTY FLAG TIMINGw..AC ELECTRICAL CHARACTERISTICS(O°C:s;TA:S; +70°C) (VCC = +5.0 volts ± 10%)SYM PARAMETER4501·65 4501·80tAC Read Cycle Time 80 100tA Access Time 65 80tAA Read Recovery Time 15 20APW Read Pulse Width 65 80tAL R Low to Low Z 0 0tov Data Valid from HighR 5 5tAHZ R High to High Z 25 25tAEF R Low to EF Low 60 75tEFA EF High to Valid Read 10 10tWEFW High to.EF High 60 75tAPI Read Protect Indeterminant 35 354501·10 4501·12 4501·15 4501·20MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES120 140 175 235 ns100 120 150 200 ns 220 20 25 35 ns100 120 150 200 ns 10 0 0 0 ns 25 5 5 5 ns 225 35 50 60 ns 295 115 145 195 ns 210 10 10 10 ns 295 110 140 190 ns 235 35 35 35 ns 24/15400

MK4501(N ,K)-65/80/10/12/15/20FIGURE 4A. READIWRITE TO FULL FLAGRIRFFIFFwFIGURE 4B. WRITE/READ TO EMPTY FLAGw5115401

MK4501 (N, K)-65/80/10/12/15/20RESETThe MK45Q!Js reset (see Figure 5) whenever theReset pin (RS) is in the low state. During a Reset,both the internal read and write pOinters are set tothe first location. Reset is required after power up,before a Write operation can begin.FIGURE 5 RESETAlthough neither W or R need be high when RSgoes low, both Wand R must be high tRSS beforeRS goes high, and must remain hightRSR afterwards. Refer to the fo"o~ng discussionfor the required state of FURT and XI during Reset.IRS~\ I--dlASSI~ ~I~w~I I~R~IRse·1-I,~~ }-x xx .xxxxxxxxxxxx xxx.. xxxx~EF ~xxxxxx xx.xx .xxx." xxx»"x xxxxxxxxxmNOTE~ and FF may change status during Reset,but flags will be valid at IRse'AC ELECTRICAL CHARACTERISTICS(O°C:sTA:s +70°C) (Vee = +5.0 volts ± 10%)4501·65 4501·80SYM PARAMETER MIN MAX MIN MAXtRse Reset Cycle Time 80 100t RS Reset Pulse Width 65 80t RSR Reset Recovery Time 15 20tRSS Reset Set Up Time 45 604501·10 4501·12 4501-15 4501-20MIN MAX MIN MAX MIN MAX MIN MAX UNITS120 140 175 235 ns100 120 150 200 ns20 20 25 35 ns80 100 130 180 nsNOTES16/15402

MK4501(N, K)-65/80110/12/15/20RETRANSMITThe MK4501 can ge made to retransmit (re-readpreviously read data) after the Retransmit pin (RT)is pulsed low. (See Figure 6).A Retransmit operation sets the internal read pointerto the first physical location in the array, Q.ut will notaffect the position of the write pointer. R must beinactive tATS before AT goes high, and must remainhigh for tATR afterwards.The Retransmit function is particularly useful whenblocks of less than 512 Writes are performed betweenResets. The Retransmit feature is not compatiblewith Depth Expansion.FIGURE 6. RETRANSMIT~tRTC-~·11~.~ __________ • ______ t~ __________________ •• 1VJI~.~ _______________ t~ ______________ ~~t~. __IiFLAG VALIDNOTEEF and ~ may change status during Retransmit,but flags will be valid at tRTC'AC ELECTRICAL CHARACTERISTICS(O"CsTAs +70°C) (Vee = +5.0 volts ± 10%)4501·65 4501·80SYM PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTEStATe Retransmit Cycle Time 80 100tRT Retransmit Pulse Width 65 80tATR Retransmit Recovery 15 20TimetATS Retransmit Setup 45 60Time4501·10 4501·12 4501·15 4501·20120 140 175 235100 120 150 20020 20 25 3580 100 130 180nsns 1nsns7115403

M K4501(N, K)-65/80110/12115/20SINGLE DEVICE CONFIGURATIONWIDTH EXPANSIONA single MK4501 may be used when application requirementsare for 512 words or less. The MK4501is placed in Single Device Configuration mode wh~the chip is Reset with the Expansion In pin (XI)grounded (see Figure 7).FIGURE 7. A SINGLE 512 x 9 FIFO CONFIGURATIONEXPANSION OUT(r- -WRITE (WI (RI READWord width may be increased simply by connectingthe corresponding input control signals of multipledevices. Status Flags (EF and FF) can bedetected from anyone device. Figure 8 demonstratesan 18-bit word width by using two MK4501s.Any word width can be attained by adding additionalMK4501s.99JI.L j.,DATA IN/\ 4/DATA OUT5_ r0.. FULL FLAG IFFIY1 (EFI EMPTY FLAGRESET IRsI (FITI RETRANSMITEXPANSION IN (xi) 1FIGURE 8. A 512 x 18 FIFO CONFIGURATION (WIDTH EXPANSION)DATA INWR ITE --'.!!.!.....--+iFULL FLA ... G~(=FF=I __--lR ESET_-,(.:.:R.::.S I'-----i~IAI READ~--------l--4--~-(--~EF"I~EM~P~T~Y~F~lAG5(Afl RETRANSMITI+::---------l - - L_9 9oEXPANSION IN (Xi)DATA OUTNOTEFlag detectipn is accomplished by monitoring the FF and EF signals on either(any) device used in the width expansion configuration. Do not connect flagoutput signals together.8/15404

MK4501 (N, K)-65/80/10/12/15/20[)EPTH EXPANSION (DAISY CHAIN)rhe MK4501 can easily be adapted to applicationsNhen the· requirements are for greater than 512NOrdS. Figure 9 demonstrates Depth Expansion us­Ing three MK4501s. Any depth can be attained byadding additional MK4501s.The MK4501 operates in the Depth Expansion configurationafter the chip is Reset under the belowlisted conditions.1. The first device must be designated by groundingthe First Load pin (FL). The Retransmit function isnot allowed in the Depth Expansion Mode.External logic is needed to generate a compositeFull F!!g and Empty Flag. This requires the ORingof all EFs and the ORing of all FFs (i.e,J1I mustoe set to generate the correct composite FF or EF).FIGURE 9. A 1536 x 9 FIFO CONFIGURATION (DEPTH EXPANSION)2. All other devices must have FL in the high state.3. The Expansion Out (XO) pin o~ach device mustbe tied to the Expansion In (XI) pin of the nextdevice.DATA IN -------1----.-.,..-,r-r--.,--,---f-----,) DATA OUTH--1_+-+-------vcc9/15405----------.--------~-------.----- ---~

MK4501(N,K)-65/80110112/15/20EXPANSION TIMINGFigures 10 and 11 illustrate the timing of the Expan·sion Out and Expansion In signals. Discussion ofExpansion Out/Expansion In timing is provided toclarify how Depth Expansion Works. Inasmuch asExpansion Out pins are generally connected onlyto Expansion In pins, the user need not be con·cerned with actual timing in a normal Depth Ex·panded application unless e~eme propagationdelays exist between the XC/XI pin pairs.Expansion Out pulses are the image of the WRITEand READ signals that cause them; delayed in timeby tXOL and tXOH' The Expansion Out signal ispropagated when the last physical location in thememory array is written and againwhen it is read(Last Read). This is in contrast to when the Full andEmpty Flags are activated, which is in response towriting and reading a last available location.FIGURE 10. EXPANSION OUT TIMING[ lLASTWRITE TOLAST PHYSICALLOCATIONVi '\_______-'1READ FROMPHYSICALLOCATIONR ~~ ____ ----,{m -9~!----f" ~'"i ~~JAC ELECTRICAL CHARACTERISTICS(O°CsTAs +70OC) (Vee = +5.0 volts ± 10%)SYM PARAMETER4501·65 4501·80txoL Expansion Out Low 55 70txoH Expansion Out High 60 804501·10MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES75904501-12 4501·15 4501-2090 115 150 ns100 125 155 ns10115406

MK4501 (N ,K)-65/80110/12/15/20When in Depth Expansion mode. a given MK4501will begin writing and reading as soon as validWRITE and READ signals begin. provided FLwas grounded at RESET time. A MK4501 in DepthExpansion mode with FL high at RESETwill not begin writing until after an Expansion Inpulse occurs. It will not begin reading untila second Expansion In pulse occurs and the EmptyFlag has gone high. Expansion In pulses mustoccur tXIS before the WRITE and READ signalsthey are intended to enable. Minimum ExpansionIn pulse width. tXI• and recovery time. tXIR' must beobserved.FIGURE 11. EXPANSION IN TIMINGXiW'\IIX'~IX'.-\~14IWRITE TOFIRST PHYSICALLOCATIONIXlR==j'\[.-READ\IFROMFIRST PHYSICALLOCATIONrAC ELECTRICAL CHARACTERISTICS(O°C~TA~ +70°C) (Vee = +5.0 volts ± 10%)SYM PARAMETER4501·65 4501·80tXI Expansion In Pulse 60 75WidthtXIR Expansion In Recovery 15 20TimetXIS Expansion In Setup 25 30Time4501·10 4501-12 4501·15 4501·20MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES95 115 145 195 ns 120 20 25 35 ns45 50 60 85 ns11/15407

MK4501(N, K)-65/80110/12/15/20COMPOUND EXPANSIONThe two expansion techiques described above canbe applied together in a straight forward mannerto achieve large FIFO arrays (see Figure 12).BIDIRECTIONAL APPLICATIONSApplications, which require data buffering betweentwo systems (each system capable of READ andWRITE operations), can be achieved by pairingMK4501s, as shown in Figure 13. Care must betaken to assure that the ap.QL0priate flag is monitoredby each ~stem. (Le.,£f is monitored on thedevice where W is used; EF is monitored on thedevice where R is used.) Both Depth Expansion andWidth Expansion may be used in this mode.FIGURE 12. COMPOUND FIFO EXPANSIONoo·oaoo·oa00·017OO·ONA.W.RSOO·ON09·0NOla·ONNOTES1. For depth expansion block see DEPTH EXPANSION Section and Figure 9.2. For Flag operation see WIDTH EXPANSION Section and Figure B.FIGURE 13. BIDIRECTIONAL FIFO APPLICATIONAw. R,;"4F~ 5EF.l\ ° 1o.o·aO~.SYSTEM A - - - - - - - - - - - - - - SYSTEM B~R,;o.o·a~4 O.o·a501w.EF.FF.12/15408

MK4501{N,K)-65/80/10/12/15/20ABSOWTE MAXIMUM RATINGS·Voltage on any pin relative to GND ....................................... -0.5 V to + 7.0 VOperating Temperature TA (Ambient) ........................................ OOC to + 70°CStorage Temperature .................................................. -55OC to + 125°CTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 20 mA·Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. Thisis a stress rating only, and functional operation of the device at these, or any other conditions above those indicatedin the operational sections of this specification, is not implied. Exposure to absolute maximum ratings for extendedperiods may affect device reliability.RECOMMENDED DC OPERATING CONDITIONS(OOC s T A s +70OC)SYMPARAMETERMINTYP MAX UNITSNOTESVeeSupply Voltage4.55.0 5.5 V3GNDGround00 0 VVIHVILLogic "1" Voltage All InputsLogic "0" Voltage All Inputs2.0-0.3Vee + 1 V0.8 V33, 4DC ELECTRICAL CHARACTERISTICS(OOCsTAs+70OC) (Vee = 5.0 volts ± 10%)SYMPARAMETERMIN MAX UNITSNOTESIlLInput Leakage Current (Any Input)-1 1 pA5IOLVOHVOLleclIcc2Output Leakage CurrentOutput Logic "1" Voltage lOUT = -1 mAOutput Logic "0" Voltage lOUT = 4 mAAverage Vee Power Supply CurrentAverage Standby Current(R = iii = AS = FURT = VIH)-10 10 pA2.4 V0.4 V80 mA8 mA63377lee3Power Down Current(All Inputs~ Vee -0.2 V)500 pA7AC ELECTRICAL CHARACTERISTICS(TA = 25OC, f = 1.0 MHz)SYMPARAMETERTYPMAXNOTESCICapacitance on Input Pins7 pFCQCapaCitance on Output Pins12 pF8NOTES1. Pulse widths less than minimum values are not allowed. 5. Measured with 0.4sVINsVCC.2. Measured using output load shown in Output Load6. R""VIH' 0.4""VOUTsVCC'Diagram.7. ICC measurements are made with outputs open.3. All voltages are referenced to ground.8. With output buffer deselected.4. -1.5 Volt undershoots are allowed for 10 ns once percycle ..13115409

MK4501 (N, K)-65/80110112115/20FIGURE 14. OUTPUT LOAD5VDEVICEUNDERTEST1.1 K!I680n;: :::: 30 pF--AC TEST CONDITIONS:Input Levels ............................................ GND to 3.0 VTransition Times ................................................... 5 nsInput Signal Timing Reference Level ................... 1.5 VOutput Signal Timing Reference Level 0.8 V and 2.2 VAmbient Temperature ................................ O"C to 7O"CVee ........................................................ 5.0 V ± 10%FIGURE 15. MK4501 PLASTIC (N TYPE) DUAL-IN-LlNE, 28 PINS1'l{'l{'l{'l{'l{'l{'l{'l{'l{'l{'l{'l{'l{'l0I V v v v v V V.V V V V V V -l,~I "----jA2~hJ(Dim.mmInche.Min Max Min MaxNote.A - 5.334 - 210 2Al 0.381 - .015 - 23.556 4.064 .140 .1608 0.381 0.533 .015 .021 381 1.27 1.778 .050 .070C 0.203 0.304 .008 .012 3D 36.576 37.338 1.440 1.470 1D1 1.651 2.159 .065 .085E 15.24 15.875 .600 .625E1 13.462 14.224 .530 .560NOTES e1 2.28S 2.794 .090 .1101. OVERALL LENGTH INCLUDES .010 IN. eA 15.24 17.78 .SOO .700FLASH ON EITHER END OF THE PACKAGE.L 3.048 - .120 -2. PACKAGE STANDOFF TO BE MEASUREDPER JEDEC REQUIREMENTS.3. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. WHENSOLDER LEAD FINISH IS SPECIFIED.14115410

MK4501(N,K)-65/80/10/12/15/20FIGURE 16. MK4501 PLASTIC LEADED CHIP CARRIER, 32 PIN (K TYPE)ORDERING INFORMATION~2 PLest· DENOTES-A-~01-PIN IlnnnI NOM~-,.. ,.g~§- ::IN 1q~~,~~ S l=~~ [1S EI aJ ~1 ~ ~uuuuuuJliJ~ D2/E2 ~ U ~~ ~ nc:; ~ .. "'''' .. '''''' .. u =---e~RRRF-'mmInch ••Dim.8!1'~>'d!! Min Max Min Max/4 3 2 r 323'30 A 3.048 3.556 .120 .140D2~ 5 2t DO01 [ Ii 2.DOC 7 27Xi [ ,""'A1 1.981 2.413 .078 .0956 0.330 0.533 .013 .021" FliRT 61 0.660 0.812 .026 .032Ff [ 9 32 Pin PLee u AiTop VI_ooe D 12.319 12.573 .485 .495,g"Ql [ 11 23 iO "D1 11.353 11.506 .447 .453Ne[ 12 22 0102[ 13" ..D2 9.906 10.922 .390 .430E 14.859 15.113 .585 .595'.15'11 17 18 19 20'8 a >"a ~ I.,; ;; :;E1 13.893 14.046 .547 .553E2 12.446 13.462 .490 .530PART NO. ACCESS TIMERIW CYCLETIMEMK4501N-65 65 ns 80 nsMK4501N-80 80 ns 100 nsMK4501N-10 100 ns 120 nsMK4501N-12 120 ns 140 nsMK4501N-15 150 ns 175 nsMK4501N-20 200 ns 235 nsMK4501K-65 65 ns 80 nsMK4501K-80 80 ns 100 nsMK4501K-10 100 ns 120 nsMK4501K-12 120 ns 140 nsMK4501K-15 150 ns 175 nsMK4501K-20 200 ns 235 nsT TSGS.:rHOMSONDevice familyPrefixand numberidentificationCLOCK FREQ. PACKAGE TYPE12.5 MHz10.0 MHz8.3 MHz7.1 MHz5.7 MHz4.2 MHz12.5 MHz10.0 MHz8.3 MHz7.1 MHz5.7 MHz4.2 MHz28 Pin Plastic DIP28 Pin Plastic DIP28 Pin Plastic DIP28 Pin Plastic DIP28 Pin Plastic DIP28 Pin Plastic DIP32 Pin Plastic Lee32 Pin Plastic Lee32 Pin Plastic LCe32 Pin Plastic Lee32 Pin Plastic Lee32 Pin Plastic Lee~Package typeN: Plastic DIPK: Plastic LeeTEMPERATURERANGE0° to ?OoC0. 0 to ?OOC0° to ?OOC0" to ?OOC0° to ?Ooe0° to ?Ooe0° to ?Ooe0° to ?OOC0° to ?Ooe0° to ?Ooe0° to ?OOC0° to ?OoeTSpeed gradeAccess Time15/15411

~ SGS-1HOMSON,."'! I. ~u©oo@rn[brn©'j]'oo@~u©~MK4503{N, K)-50/65/80/10/12/15/20• FIRST-IN, FIRST-OUT MEMORY BASEDARCHITECTURE• FLEXIBLE 2048 x 9 ORGANIZATION• LOW POWER HCMOS TECHNOLOGY• ASYNCHRONOUS AND SIMULTANEOUSREADIWRITE• BIDIRECTIONAL APPLICATIONS• FULLY EXPANDABLE BY WORD WIDTH ORDEPTH• EMPTY AND FULL WARNING FLAGS• RETRANSMIT CAPABILITY• HIGH PERFORMANCE• HALF FULL FLAG IN SINGLE DEVICEMODERIWPart No. Access Time Cycle TimeMK4503-50 50 ns 65nsMK4503-65 65 ns 80 nsMK4503-80 80 ns 100 nsMK4503-10 100 ns 120 nsMK4503-12 120 ns 140 nsMK4503-15 150 ns 175 nsMK4503-20 200 ns 235 nsPIN NAMESWR= Write= ReadXI = Expansion InXO/HF = Expansion OutHalf Full FlagRS = Reset FF = Full FlagFLIRT = Fi rst Loadl EF = Empty FlagRetransmit Vee = 5 Volts0 = Data In GND = GroundQ = Data Out NC = No ConnectionDESCRIPTIONThe MK4503 is a member of the BiPORT'" MemorySeries, which utilizes special two-port cell techniql1es.Specifically, this device implements a First­In, First-Out algorithm, featuring asynchronous2048 x 9 CMOS BiPORT FIFO,,NDIP-2a:(Plastic Package)PRELIMINARY DATAKPLCC32(Plastic Chip Carrier)FIGURE 1. PIN CONNECTIONSVi0803 302 401 5DO 6Xi 7FF 800 901 1002 1103 1208 13GNO 14S•28 Pin Plastic DIPi!! 1;0 lit >8 11 !l3 2 f32313032 Pin PLCCTop View14 15 1& 17 18 19 2028 Vee27 0426 0525 0624 D723 FL/iii'22 As21 EF20 XCIHi'19 0718 0617 0516 0415 IiJune 19881/16413

MK4503(N,K)-50/65/80110/12115/20readlwrite operations, full, half full and empty flags,and unlimited expansion capability in both word sizeand depth. The main application of the MK4503 isas a rate buffer, sourcing and absorbing data atdifferent rates, (e.g., interfacing fast processors andslow peripherals). The full, half full and empty flagsare provided to prevent data overflow and underflow.The data is loaded and emptied on a First-In,First-Out (FIFO) baSis, and the latency for theretrieval of data is approximately one load cycle(write). Since the writes and reads are internally sequential,thereby requiring no address information,the pinout definition will serve this and future highdensitydevices. The ninth bit is provided to supportcontrol or parity functions.FUNCTIONAL DESCRIPTIONUnlike conventional shift register based FIFOs, theMK4503 employs a memory-based architecturewherein a byte written into the device does not"ripple-through." Instead, a byte written into theMK4503 is stored at a specific location, where it remainsuntil over-written. The byte can be read andre-read as often as desired in the single device configuration.Twin internal pOinters (ring counters) automaticallygenerate the addresses required for each write andread operation. The empty/full flag circuit preventsillogical operations, such as reading un-writtel'l bytes(reading while empty) or over-writing un-read bytes(writing while full) .. Once a byte stored at a givenaddress has been react. it can _be over-written.The addresspointers automatically loop back to addresszero after reaching address 2047. The empty/halffull and full status of the FIFO is thereforea function of the distance between the pOinters, notof their absolute location. As long as the pointersdo not catch one another, the FIFO can be writtenand read continuously without ever becoming fullor empty.Resetting the FIFO simply resets the write and readpointers to location zero. Pulsing retransmit resetsthe read address pointer without affecting the writeaddress pOinter.With conventional FIFOs, implementation of a largerFIFO is accomplished by cascading the individualFIFOs. The penalty of cascading is often unacceptableripple-through delays. The 4503 allows implementationof very large FIFOs with no timingpenalties. The memory-based architecture of theMK4503 allows connecting the read, write, data in,and data out lines of the MK4503s in parallel. Thewrite and read control circuits of the individual FI­FOs are then automatically enabled and disabledthrough the expansion-in and expansion-out pins.FIGURE 2. MK4503 BLOCK DIAGRAMD o· D.wtINPUT I OUTPUT-BUFFERBUFFERWRITE 2048 X 9WRITEREADREAD...CONTROL f- ....... ADDRESS aIPORT'"r- r- ADDRESS >-- CONTROL .-POINTER MEMORY ARRAY POINTERIQ, -Q,FFFLAG LOGICUXIEXPANSION LOGICOfHF X-----------·~I~~-"'I~·.-------,-----IIT2/16414

MK4503(N,K)-50/65/80/10/12/15/20WRITE MODEThe MK4503 initiates a Write Cycle (see Figure 3A)on t~ falling edge of the Write Enable control input(W), provided that the Full Flag (FF) is not asserted.Data set-up and hold-time requirementsmust be satisfied with respect to the rising edge ofW. The data is stored sequentialll!!nd independentof any ongoing .Read operations. FF is asserted duringthe last valid write as the MK4503 becomes full.Write operations begun with FF low are inhibited.FF will go high tRFF after completion of a validREAD operation. FF will again go low tWFF fromthe beginning of a subsequent WRITE operation,provided that a second READ has not been completed(see Figure 4A). Writes beginning tFFW afterFF goes high are valid. Writes beginn.l!!g afterFF goes low and more than tWPI before FF goeshigh are invalid (ignored). Writes beginning lessthan twPI before J!F goes high and less than tFFWlater mayor may not occur (be valid), dependingon internal flag status.FIGURE 3A. WRITE AND FULL FLAG TIMINGLAST VALIDWRITEINVALIDWRITEINDETERMINANTWRITEw \ /'- __ JFULLAC ELECTRICAL CHARACTERISTICS(OOCsTAs +70OC) (Vee = +5.0 volts ± 10%)SYM PARAMETER4503·50 4503·65 4503·80twe Write Cycle Time 65 80 100twpw Write Pulse Width 50 65 80tWR Write Recovery Time 15 15 20tDS Data Set Up Time 30 30 40tDH Data Hold Time 5 10 10MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UIllITS NOTEStWFF W low to FF low 45 60 70tFFWFF High to ValidWrite 10 10 10tRFF R High to FF High 45 60 70tWPIWrite ProtectIndeterminant 35 35 354503·10 4503·12 4503·15 4503·20120 140 175 235 ns100 120 150 200 ns 120 20 25 35 ns40 40 50 65 ns10 10 10 10 ns95 115 145 195 ns 210 10 10 10 ns 295 110 140 190 ns 235 35 35 35 ns 23/16415

MK4S03(N, K)-SO/6S/80/1 0/12/1S/20READ MODEThe MK4503 initiates a Read Cycle (see Figure~)on the falling edge of Read Enable control input (R),provided that the Empty Flag (EF) is not asserted.In the Read mode of operation, the MK4503 providesa fast access to data from 9 of 18432 locationsin the static storage array. The data isaccessed on a FIFO basis inde~ndent of any ongoingWRITE operations. After R goes high, dataoutputs will return to a high impedance conditionuntil the next Read operation.In the event that all data has been read from theFIFO, the EF will go low, and further Read opera-tions will be inhibited ~ data outputs will remainin· high impedance). EF will go high tWEF aftercompletion of a valid Write operation. EFwill again go low tREF from the beginning a subsequentREAD operation, provided that a secondWRITE has not been completed ~e Figure 4B).Reads beginning tEFR after EL goes highare valid. Reads begun after...EF goes lowand more than tRPI before EF goes highare invalid .iliI.nored). Reads beginning less thantRPI before EF goes high and less than tEFR latermayor may not occur (be valid) depending on internalflag status.AC ELECTRICAL CHARACTERISTICS(O°C:s;TA:s; +70°C) (Vee = +5.0 volts ± 10%)SYM PARAMETER4503·50 4503·65 4503·80MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX ~NITS NOTEStRC Read Cycle Time 65 80 100tA Access Time 50 65 80tRR Read Recovery Time 15 15 20tRPW Read Pulse Width 50 65 80tRL R Low to Low Z a a atovData Valid from RHigh 5 5 5tRHZ R High to High Z 25 25 25tREF R Low to EF Low 45 60 75tEfREF High to ValidRead 10 10 10tWEF W High to EF High 45 60 75tRPIRead ProtectIndeterminant 35 35 354503·10 4503·12 4503·15 4503-20120 140 175 235 ns100 120 150 200 ns 220 20 25 35 ns100 120 150 200 ns 1a a a a ns 25 5 5 5 ns 225 35 50 60 ns 295 115 145 195 ns 210 10 10 10 ns 295 110 140 190 ns 235 35 35 35 ns 24/16416

MK4S03(N ,K)-SO/6S/80/1 0/12/1S/20FIGURE 3B. READ AND EMPTY FLAG TIMINGwINVALIDREADINDETERMINANTREAD"\ I'- __ ...IQ.~.------------------------~XXFIGURE 4A. READIWRITE TO FULL FLAG"at""1FIRST READ_____• SINCE FULL .,......:..______________-- I---t,,,,w--~~--FIGURE 4B. WRITE/READ TO EMPTY FLAGw= fiRST tWEFr---___-,. SINCE EMPTY ,..-..:1----------------~/------. t----tEFR" --~.-----5116417

MK4S03(N ,K)oSO/6S/8011011211S/20RESETThe MK4503 is reset (see Figure 5) whenever theReset pin (J!iS') is in the low state. During a Reset,both the internal read and write pointers are set tothe first location. Reset is required after power up,before a Write operation can begin.Although neitheLW or ii need be high when ASgoes low, both Wand R must be high tRSS beforeRS goes high, and must remain hightRSR afterwards. Refer to the foll~ng discussionfor the required state of FURY and XI during Reset.FIGURE 5. RESETw~ . 1 LI 14--1--'----1 INOTERF, EF and FF may change status during Reset,but flags will be valid at tRSC'AC ELECfRICAL CHARACfERISTICS(O"CsTAs +70"C) (Vee = +5.0 volts ± 10%)SYM PARAMETER4503·50 4603·65 4503·80tRSC Resat Cycle Time 65 80 100tRS Raset Pulse Width 50 65 80tRSH Reset Recovary Time 15 15 20tRSS Reset Set Up Time 30 45 604503·10 4503·12 4503·15 4503·20MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES120 140 175 235 ns100 120 150 200 ns 120 20 25 35 ns80 100 130 180 ns6116418

MK4503(N ,K)-50/65/80110112/15/20RETRANSMITThe MK4503 can be made to retransmit (re-readpreviously read data) after the Retransmit pin (RT)is pulsed low. (See Figure 6).A Retransmit operation sets the internal read pointerto the first physical location in the array, but will notaffect the position of the write pOinter. R must beinactive tATS before AT goes high, and must remainhigh for tATA afterwards.The Retransmit function is particularly useful whenblocks of less than 2048 Writes are performed betweenResets. The Retransmit feature is not compatiblewith Depth Expansion.FIGURE 6. RETRANSMIT•IATIRTC.. "IATFLAG VALIDNOTEHF, EF and FF' may change status during Retransmit,but flags will be valid at tATe'AC ELECTRICAL CHARACTERISTICS(O°C:sTA:s +70°C) (Vee = +5.0 volts ± 10%)4503·50 4503·65 4503·80SYM PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTEStRTCtRTtRTRtRTSRetransmit CycleTime 65 80 100Retransmit PulseWidth 50 65 80Retransmit RecoveryTime 15 15 20Retransmit SetupTime 30 45 604503·10 4503-12 4503·15 4503·20120 140 175 235 ns100 120 150 200 ns 120 20 25 35 ns80 100 130 180 ns7116419

MK4503(N, K)-50/65/80/1 0/12115120SINGLE DEVICE CONFIGURATIONWIDTH EXPANSIONA single MK4503 may be used when application requirementsare for 2048 words or less. The MK4503is placed in Single Device Configuration mode wh~the chip is Reset with the Expansion In pin (XI)grounded (see Figure 7).FIGURE 7. A SINGLE 2047 x 9 FIFO CONFIGURATION(f) HALF FULL FLAG- -WRITE (W) (R) READDATA IN \ 4/ / 5FULL FLAG (FF) V 09f\Word width may be increased simply by connectingthe corresponding input control signals of mUltipledevices. Status Flags (EF and FF) can bedetected from anyone device. Figure 8 demonstratesan l8-bit word width by using two MK4503s.Any word width can be attained by adding additionalMK4503s. The half full flag (HF) operates the sameas in the single device configuration.__9f\DATA OUT/3 (EF) EMPTY FLAGRESET (Rs) (AT) RETRANSMITEXPANSION IN (XI) 1rFIGURE 8. A 2048 x 18 FIFO CONFIGURATION (WIDTH EXPANSION)DATA IN(HF) HALF FULL FLAG=--~.- -4--r---------+I (R) READFULL FlAG (FF) 5 - -r-""-(=EF~)--==EM:-:'=:PT==Y=:F""LAG~= __ ~-~ 0 5RESET_-'(.:..:R=-S)'----i~ - _3_ -.(-------+1 0~~----~--~--9EXPANSION IN (Xi)NOTEFlag detection is accomplished by monitoring the FF and EF signals oneither (any) device used in the width expansion configuration. Do not connectflag output signals together.8/16420

MK4S03(N, K)-S0/6S/80110112/1S/20HALF FULL FLAG LOGICWhen in single device configuration, the (HF) outputacts as an indication of a half full memory. Afterhalf of the memory is filled, and at the falling~e of the next write operation, the half full flag(HF) will be set low and remain low until the differ-FIGURE 9. HALF FULL FLAG TIMINGence between the write pointer and read pointer isless than or e~1 to one half the total memory. Thehalf full flag (HF) is then reset by the rising edgeof the read operation. See Figure 9.iiIIHALF-FULL~ 'wtt.HALF-FULL +1-tAHFI\'-HALF-FULLr-AC CHARACTERISTICS(O"C:sT A :s+70"C) (Vee = +5 Volts ±10%)SYM PARAMETERtWHFtRHF4503·50 4503·65 4503·80MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Mill MAX MIN MAX ~IIITS NOTESWrite Low to Half FullFlag Low 65 80 100Raad High to Half FullFlag High 65 80 1004503·10 4503·12 4503·15 4503·20120 140 175 235 ns120 140 175 235 ns9/16421

MK4503(N,K)-50/65/80/10/12/15/20DEPTH EXPANSION (DAISY CHAIN)The MK4503 can easily be adapted to applicationswhen the requirements are for greater than 2048words. Figure 10 demonstrates Depth Expansionusing three MK4503s. Any depth can be attainedby adding additional MK4503s.External logic is needed to generate a compositeFull F~ and Empty Flag. This r~ires the ORingof all EFs and the ORing of all FFs (i.e:...i\1I mustbe set to generate the correct composite FF or EF).FIGURE 10. A 6K x 9 FIFO CONFIGURATION (DEPTH EXPANSION)The MK4503 operates in the Depth Expansion configurationafter the chip is Reset under the belowlisted conditions.1. The first device must be designated by groundingthe First Load pin (FL). The Retransmit function isnot allowed in the Depth Expansion Mode.2. All other devices must have FL in the high state.3. The Expansion Out (XO) pin o~ach device mustbe tied to the Expansion InlXI) pin of the nextdevice. The Half Full Flag (HF) is disabled in thismode.O~AIN ______ ~~ __ ~"".---r-~-+------,/ DATA OUT1-+---._+-+------------ VeeRS10/16422

MK4S03(N ,K)-SO/6S/80110112I1S/20EXPANSION TIMINGFigures 11 and 12 illustrate the timing of the ExpansionOut and Expansion In signals. Discussion ofExpansion OuUExpansion In timing is provided toclarify how Depth Expansion works. Inasmuch asExpansion Out pins are generally connected onlyto Expansion In pins, the user need not be concernedwith actual timing in a normal Depth Expandedapplication unless extreme propagationdelays exist between the XC/Xi pin pairs.FIGURE 11. EXPANSION OUT TIMINGExpansion Out pulses are the image of the WRITEand READ signals that cause them; delayed in timeby tXOL and txOH. The Expansion Out signal ispropagated when the last physical location in thememory array is written and again when it is read(Last Read). This is in contrast to when the Full andEmpty Flags are activated, which is in response towriting and reading a last available location.WRITE 10LAST PHYSICALLOCATIONw\[ __ ~flREAD FROMLAST PHYSICAL\ LOCATION i~ -9 ~!------i1f I..:'----~i- ~""}AC ELECTRICAL CHARACTERISTICS(O"CsTAs +70"C) (Vee = +5.0 volts ± 10%)SYM PARAMETER4503·50 4503·65 4503·80MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTESIXOl Expansion Oul Low 40 55 70IXOH Expansion Oul High 45 60 804503·1075904503·12 4503·15 4503·2090 115 150 ns100 125 155 ns11116423

MK4503(N, K)-50/65/80/1 0/12115/20When in Depth Expansion mode, a given MK4503will begin writing and reading as soon I!L validWRITE and READ signals begin, provided FL wasgrounded at RESET time. A MK4503 in Depth Expansionmode with FL high at RESET will not beginwriting until after an Expansion In pulse occurs.It will not begin reading until a second ExpansionIn pulse occurs and the Empty Flag has gone high.Expansion In pulses must occur t XIS before theWRITE and READ signals they are intended to enable.Minimum Expansion In pulse width, t XI ' andrecovery time, t XIR, must be observed.FIGURE 12. EXPANSION IN TIMINGXiVi'\[IXI~IXIS--\-I-IWRITE TOFIRST PHYSICALLOCATIONIXIA===J'\[.-READ\-IFROMFIRST PHYSICALLOCATION;-AC ELECTRICAL CHARACTERISTICS(O°CsTAs +70°C) (Vce = +5.0 volts ± 10%)SYM PARAMETERtXItXIRtXls4503·50 4503·65 4503·80MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX ~NITS NOTESExpansion In PulseWidth 45 60 75Expansion In RecoveryTime 15 15 20Expansion In SetupTime 20 25 304503·10 4503·12 4503·15 4503·2095 115 145 195 ns 120 20 25 35 ns45 50 60 85 ns12/16424

MK4503(N, K)-50/65/80/10112/15/20COMPOUND EXPANSIONThe two expansion techiques described above canbe applied together in a straight forward mannerto achieve large FIFO arrays (see Figure 13).BIDIRECTIONAL APPLICATIONSApplications, which require data buffering betweentwo sy.stems (each system capable of READ andWRITE operations), can be achieved by pairingMK4503s, as shown in Figure 14. Care must betaken to assure that the ap~opriate flag is monitoredby each ~stem. (Le.J:..F is monitored on thedevice where W is used; EF is monitored on thedevice where R is used.) Both Depth Expansion andWidth Expansion may be used in this mode.FIGURE 13. COMPOUND FIFO EXPANSION00-0800-ON00-OSR.W.RSMK4503-----I~OEPTH EXPANSIONBLOCKMK4503DEPTH EXPANSIONBLOCKOfN-SI-ONMK4503DEPTH EXPANSIONBLOCKDO-ON09-0N01S-0NNOTES1. For depth expansion block see DEPTH EXPANSION Section and Figure 10.2_ For Flag operation see WIDTH EXPANSION Section and Figure 8.FIGURE 14. BIDIRECTIONAL FIFO APPLICATION11w.4FF. 503O.O-Svo.o-SSYSTEM A - - - - - - - - - -R;EF.- - - - SYSTEM B";lO.O-S4 ,5R;° 3E1';;o.o-sw.FF.13116425

MK4503(N ,K)-50/65/80/10/12115/20ABSOWTE MAXIMUM RATINGS·Voltage on any pin relative to GND ....................................... -0.5 V to + 7.0 VOperating Temperature TA (Ambient) ........................................ O°C to + 70°CStorage Temperature ....... ; .......................................... -55°C to + 125°CTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 20 mA'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Thisis a stress rating only, and functional operation of the device at these, or any other conditions above those indicatedin the operational sections of this specification, is not implied. Exposure to absolute maximum ratings for extendedperiods may affect device relia/:lilitv.RECOMMENDED DC OPERATING CONDITIONS(O"C s TA S +70 0 C)SYMPARAMETERMINTYP MAX UNITSNOTESVccSupply Voltage4.55.0 5.5 V3GNDGround00 0 VVIHLogic "1" Voltage All Inputs2.0Vcc + .3V3,9VILLogic "0" Voltage All Inputs-0.30.8 V3,4,9DC ELECTRICAL CHARACTERISTICS(O°CsTAs+70"C) Ncc = 5.0 volts ± 10%)SYMPARAMETERMIN MAX UNITSNOTESIlLInput Leakage Current (Any Input)-1 1 pA5IOLOutput Leakage Current-10 10 pA6VOHOutput Logic "1" Voltage lOUT = -1 mA2.4 V3VOLOutput Logic "0" Voltage lOUT = 4 mA0.4 V3Icc1Average Vcc Power Supply Current120 mA7Icc2ICC3Average Standby Current(R = W = RS = FURT = VI H)Power Down Current(All Inputs 0: Vcc -0.2 V)12 mA4 mA77AC ELECTRICAL CHARACTERISTICS(O"CsTAs+70"C) (Vcc = +5.0 volts ± 10%)SYMPARAMETERTYPMAXNOTESCICapaCitance on Input Pins7 pFCQCapaCitance on Output Pins12 pF8NOTES1. Pulse widths less than minimum values are not allowed. 5. Measured with O.OsVINsVCC.2. Measured using output load shown in Output Load 6. F'i2:VIH, O.O~VOUTsVCC.Diagram.7. ICC measurements are made with outputs open.3. All voltages are referenced to ground.8. With output buffer deselected.4. -1.5 volt undershoots are allowed for 10 ns once per 9. Input levels tested at 500 ns cycle time.cycle.14/16426

MK4S03(N, K)-SO/6S/80/1 0/1211 S/20FIGURE 15. OUTPUT LOAD+5VDEVICEUNDERTEST680 II:::1'1.1 KG30 pFAC TEST CONDITIONS:Input Levels ............................................ GND to 3.0 VTransition Times ................................................... 5 nsInput Signal Timing Reference Level ................... 1.5 VOutput Signal Timing Reference Level 0.8 V and 2.2 VAmbient Temperature ................................ O"C to 7O"CVee ........................................................ 5.0 V ± 10%- .....FIGURE 16. MK4503 PLASTIC (N TYPE) DUAL-IN-LlNE, 28 PINSr'i r'i r'i r'i r'i r'i r'iJ'"l '"' '"' '"' '"' '"' '"'Dim.mmInchesMin Ma. Min Ma.NotesA - 5.334 - 210 20 A1 0.381 - .015 - 2A2 3.556 4.064 .140 .160(6 0.381 0.534 .015 .021 361 1.27 1.778 .050 .070C 0.203 0.304 .008 .012 30 36.576 37.338 1.440 1.470 1I V V V V V V V oV V V V V V-'f.:~ 01 1.651 2.159 .065 .085E 15.24 15.875 .600 .62501~f=1Ai -1-II-NOTES1. OVERALL LENGTH INCLUDES .010 IN.FLASH ON EITHER END OF THE PACKAGE.2. PACKAGE STANDOFF TO BE MEASUREDPER JEDEC REQUIREMENTS.3. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. WHENSOLDER LEAO FINISH IS SPEC IF lEO .I .. ---1E1 13.462 14.224 .530 .5602.286 2.794 .090 .110oA 15.24 17.78 .600 .700L 3.048 - .120 -15/16427

MK4503(N,K)-50/65/80110/12115/20FIGURE 17. MK4503 PLASTIC LEADED CHIP CARRIER, 32 PIN (K TYPE)o01~2 PLCS~ t· DENOTES PIN 1.023.02911--. 0• 0I NOMDim.mmInchesMin Max Min MaxA 3.048 3.556 .120 .140A1 1.981 2.413 .078 .095B 0.330 0.533 .013 .021EIB1 0.660. 0.812 .026 .0320 12.319 12.573 .485 .49501 11.353 11.506 .447 .45302 9.906 10.922 .390 .430E 14.859 15.113 .585 .595E1 13.893 14.048 .547 .553E2 12.446 13.482 .490 .530ORDERING INFORMATIONPART NO.ACCESS TIMERJW CYCLETIMECLOCK FREQ.PACKAGE TYPETEMPERATURERANGEMK4503N-5050 ns65 ns15.3 MHz28 Pin Plastic DIP O· to 700CMK4503N-6565 nsSO ns12.5 MHz28 Pin Plastic DIP o· to 700CMK4503N-8080 ns100 ns10.0 MHz28 Pin Plastic DIP O· to 700CMK4503N-10100 ns120 ns8.3 MHz28 Pin Plastic DIP O· to 700CMK4503N-12120 ns140 ns7.1 MHz28 Pin Plastic DIP O· to 700CMK4503N-15150 ns175 ns5.7 MHz28 Pin Plastic DIP O· to 700CMK4503N-20200 ns235 ns4.2 MHz28 Pin Plastic DIP O· to 7O·CMK4503K-5050 ns65 ns15.3 MHz32 Pin PLCC O· to 700CMK4503K-6565 ns80 ns12.5 MHz32 Pin PLCC O· to 700CMK4503K-SO80 ns100 ns10.0 MHz32 Pin PLCC O· to 700CMK4503K-10100 ns120 ns8.3 MHz32 Pin PLCC O· to 700CMK4503K-12120 ns140 ns7.1 MHz32 Pin PLCC O·to 700CMK4503K-15150 ns175 ns5.7 MHz32 Pin PLCC O· to 700CMK4503K-20200 ns235 ns4.2 MHz32 Pin PLCC O· to 700C16116428

MK4511(N,K)-12/15/20512 x 8 CMOS BiPORl'M RAM• SINGLE CHIP BI-DIRECTIONAL MESSAGEPASSING• SOFTWARE CONTROLLED INTERRUPTOUTPUTS• ADDRESSABLE STATUS/CONTROL FLAGS• IDENTICAL PORTS, 3-WIRE CONTROLLED I/OPIN NAMESAD - Address/Data I/OCE - Chip EnableDE - Output EnableINT - Interrupt OutputGND- GroundVee - +5 VoltsWE- Write Enable NC - No ConnectionPart Number ~cess Time Cycle Time Cycle RateMK4511-12 120 ns 150 ns 6.67 MHzMK4511-15 150 ns 190 ns 5.26 MHzMK4511-20 200 ns 250 ns 4.00 MHzDESCRIPTION~p, ~,NDIP-28(Plastic Dip)AD", 1ADxs 2AD .. 3ADX7 4ADx, 5We,. 6~ 7CEy 8WEy 9ADy, 10ADY7 11ADyS 12ADyS 13GND 14KPLCC32(PlastiC Chip Carrier)28 vee27 AD ..26 ADx225 ADx•24 ADxo23 OEx22 INTx21 INTy20 OEy19 ADy.18 ADY117 ADY216 ADY315 ADy,The MK4511 dual port RAM contains a single 512x 9 CMOS memory matrix that can be accessedsimultaneously from both of the input/output ports.Dual port operation is achieved through the use ofa memory array composed of BiPORT memorycells. Each memory cell is accessible from bothports at all times.Pin count is kept low through the use of address/datamultiplexing. This technique is beingused on advanced microprocessors and otherdevices to keep pin counts and package sizes down.The MK4511 incorporates all functions required fordual port operations, including software controlledinterrupt outputs. Use of the interrupt outputs is optional,allowing both polled and interrupt controlledapplications.4 3 2 ~ 32 31 3032 Pin PLeeTop View14 15 16 17 18 19 20June 19881111429

MK4511(N,K)-12/15/20SINGLE PORT OPERATIONSThe MK4511 may be viewed from either port as anordinary three wire controlled 512 x 9 static RAM.Timing of read and write ooerations is altogetherconventional; the presence of the other port is effectivelytransparent to the accessing processor.Therefore. all timing parameters are specifiedwithout references that differentiate between theports.FIGURE 2. MK4511 BLOCK DIAGRAMCE xWE xX PORTCONTROLLOGICOE x36X INTERRUPTCONTROLREGISTER128INTxINT..,512 X 9BiPORTMEMORYARRAY128Y INTERRUPTCONTROLREGISTER36eEyWE yYPORTCONTROLLOGICOEy2111430

MK4511(N,K)-12115/20READ MODEThe MK4511 is in Read Mode whenever Chip Enable(~) is low and Write Enable (WE) is high. Astable address must be placed onto the AD linestAS prior to Chip Enable becoming active. The addressmust be held valid for tAH following the failingedge of ~.In Read Mode the bi-directional AD lines are drivenalternately by the user and the MK4511. Bus con-tention will occur if the user's address driver remainsactive too long. An Output Enable input (OE)is provided, offeri!!9... an improved ability to avoid buscontention. The OE control keeps the AD lines ina high impedance state while held high and fortoEL after it goes low. Output data will be valid atthe latter of toEA or tCEA' A Chip Enable recoverytime (leER) must be observed between assertionsof~.FIGURE 3. READ-READ-READ MODIFY WRITE.. AD READREAD MODIFV WAITEADREAD CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O°CsTAs70OC) (Vcc = 5.0 V ± 10 percent)MK4511-12 MK4511-15 MK4511-20SYM PARAMETERS MIN MAX MIN MAX MIN MAX UNITS NOTEStRC Read Cycle Time 150 190 250 nstAS Address Setup Time 0 0 0 nstAH Address Hold Time 20 25 35 nsleEA Chip Enable Access Time 120 150 200 ns 1toEL Output Enable to Lo-Z 15 15 15 nstoEA Output Enable Access Time 55 70 90 ns 1tOH Valid Data Out Hold Time 5 5 5 ns 1tCEZ Chip Enable Hi to Hi-Z . 90 110 150 nstOEZ Output Enable Hi to Hi-Z 40 50 65 nstWEZ Write Enable Lo to Hi-Z 40 50 65 nstCER Chip Enable Recovery Time 30 40 50 ns3111431

MK4511(N,K)-12115/20WRITE MODEThe MK4511 is in Write. Mode whenever Write Enable(WE) and Chip Enable (CE) are active low. Asin Read Mode, the falling edge of CElatches theaddresses present at the AD lines. The same addressesset-up and hold times apply. Input to theAD pins must then change from the address to inputdata. Input data present on the AD lines mustbe stable for tosprior to the end of write and mustremain valid for tOH afterward. A writ~le may beended by the riSing edge of WE or CEo Chip Enablerecovery time must also be observed in writemode.Even if WE becomes active prior to CE becomingactive, CE falling actually begins the cycle, latchingthe address present on the AD lines. Such cyclesmust reference t~, tos and 10H to the riSingand falling. edges of CE and WE.Read-Modify-Write cycles are possible if the outputsare enabled and the assertion of WE is dela~through tea: The write cyQle will begin when WEgoes low. WE going low or OE going high will retumthe output drivers to high-Z within tWEz..2! toEZrespectively. The address latched when CE wentlow is still the valid address as the write cycle proceeds.Th!.9'Cle is ended by the earlier rising edgeofCE or WE.FIGURE 4. WRITE-WRITE-READ MODIFY WRITEWRITEWRITEREAD MODIFY WRITEADI ..I~ ft=-I~~WRITE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O°CsT As70"C) (Vee = 5.0 V ± 10 percent)MK4511-12 MK4511-15 MK4511-20SYM PARAMETERS MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 150 190 250 nsteEW Chip Enable to End of Write 120 150 200 nstWEW Write Enable to End of Write 80 105 130 nstos Data Setup. Time 40 55 65 nstOH Data Hold Time 10 10 10 ns4111432

MK4511(N,K)-12115/20DUAL PORT OPERATIONSnot affect the status of the Port X Interrupt Register.INTERRUPT CONTROLThe lower three bits of each byte written to the topand bottom addresses are the ones routed simul­Although the Interrupt Control Registers for each taneo"usly to the Interrupt Control Registers. The Inportare accessed in parallel with RAM locations terrupt Control Registers consists of three flip-flopsOOOH and 1FFH, they do not reside within the RAM per port that serve as the Interrupt Request/Cancelarray. They do not derive their control Inputs from flag (REQlCAN), Interrupt Output Enable/Disablethe RAM cells' Status. In fact, changing the RAM flag (ENAIDiS) and Interrupt Acknowledge/Readylocation's contents via an opposite port will not af- flag (ACKlRDY). As Figure 5 shows, the logic atfecta Interrupt Control Register at all. Therefore, tached to the Interrupt Control Registers interpretsfor example, Port Y writing to address OOOH can- interrupt status and drives the Interrupt Outputs.FIGURE 5. MK4511 INTERRUPT CONTROL REGISTERS AND INTERRUPT LOGICINTx~~-------------'INTyENAJDISENAIDISADx,--__ .I 0QQ 0 ADy,CKCKREQ/CAN0 QADyoCKCOWMNOxROW 127yCOWMN 3yINTERRUPT BYTE STRUCTUREBecause only the lower 3 bits of each interrupt byteare used to control the interrupt logic, the six MSBswritten to the RAM have no affect on the state ofthe interrupt outputs,and may be used for any otherpurpose. The functions of the three control bits are:Inter~ Output Enable/DlsableENAlmlx (AOx,) and ENAlDiSy (ADy1)Each port can disable its own interrupt o..!ill1.uts bywriting a 0 (XXXXXXXOX 2) into its ENAIDIS bit. Ifdisabled, the interrupt pin will remain high regardlessof interrupt requests from the other port. If aninterrupt is requested of a disabl~rt, and an enabling1 is later written into ENAIDIS of the disabledport, the interrupt output will go low tWIL following therising edge of the enabling write. Disabling a port withan active interrupt output pin will result in the outputgoing high twlH after the end of the disabling write.5111433

MK4511(N,K)-12115/20Interr~Reque8t1cancel __REQ/CANx {ADxol and REQ/CANy (ADyo)Assuming that the Enable and Ready flags are set,writing a1 into a REO/CAN bit drives an enabledinterrupt output pin on the opposite port low. Theinterrupt line will be driven low tWIL foliOWinactheend of the write that places a 1 in the REal ANbit. For example, when XXXXXXXXhls written intolocation OOOH setting REQ/~x, INT y will go activelow within tWIL' Writing a 0 into the REO/CANbit cancels the interrupt request, returning the INToutput to a high state tWIH after the end ofwrite.FIGURE 6. INTERRUPT REOUEST TIMINGIIEAliVDATAInterrupt Acknowledge/Rea~ACKIRDY x (AD X2) and ACKIRDY y (ADY2) :Once an interrupt has been received at a port, theinterrupt can be turned off by' writing a1(XXXXXX1XX~ into the ACKIRDY bit of the receiv­Ing port. Writing an acknowledge will cause the interruptoutput to go high tWIH ·after the end of thewrite. The interrupt request flag cannot be set whilethe acknowledge flag is active. Ali acknowledgemust always be followed with a ready (writing a 0over the 1) before requests from the other'port canbe recognized. Interrupt requests can be recognizedtRRR after a ready. ' .ACKNOWLEDGEDATAj~j -"""'\'-__....J/ENABLE AND/ORREQUEST DATA~AND/oRIlliAI!![ DATAINTERRUPT OUTPUT TIMINGAC ELECTRICAL CHARACTERISTICS(OOC:sT A :s70OC) (Vcc = 5.0 V ± 10 percent)MK4511-12 MK4511-15 MK4511-20SYM PARAMETERS MIN MAX MIN MAX MIN MAX UNITS NOTEStWIL End of Write toTliiT Low , 50 60 85 nstWIH End of Write to TIiiT High 50 60 85 nstRRR Ready to Request Recognized 10 10 15. hs6111434

MK4511 (N,K)-12115/20IMPLEMENTATIONUse of the interrupt feature is completely optional,allowing simple implementation of either interruptdriven or polled inter-processor communications applications.Either port can read or write any of the512 bytes without restriction. Users who choose notto utilize the interrupt feature should leave the interruptpins unconnected.Any inter-processor communications application willdoubtless employ sorge ~pe of sem~hore scheme.The use of the REOI A ,ENNDiS and ACKIRDYbits allow for each port to follow the exact statusof the other port. The following example covers thecase of port X interrupting port Y but applies equallywell for port Y interrupting port X.An Example Approach to Inter-processor CommunicationsUsing Pre-Allocated Memory Blocksand InterruptsPre-define six memory blocks of 85 bytes each (fora total of 510 bytes). Assign some number of blocks(probably three) to the X port and the balance tothe Y port. Each port will write only to its assignedmemory blocks, preventing port X and port Y attemptingto load their messages into the same area.Write the message to be passed into the Port X messagearea. When finished, read ACKlRDYy . Ifready, request an interrupt on port Y by writing a1 into REO/CANx. Indicate which messageblock(s) contain valid message data, using the uppersix bits of the interrupt register byte.Now, acknowledge the interrupt to Port Y by writinga 1 to the acknowledge flag on Port Y. Beginreading the message via Port Y. The acknowledgeshould not be removed until after the message Basbeen read. When it has been, set the ACKIR ¥yflag to ready.ports attempting to write at the same address or oneport reading and one writing at the same addressat the same time.While a collision is generally considered undesirable,the conditions that can lead to iII-defined resultsare definable and manageable. In the case of awritelwrite collision, the data stored at the addressin question mayor may not have any similarity toeither write attempted or the previously residentdata if the delay between the ends of the writes(twwJis not long enough. On the other hand,write/read collisions do not affect the integrity of datastorage, but do have an impact on the validity ofoutput data at definable pOints in time (1001 andIoov). Figures 7 and 8 describe these conditions.All of the parameters indicated reference the validityof the entire byte of data. Individual bits of a bytechange state at slightly different rates. Though thisis a subtle distinction, it is nonetheless important,particularly in the case of monitoring ACKIRDY. Beaware that a read may catch the ready bit at a validzero before the rest of the byte has finished transition.Nevertheless, because there is no reason forthe ready bit to go low, other than that the oppositeport is writing a zero into it, catching it low isa reliable indication that the other port is ready. Thisis all to say that single significant bit flag write/readoperations can proceed reliably under collision conditionswhere byte wide operations cannot.Simultaneous reads at the same address will alwaysproduce valid data and are therefore not considereda collision in this context.FIGURE 7. MINIMUM WRITE TO WRITE LATENCYFOR VALID DATA STORAGE"".Check to see that the message was received. MonitorACKlRDYy via Port X. Changes to the messageblock should not be made by Port X untilACKlRDYy is zero, indicating Port Y has finishedreading its message.COLLISIONThe central objective of the MK4511 design effortwas to produce a component that makes implementationof asynchronous, random access dual portmemory applications, that can assure data integrity,as simple and inexpensive to design and implementas possible.Data Integrity can be called into question if port toport collision occurs. A collision is defined as both\ /7111435

MK4511(N,K)-12115/20FIGURE 8. SIMULTANEOUS READ WRITE TIMINGCE x\/WEx1ADxIODYADyVALID DATA OUTNEW VALID DATA OUTOEy'"IICEA~10EZtCEZIbCEyCOLLISION TIMINGAC ELECTRICAL CHARACTERISTICS(O°C:sT A:s70°C) (Vee = 5.0 V ± 10 percent)MK4511-12MK4511-15MK4511-20SYM PARAMETERS MIN MAXtoOl Output Data Indeterminant 10tODV Output Data Valid 90tWWL Write to Write Latency 80MIN MAX MIN MAX UNITS NOTES10 10 ns115 150 ns105 130 ns8/11436

MK4511(N,K)-12/15/20ABSOWTE MAXIMUM RATINGS·Voltage on any pin relative to GND ....................................... -0.3 V to +7.0 VAmbient Operating Temperature (TAl ......................................... O°C to +70°CAmbient Storage Temperature ........................................... -55°C to +125°CTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 20 mA• Stresses greater than those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or other conditions beyond those indicatedIn the operational section of this specification is not implied. Exposure to absolute maximum rating conditions forextended periods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(0 OC sT AS 70 OC)SYMPARAMETERSMINTYPMAX UNITS NOTESVccSupply Voltage4.55.05.5 V 2GNDSupply Voltage000 VVIHLogic 1 VOltage, All Inputs2.2Vcc + 0.3 V 2,3VILLogic 0 Voltage, All Inputs-0.30.8 V 2,3DC ELECTRICAL CHARACTERISTICS(OOCsTAs70OC) (Vcc = 5.0 V ± 10 percent)SYMIcc1ICC2Icc3IlLIOLVOHVOLPARAMETERSAverage Power Supply Current per PortTTL Standby Current per PortCMOS Standby Current per PortInput Leakage CurrentOutput Leakage Current (Any Output Pin)Output Logic 1 Voltage (lOUT = -1 mAlOutput LogiC 0 Voltage (lOUT = 2.1 mAlMIN-1-52.4MAX UNITS NOTES25 mA 42.5 mA 51 mA 6+1 pA- 7+5 pA- 7V 20.4 V 2CAPACITANCE(TA = 25OC, f = 1.0 MHz)SYMCICoPARAMETERSCapacitance on any Input PinCapacitance on any Output PinNOTES1. Measured with load shown in Figure 9.2. All voltages referenced to GNO.3: No more than one negative undershoot or positive overshoot of 1.5 V witha maximum pulse width of 10 ns is allowed once per cycle.4. Output buffer is deselected, both ports are active.5. All inputs = VIH.6. All inputs ""Vee - 0.2V7. Measured with GNOsVI';;Vee and outputs deselected.8. Effective capacitance is calculated as follOWS: e = .1Q.1V=3V .1V9. Output buffer is deselected.TYP UNITS NOTES4 pF 810 pF 8,99111437

MK4511(N,K)-12/15/20AC TEST CONDITIONSInput Levels ................ , ............................................ GND to 3.0 VTransition Times ................................................................. 5 nsInput Signal Timing Reference Level ................................................ 1.5 VOutput Signal Timing Reference Levels ..................................... 0.8 V and 2.2 VAmbient Temperature ....................................................... O"C to 7O"CVee ............................................................... 5.0 V ± 10 percentFIGURE 9. EQUIVALENT OUTPUT LOAD CIRCUIT+5.0 V1.8KDDEVICEUNDERTESTlKD+oo~.-=-GND• INCLUDES SCOPE AND TEST JIG.FIGURE 10. MK4511 PLASTIC LEADED CHIP CARRIER, 32 PIN (K TYPE)D01~2 PLes~ t DENOTES PIN 1.023.029 11--. 050I NOMmmDim.Min MaxA 3.048 3.556A1 1.981 2.4136 0.330 0.53361 0.660 0.812D 12.319 12.573D1 11.353 11.506D2 9.906 10.922E 14.859 15.113E1 13.893 14.046E2 12.446 13.462inchesMin Max.120 .140.078 .095.013 .021.026 .032.485 .495.447 .453.390 .430.585 .595.547 .553:490 .53010/11438

MK4511(N,K)-12115/20FIGURE 11. MK4511 28 PIN PLASTIC DIP (N TYPE)Dim.mmMin Max MinA - 5.334 -AI 0.381 - .015A2 3.556 4.064 .1408 0.381 0.533 .01581 1.27 1.778 .050C 0.203 0.304 .008D 36.576 37.338 1.440Dl 1.651 2.159 .065E 15.24 15.875 .600El 13.462 14.224 .530el 2.286 2.794 .090eA 15.24 17.78 .600L 3.048 - .120inchesMax210-.160.021.070.0121.470.085.625.560.110.700-Notes22331~1. OVERALL LENGTH INCLUDES .010 IN.FLASH ON EITHER END OF THE PACKAGE.2. PACKAGE STAN~OFF TO BE MEASUREDPEA JEOEC REQUIREMENTS.3. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. WHENSOLDER LEAD FINISH IS SPECIFIED.ORDERING INFORMATIONMK4511 x -xxRoar PART PACKAGE SPEED TEMP RANGENUMBER-12 120 NS ACCESS TIME-15 150 NS ACCESS TIME-20 200 NS ACCESS TIMENK28 PIN DIP32 PIN PLCC11/11439

MK4505M/4505S{N)·25/33/50VERY HIGH-SPEED CMOS CLOCKED FIFOPRELIMINARY DATA.1024 x 5 ORGANIZATION• VERY HIGH PERFORMANCEPart No. Cycle Time Cycle AccessFrequency Time4505-25 25 ns 40 MHz 15 ns4505-33 33 ns 30 MHz 20 ns4505-50 50 ns 20 MHz 25 ns• RISING EDGE TRIGGERED CLOCK INPUTS• SUPPORTS FREE-RUNNING 40% TO 60%DUTY CYCLE CLOCK INPUTS• SEPARATE READ AND WRITE ENABLEINPUTS• BiPORT'" RAM ARCHITECTURE ALLOWS FUL­LY ASYNCHRONOUS AND SIMULTANEOUSREADIWRITE OPERATION• CASCADABLE TO ANY DEPTH WITH NO AD­DITIONAL LOGIC• WIDTH EXPANDABLE TO MORE THAN 40 BITSWITH NO ADDITIONAL LOGIC• HALF FULL STATUS FLAG• FULL AND EMPTY FLAGS, ALMOST FULL,ALMOST EMPTY, INPUT READY, OUTPUTVALID STATUS FLAGS (4505M)~ (~'I:'20' . . . I" .'! I' ' '.1 'NDlp·20(Plastic Package)NDIP-24(Plastic Package)FIGURE 1. PIN CONFIGURATION2. V" 20 V"D, 2 23 CKw D, 2 19D, 3 22 WE, D, 3 18D,•21 FF D,•17D, 5 20 DR D, 5 MK4505S 1.AE• MK4505M 1. HF As •15As 7 18 AF RE, 7 14av 8 17 a, RE, 8 13EF •1. a, CK,•12RE, 1. 15 a, v"eK, 11 1. a,12 13 a,v"10 11CKwWE,WE,HFa,a,a,a,a,• FULLY TTL COMPATIBLE• 300 MIL PLASTIC DIPPIN NAMESDo - D40 0 - 0 4CKw, CK RWE,RE,ASHFSupersedes publication for January 1988.June 1988. Data Input- Data Output- Write and Read Clock- Write Enable Input 1- Read Enable Input 1- Reset (Active Low)- Half Full Flag- +5 Volt, Ground(4505M Only)FF, EFAF, AEDR,OV(4505S Only)- Full and Empty Flag (Active Low)- Almost Full, Almost Empty Flag- Input Ready, Output ValidWE2 - Write Enable Input 2RE2 - Read Enable Input 2 (Rising EdgeTriggered 3 State Control)1/16441

M K4505M/4505S(N)-25/33/50DESCRIPTIONThe MK4505 is a Very High Speed 1K x 5 ClockedFIFO memory. It achieves its high performancethrough the use of a pipelined architecture, a 1.21'full CMOS, single poly, double level metal process,and a memory array constructed using SGS­THOMSON's 8 transistor BiPORT memory cell.The device is designed for use in applications wheredata is moving through a system on a square waveclock; applications such as digitized video and audio,image processing, A-to-D and D-to-A conversions,high speed data links, Radar return samplingor data tracing.FIGURE 2. BLOCK DIAGRAM MK4505M/4505SThe device is available in two versions; a Master,the MK4505M, and a Slave, the MK4505S. TheMaster provides all of the control signals necessaryfor reliable, full speed, fully asynchronous width expansionand/or depth expansion. The Master alsoprovides a full compliment of status flags, includingOutput Valid, Empty, Almost Empty, Half Full,Almost Full, Full, and Input Ready. The Master cannotbe written while Full or read while Empty. TheSlave, in contrast, can be forced to write and/or readcontinuously regardless of device status; a featureuseful in triggered data acquisitions, or for retransmit(repeat reading) applications.r-----------------~~------~~aHF-----------~~--------~--------~ FF,EF ~--------~--------~~------FLAG LOGIC~----------------_;--------~ff .-------------- --------~ 1-------- --------------....I 4505M IDR ..-------------- ---------1 FLAG 1"-----:---- ---------------..QyI LOGIC IAF .-------------- --- -----'1 1-------- --------------_AEL _____ ...J2/16442

MK4505M/4505S(N)-25/33/504505M (MASTER) WRITE TRUTH TABLEPRESENT STATE NEXT NEXT STATEClew OPERATIONRS WEI FF DRFF DR 0X 0 X X X Resel 1 1 Don'l Caret 1 0 0 D No·Dp ? ? Don'I Caret 1 0 1 1 No·Op 1 1 Don'l CareT 1 1 D 0 No·Op ? ? Don'l Caret 1 1 1 1 Wrile ? ? Dala In? = The "Nell Slale" logic level is unknown due to the possible oc·currence of a read operation.4505M (MASTER) READ TRUTH TABLEPRESENT STATE NEXT NEXT STATECKR RSOPERATIONREt EF DYEF DY DX 0 X X X Reset D 0 Hi ZT 1 D 0 0 Inhibit ? 0 Hi Zt 1 D D 1 Inhibit ? 0 HiZt 1 0 1 0 Hold 1 1 Previous nt 1 0 1 1 Hold 1 1 Previous nt 1 1 0 0 Inhibit ? 0 Hi Zt 1 1 0 1 Inhibit ? 0 HiZt 1 1 1 0 Read ? 1 Data Dutt 1 1 1 1 Read ? 1 Data Out? = The "Nelt State" logic level is unknown due to the possible oc·currence of a write operation4505S (SLAVE) WRITE TRUTH TABLEPRESENT STATE NEXT NEXT STATECKw RS WEt WE2 OPERATION 0X D X X Reset Don't Caret 1 D 0 No·Op Don't Caret 1 0 1 No·Dp Don't Caret 1 1 0 No·Op Don't Caret 1 1 1 Write Data In4505S (SLAVE) READ TRUTH TABLEPRESENT STATE IEXT NEXT STATECKR OPERATIONRS REI RE2DX 0 X X Reset Hi Zt 1 D 0 Inhibit Hi Zt 1 D 1 Hold Previous nt 1 1 0 Inhibit HiZt 1 1 1 Read Data DutX = Don't careWRITE OPERATIONSThe device will perform a Write on the next risingedge of the Write Clock (CKw) whenever (seefigure 3):- (45058) WEI and WE2 are high at the risingedge of the clock. _- (4505M) WEI and FF are high at the risingedge of the clock.Because the device only re-evaluates and updatesthe Full Flag (FF) on the rising edge of CKw, theappearance of an active Full Flag at valid flag accesstime, t!=lA' assures the user that the next risingedge of CKw will generate a NO-OP condition.READ AND HOLD OPERATIONSThe device will perform a Read on the next risingedge of the Read Clock (CKR) whenever (seefigure 4):- (45058) REI and RE2 are high at the risingedge of the clock._- (4505M) REI and EF are high at the riSingedge of the clock.Because the device only re-evaluates and updatesthe Empty Flag (EF) on the rising edge of CKR, theappearance of an active Empty Flag at valid flagaccess time, tf'1A' assures the user that the nextrising edge of CKR will generate an Inhibit condition.All Q outputs will be High Z at toz from therising edge of CKR.The device will perform a Hold Cycle (hold overprevious data) if REI is low at the rising edge of theclock (CKR). If EF (4505M) or RE2 (45058) is lowat the rising edge of the clock, then the outputs willgo to High-Z.RESETAS is an asynchronous master reset input. A Resetis required after power-up, before first write. Resetcommences on the falling edge of AS irrespectiveof the state of any other input or output. The useris required to observe Reset 8et Up Time (tess)only if the device is enabled (see Figure 6). ThetR~ specification is a don't care if the device remainsdisabled (WEI = REI = LOW). All statusflaliutputs will be valid tRSA from the falling edgeof RS, and all Q data outputs will be high impedancetRSaz from the same falling edge.After Reset, if no valid Read operations have beenperformed since Reset, the "previous data" that willbe output when executing the first Hold cycle willbe all zeros (see Figure 7.)3116443

MK4505M/4505S(N)-25/33/50AC ELECTRICAL CHARACTERISTICS(TA = 0° to 70"C, Vcc = 5.0 ± 10%)SYMPARAMETER4505-25 4505-334505-50 UNITS NOTEMIN MAX MIN MAXMINMAXtCKClock Cycle Time25 3350 ns 1tCKHClock High Time10 1320 ns 1tCKlClock Low Time10 1320 ns 1tsSet Up Time10 1316 ns 1tHHold Time0 00 nstAOutput (a) Access Time15 2025 ns 1,2tF1AtF2AtOHtoztOltRSStRSFlag 1 Access Time(7)Flag 2 Access Time(8)Output Hold TimeClock to Outputs High-ZClock to Outputs Low-ZReset Set Up TimeReset Pulse Width15 2020 255 515 205 512 1625 3325 ns 1,230 ns 1,25 ns 1,225 ns 1,35 ns 1,325 ns 1,450 nstRSAReset Flag Access Time50 66100 ns 1,3tRSOZReset to Outputs High-Z25 3350 ns 1,3tFRlFirst Read Latency50 66100 ns 1,5tFFlFirst Flag Cycle Latency25 3350 ns 1,61. All AC Electrical Characteristics measured under conditions specifiedin ''AC Test Conditions".2. Measured w/40pf Output Load (Figure 15A).3. Measured w/5pf Output Load (Figure 158).4. Need not be met unless device is Read andlor Write Enabled.5. Minimum first Write to first Read delay required to assure valid first Read.6. Minimum first Write to first Read Clock delay required to assure clearingthe Empty Flag.7. Flag 1 = EF, FF, av, DR.8. Flag 2 = AE, AF, HF.4/16444

MK4505M/4505S(N)-25/33/50IGURE 3. WRITE CYCLE TIMINGI, ~ ..HarEFor this particular diagram. the FF changes logic states presuming that avalid READ operation has occurrad prior to the rising edge of CKW attl'FIGURE 4. READ CYCLE TIMINGCK,, __HareFor this particular diagram. the EF changas logic states presuming that avalid WRITE operation has occurred prior to the rising edge of CKR at t2'------------------ ~I~~III ________________ ~5~n6445

MK4505M/4505S(N)-25/33/50FIGURE S. HOLD CYCLE TIMINGREAD HOLD READ READ-~-'CK'CK-~-Q DATA DATA x::x==RE,FIGURE 6. RESET CYCLE TIMING (4S0SM/SNOTE: 'RSS MUST BE MET IF THE DEVICE. IS READ AND/OR WRITE ENABLED (WE,_ RE, = HIGH).::..611:..::,.6 ________ ~.~m?~SJI ---------446

MK4505M/4505S(N)-25/33/50FIGURE 7. FIRST HOLD AFTER RESETRESETI, I,INHIBIT~ INHIB~TFIRST HO~DAFTER RESETREADtAC tAC tAC -----..Q ~rRE,.. ~--....;I:.....-t_lsJ ____....!....-___ -J r--_I. __ ~_"LI_DDA_rA_OuTEF (4505M)ORRE, (4505S)-J ~u...u.;L_. __NOTE: A VALID WRITE OPERATION IS PRESUMED BETWEEN II and 12.FIGURE 8. ALMOST EMPTY FLAG TIMING (4505M)READHOLDHOLDQLAST READ BEFOREAERE,AEWE, _____________ ~~LUD~ ___ J>____

M K4505M/4505S(N)-25/33/50FIGURE 9. ALMOST FULL, HALF FULL FLAG TIMING (4505M/S)----«LAST WRITEBEFORE HF OR AFVALID >-------l(_-"VALID ~DATA IN~::~ IAF, HF"', ,~.".J-,---tsRE 2(SLA:-.-E)--------------II ~a(1}IFIRST READ SINCEHFORAFHOLD PREVIOUS at. Q outputs in Master/Slave Width Expansion (RE2 = EF), or when usingMK4505S Slave separately._2. Q outputs in Master-to-Master Depth Expansion (REt with EF = HIGH),or when using the MK4505M separately.FIRST READ SINCE!iF OR AFFlag Interpretation KeyVALID WRITECURRENTCYCLESFLAG STATE REMAININGMIN MAXAE1 1016 10240 0 1015HF1 0 5120 513 1024AF1 0 80 9 1024VALID READCYCLESREMAININGMINMAX0 89 1024512 10240 5111016 10240 1015NOTEThe table describes the number of valid cycles that can be performed, includingthe next rising edge of the clock. ---8116448

MK4505M/4505S(N)-25/33/50FIGURE 10. SIMULTANEOUS WRITE/READ TIMING (4505M)WE, ~-=:.j .. 1--oCK"RE,________ _QVQFIGURE 11. SIMULTANEOUS WRITE/READ TIMING (4505S)WE,. WE,o~.---!--.'s _~_RE 1 .AE 2 -----------~Q_ ________________________ ~.~~ --- --- ---r.------~9/16449

MK4505M/4505S(N)-25/33/50SIMULTANEOUS WRITE/READ TIMINGThe Empty Flag (EF) is guaranteed to clear (goHIGH)in response to the first rising edge of the readclock (CKR) to occur tFFL (First Flag Latency) aftera valid First Write (from the rising edge of CKw).Read clocks occurr.!!!9 less than tFFL after a FirstWrite may clear the EF, but are not guaranteed (seeFigure 10). As always, reads attempted in conjunctionwith an active Empty Flag are inhibited. Therefore,the next rising edge of CKR following tFFL willproduce the first valid read. This is the tFRL (FirstRead Latency) parameter, and must be observedfor proper system operation with the latched. EF.Coming from an empty condition, the First Readoperation should be accomplished by enablingRE1 no less than ts before the rising edge of CKRat tFRL. The a outputs will present valid data tAfrom the riSing edge of CKR.When using the MK4S0SS (Slave) separately, theuser must observe the tFRL (First Read Latency)parameter to ensure first-write-to-first-read validdata. Referring to Figure 11, the first rising edge ofCKR to occur tFRL after a First Write clock willguarantee valid data tA from the rising edge ?fCKR. Read operations attempted before tFRL ISsatisfied may result in reading RAM locations notyet written. Careful observance of tFRL by the useris a must when using free running asynchronousreadlwrite clocks on the MK4S0SS; there is no automaticread and write protection circuitry in theSlave.It should also be noted that the MK4S0SM/S hasan expected "fall-through delay time" described asFirst Write data presented to the FIFO and clockedout to the outside world. This can be calculated as:ts + tFRL + tA (from Figure 10 or 11). Further occurringvalid read clocks will present data to the aoutputs tA from the rising edge of CKR.WIDTH AND DEPTH EXPANSIONA single Master (MK4S0SM) is required for each 1kof depth configured. The number of Slaves that canbe driven by a single Master is limited only by theeffects of adding extra load capacitance (Write andRead Enable Input CapaCitance) onto th~lnputReady (DR), Output Valid (OV), Full Flag (FF) andEmpty Flag (EF) outputs. However, even 40 bits ofwidth (8 devices) results in only 40pf of loading,which corresponds to the amount of load called outin the AC Test Conditions. Additional loading willslow the flags down, but as long as Enable Set Uptime (ts) is met, slowing the flags has no negativeconsequences.WIDTH AND DEPTH EXPANSION EXAMPLESThe width and depth expansion interface timing diagrams(Figures 13 and 14) are in reference to thewidth and depth expansion schematic in Figure 12(For simplicity all clocks have the same frequencyand transistion rate). Example 1 - First Write SinceEmpty - Reading the timing diagram from the topleft to bottom right, one can determine that Figure13 illustrates the effects of the first WRITE/READ9!9les from an EMPTY I!!:.@Y .Q!.,FIFOs. Both of theEF pins are initially low (EFx, EF and RE~. As datais written into Bank A, the expansion clock readsdata from Bank A and writes it to Bank B, the interfaceEF (EF and RE 2) and the external EF (EFx)go inactive (logic 1) while data is shifted throughthe FIFO array from BankAthrough Bank B to theexternal output (ax). The EF logic goes valid (logic0) once data is shifted out of its respective bank.Example 2 - First Read Since Full - Reading the timingdiagram from the bottom left to top right, onecan determine that Figure 14 illustrates the effectsof the first READs from a FULL array of FIFOs. Asdata is read out of the system (ax), it allows BankB to receive data shifted from Bank A. As Bank Bshifts data out via ax, allowing Bank A to shift datainto Bank B, both banks will show a reset FF status(logic 1) on the eX.Q!!nsion FF (FF and WE~ a~ wellas the external FF (FFx). When Bank A IS nolonger considered FULL, Data In from the system(Ox) is now written into Bank A and shifted to BankB until the FIFO array is again completely Full.APPLICATIONThe MK4S0S operates from a S.O volt supply. It iscompatible with aU standard TTL families on all inputsand outputs. The device should share a solidground plane with any other devices interfaced withit, particularly TTL devices. Additionally, becausethe outputs can drive rail-to-rail into high impedanceloads, the MK4S0S can also interface to S voltCMOS on all inputs and outputs.Since very high frequency current transients will beassociated with the operation of theMK4S0S, powerline inductance must be minimized on the circuitboard power distribution network. Power andground trace gridding or separate power planes canbe employed to reduce line inductance. A high frequencydecoLipling capacitor should be placed nextto each FIFO .. The capacitor should be 0.1 "F or larger.Also, a pull-up resistor in the range of 1K ohmsis recommended for the RESET input pin to improveproper operation.Though often times not thought of as such, thetraces on a memory board are basically unterminated,low impedance transmission lines. As suchthey are subject to signal reflect~ons .ma.nifested.asnoise, undershoots and excessive rlngmg. Seriestermination in close proximity to the TTL drivers canimprove driver/signal path impedance matching.While experimentation most often proves to be theonly practical approach to selection of series resistors,values in the range of 10 to 33 ohms oftenprove most suitable.101164S0

~~I~",(II@.~gi~.. (IIIi-i$AF ,0,WEDR,FFxKEY,X = EXTERNA,D. = DATA IN,D. = DATA OUDB"" DATA IN,DB = DATA OU~LlANK A; BANK AlANK B',BANK B10r-BANK AHFAF AE•/ S D. D.VWE 4505MRElDRFF1QV~ I>CKw_ CKRRSiHFj 5 D. D.L v-WE, 45055 REtWE 2 REz~ I>CKw CKoWRITE CLOCKASiEXPANSIONINTERFACELSj.EF r---- f- r-r--FF~EXPANSIONCLOCK5v~BANK B------,AFHFAEDB DB SLWE 4SGSM1 RE,DRCKw _RS!HFQVEl'CKR< r----DB DB 5WE, RE,4505SWE2 REz!=KwASICKoREAD CLOCK."i5c:um.-~i:~enAE,15:i:en10 D, INDV,EFx)C"I~!:I::z:~zccm~::z:m)(~RE,I~0z 3:(II~0::z: en0m eni: 3:~ iO(; en0iii, I en(/)-Z--N~Co)Co)-en0

MK4505M/4505S{N)-25/33/50FIGURE 13. EXAMPLE 1 - WIDTH AND DEPTH EXPANSION INTERFACE TIMINGNEXT OPERATION BANK At, t, t, t, t. t, t, t, t, t.WRITE WRITE READ READ INHIBIT INHIBIT INHIBIT INHIBIT EMPTYDATA 2 DATA 3 DATA 2 DATA 3 (EMPTY)READ DATA'WExOxWRITE CLOCKa, 0,RE,avEFFFDRWE,RE,WE,EXPANSION CLOCK1/II I II I I I1/II1 1\IREx/ I I ill1\Iax DATA 1avx1/EFxLREAD CLOCKNEXT OPERATION BANK B INHIBIT INHIBIT INHIBIT WRITE WRITE WRITE READ READ INHIBIT EMPTY(EMPTY) DATA 1 DATA 2 DATA 3 DATA 2 DATA 3 (EMPTY)READ DATA 1* NOTE: EXAMPLE BEGINS WITH BOTH BANKS EMPTY, AS STATUS FLAGS INDICATE12/16452

MK4505M/4505S(N)-25/33/50FIGURE 14. EXAMPLE 2 - WIDTH AND DEPTH EXPANSION INTERFACE TIMINGNEXT OPERATION BANK AWE,DR,WRITE CLOCKI10 '1 12 13 14 Is .. 17NO'()P NO-OP READ READ WAITE DATA 1 WRITE WRITE FULL(FULL) DEIIP1 DEXP2 READ DATA 2 DATA 3j I I I DE",I IIIIIIIIIIIIII I I I ~I I I I(XXXXXXXXXXXX=I I I I; i i i'------I I 1/ I I I '------1/a. D.RE, DRQV WE,I'\1...----,------,----EFFFRE,WE,EXPANSION CLOCKRE,a, Q-DATA 3READ CLOCKNEXT OPERATION BANK 8 READQ-DATA 1READQ·DATA 2READQ..OATA 3WRITEOEXP1WRITEDExP2WRITEDExpoNO-OP(FULL)NO-OP(FULL)FULL* NOTE: EXAMPlE ·BEGINS WITH BOTH BANKS FULL, AS INDICATED BV STATUS FLAGS13/16453

MK4505M/4505S(N)-25/33/50ABSOWTE MAXIMUM RATINGS·Voltage on any pin relative to GND ......................................... -UN to +7.OVAmbient Operating Temperature (T.v ........................................... 0 to +70 CAmbient Storage Temperature (Plastic) ...................................... -55 to +125 CTotal Device Power Dissipation .................................................... 1 WattRMS Output Current per Pin ...................................................... 25mA·Stresses greater than those listed under ':Absolute Maximum Ratings" may cause permanent damalle to the device. This Is a stressratln", only and functional operation 01 the device at these or other conditions beycnd those indicated In the operational section 01 thisspecIficatIon Is not Implied. Exposure to absolute maximum rating conditions lor extended periods 01 time may alfect reliability.RECOMMENDED DC OPERATING CONDITIONS(O"C sT A s70"C)SYMPARAMETERVee Supply VoltageVSS Supply VoltageV'H Logic 1 InputV'L Logic 0 InputNOTES1. All voltages referenced to GND.DC ELECTRICAL CHARACTERISTICS(O"CsT A s70"C), Vee = 5.0 ± 10%)SYM PARAMETERMK4505-25MIN TYP MAXlee Average Power Supply 115 140CurrentSYM PARAMETERIlLIOLVOHVOLInput Leakage CurrentOutput Leakage CurrentLogic 1 Output Voltage (lOUT = -4 mAlLogic 0 Output Voltage (lOUT = 8 mAlNOTES1. Measured with both ports operating at teK Min, 50%duty cycle, outputs open, Vee max. Typical valuesreflect tcK Min, outputs open, with Vee = 5.0, 25"C,with 50% duty cycle.2. Measured with V = 0,(111 to Vee.CAPACITANCE(T A = 25"C, f = 1.0 MHz)SYMPARAMETERC, Input CapacitanceCOlCO 2Output CapacitanceOutput CapacitanceLIMITSMIN TYP MAXNOTES1. Sampled, not 100% tested. Measured at 1MHz. 3. Measured at EF and FF.2. Measured at all data and flag outputs except EF and FF.14116454UNITS NOTE4.5 5.0 5.5 V 10 0 0 V 12.2 ~ee+1.C V 1-0.3 0.8 V 1MK4505-33 MK4505-50 UNITS NOTEMIN TYP MAX MIN TYP MAX95 140 75 140 mA 1MINMAX-1 +1 pA. 2-10 +10 pA. 2,32.4 V 40.4 V 43. Measured at 00 . 04'Measured after clocking with RE2 = LON (4505S).Measured with CN = LOW (4505M).4. All voltages referenced to GND.TYPLIMITS UNITS NOTEMAX4 5 pf 18 10 pf 1,212 15 pf 1,3

M K4505M/4505S(N)-25/33/50AC TEST CONDITIONSInput levels ............................................................... 0 to 3 VoltsTransition Times ................................................................. S nsInput and Output Reference levels .............................................. 1.S VoltsAmbient Temperature ......................................................... 0 to 70 CVee .................................................................. S.O Volts ± 10%FIGURE 15, EQUIVALENT OUTPUT LOAD CIRCUIT+5V +5V470 OHMS 470 OHMSDUT~~------,DUT~~---...,240 OHMS 40pF'240 OHMS5pF'GNDGND(A), INCWDES SCOPE AND TEST JIG.ORDERING INFORMATIONPART NUMBER CYCLE TIME ACCESS TIME PACKAGE TYPEMK4S0SM(N)-25 25ns 1Sns 24 pin Plastic DIPMK4505M(N)-33 33ns 20ns 24 pin Plastic DIPMK4S0SM(N)-50 50ns 2Sns 24 pin Plastic DIPMK4S0SS(N)-25 2Sns 15ns 20 pin Plastic DIPMK4S0SS(N)-33 33ns 20ns 20 pin Plastic DIPMK4S0SS(N)-SO SOns 2Sns 20 pin Plastic DIPi 505MT~_y5 __TEMPERATUREOOC to 70°CO°C to 700cO°C to 70°CO°C to 70°CO°C to 70°CO°C to 70°CMKSpeed gradeCycle TimePackage TypeN: Plastic DIPDevice family andnumber identification4505M: Master4505S: Slave'--------------------------- SGS;rHOMSON prefix15/164S5

MK4S0SM/4S0SS(N)-2S/33/S020 PIN uN" PACKAGEPLASTIC DIP (MK4505S)-ll---B~1. OVERALL LENGTH INCLUDES ,OtO IN.FLASH ON EITHER END OF THE PACKAGE.2. PACKAGE STANDOFF TO BE MEASUREDPER JEOEC REQUIREMENTS.3, THE MAXIMUM LIMIT SHALL BEINCREASEO BY .003 IN. WHENSOLDER LEAD FINISH IS SPECIFIEO.ADim.AlA2881CDDlEEl.1eALmminchesNolesMin Max Min Max- 5.334 - 210 20.361 - 015 - 23.046 3.556 .120 .1400.361 0.533 .015 .021 31.143 1.776 .045 .0700.203 0.304 .006 .012 325.906 26.67 1.020 1.050 11.524 1.905 .060 .0757.62 6.255 .300 .3256.096 6.656 .240 .2702.266 2.794 .090 .1107.62 9.271 .300 .3653.175 - .125 -24 PIN uN" PACKAGEPLASTIC DIP (4505M)Ai ~--11-.NOTES1. OVERALL LENGTH INCLUDES . a 10 IN.FLASH ON EITHER END OF THE fYACKAGE.2. PACKAGE ST ANOOFF TO BE MEASUREDPER JEDEC REGUIREMENTS.3. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. WHENSOLDER LEAD FINISH IS SPECIFIED.ADim.AlA2881CDDlEEl01oALmminchesNolesMin Max Min Max- 5.334 - 210 20.361 - .015 - 23.046 3.556 .120 .1400.361 0.533 .015 .021 31.143 1.776 .045 .0700.203 0.304 .006 .012 3- 32.256 - 1.270 11.524 2.266 .060 .0907.62 6.255 .300 .3256.096 6.856 .240 .2702.266 2.794 .090 .1107.62 9.271 .300 .3653.175 - .125 -16116456

MK45264/45265(N)-55/70(64x5)x2CMOS BIDIRECTIONAL BiPORT FIFOITRANSCEIVER• DUAL 64x5 FIFOs PLUS A '245-TYPE TRAN­SCEIVER FUNCTION• FULLY ASYNCHRONOUS DUAL PORTOPERATIONADVANCED DATA• EMPTY, FULL, ALMOST FULL AND ALMOSTEMPTY STATUS FLAGS• SPARE BITS FOR PARITY AND BEGIN­NING/END-OF-MESSAGE FLAGSNDIP-24(Plastic Package)• +1- 12mA OUTPUT DRIVE CAPABILITY• DUAL Vee AND Vss FOR IMPROVED MARGINAND DRIVE• 300 MIL DIP PACKAGE• APPLICATION: ARBITRATION-FREE /LP.:rO-/LPMESSAGE PASSINGPART ACCESS CYCLE CYCLENUMBER TIME TIME RATEMK45264N-55 55 ns 75 ns 13.3 MHzMK45264N-70 70 ns 95 ns 10.5 MHzMK45265N-55 55 ns 75 ns 13.3 MHzMK45265N-70 70 ns 95 ns 10.5 MHzPIN NAMESVee, VssDQxo-DQx4DQYO-DQY4W;.; WyFlx/DIRGFlyRSEFx, FFyEFy, FFxAEy, AFxAEx, AFy= +5V, GND= X Port Data I/O= Y Port Data I/O= X & Y Port Write Enables= X Port Read Enable andTransceiver Direction Control= Transceiver Enable= Y Port Read Enable= Master Reset= Y-to-X FIFO Empty/Full Flag= X-to-Y FIFO Empty/Full Flag= X-to-Y FIFO Almost Empty/Full= Y-to-X FIFO Almost Empty/FullFIGURE 1. PINOUT. 24 PIN, 300 MIL DIPv •• 1 24 VeeG 223 'NyRx/DIR 3 22 FFyEFx 4 21 DQyoDQxo 5 20 DQYlDQX1 6 19 DQY2DQX2 7 18 DQY3DQ .. 8 17 DQy,DQX4 9 16 EFyFFx 10 15 iiy'Nx 11 14 ASVee 12 13 V ••V.s 1 24 VeeG 223 'Nyiix/DIR 3 22 MyliEx 4 21 DQyODQxo 5 20 DQY1DQX1 6 19 DQY2DQX2 7 18 DQY3DQX3 8 17 DQy,DQX4 9 16 liEyMx 1015 iiy'Nx 11 14 ASVee 12 13 V O•June 19881118This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice 457

MK4S264/4S26S(N)-SS/70FIGURE 2. DEVICE LOGIC SYMBOLv •• Vee v •• VeeFFx FFy M x MyEFx EFy lIE. AEyGRx/OIRWXMK45264MK45265OOXvee v •• vee V ••TRUTH TABLEm ~ Tx/OIR Wx Ry Wy MODE oax DayLo X X X X X Master Reset High Z High ZHi Lo Hi X X X Transparent X-Y Data In DQxHi Lo Lo X X X Transparent V-X DQy Data InHi Hi Hi Hi Hi Hi Sby X I Sby V High Z High ZHi Hi Hi Hi Lo Hi Sby X I Read V High Z Data OutHi Hi Hi Hi X Lo Sby X I Write V High Z Data InHi Hi Lo Hi Hi Hi Read X I Sby V Data Out High ZHi Hi Lo Hi Lo Hi Read X I Read V Data Out Data OutHi Hi Lo Hi X Lo Read X I Write V Data Out Data InHi Hi X Lo Hi Hi Write X I Sby V Data In High ZHi Hi X Lo Lo Hi Write X I Read V Data In Data OutHi Hi X Lo X Lo Write X I Write V Data In Data Inx = Don't CareNOTE: Truth Table logic states presume all status flags to be inactive.2/18458

MK45264/45265(N)-55noFIGURE 3. BLOCK DIAGRAM5 5DODOTRANSCEIVERr---- DIRGGFF, {M,)r--WX·TO-YFIFO64x5R'-EFy (AEy)5D0RS 5W, X PORTY PORTRy,JDIR5r--110 READ&WRITECONTROLREAD 110 ~&WRITE ......CONTROLWyRS50RSD5EF, (AE,)_RY-TO-X W~FIFO64xSFFy (My)DEVICE APPLICATION/FUNCTIONThe MK45264/65 contains two independent singledirection FIFOs, and a bidirectional transceiver, connectedvia two internal three state busses to 110drive circuits. One FIFO is pointed X-to-Y, and theother pOinted Y-to-X. Either port's FIFOs can be reador written asynchronous with FIFO read or writeoperations on the othe!'port. The transceiver is activatedwith a low on G.Once the transceiver is activated, direction is controlledby the Rx/DIR pin. A high on Rx/DIR pointsthe transceiver X-to-Y; a low points it Y-to-X. A lowon G disables FIFO operations. Activating the Transceiverduring FIFO operations may result in invalidor unpredictable FIFO operation.3118459

MK45264/45265(N)-55nOAC ELECTRICAL CHARACTERISTICS(TA = 0° to 70°C, Vee = 5.0 ±10%)ALT. STD.SYMBOL SYMBOL PARAMETERtp tRL·RH Read Pulse Widthtp tWL.WH Write Pulse Widthtp tGH.RH X-ceiver Disable to end of Readtp tGH.WH X-ceiver Disable to end of WritetR tRH.RL Read Recovery TimetR tWH.WL Write Recovery TimetR tRH-WL Read Write Recovery TimetR tWH.RL Write Read Recovery Timete tRL.RL Read Cycle Timete tWL.WL Write Cycle Timetos tOV.WH Data Set Up TimetOH tWH.OX Data Hold TimetOL tRL·OL R Low to Outputs Low-ZtA tRL·OV Read Access TimetOH tRH·OX Output Hold TimetOH tWL·OX Output Hold Timetoz tRH·OZ R High to Outputs High-Ztwoz tWL·OZ W Low to Outputs High-ZtFL1 tWL·FFL W Low to Full Flag LowtFL1 tRL.EFL R Low to Empty Flag LowtFH1 tWH.EFH W Hi to Empty Flag HightFH1 tRH.FFH R Hi to Full Flag HightFL2 tWL.AFL W Low to Almost Full Flag LowtFL2 tRL.AEL R Low to Almost Empty Flag LowtFH2 tWH.AEH W Hi to Almost Empty Flag HightFH2 tRH.AFH R Hi to Almost Full Flag Hightl tWL.FFH Write Protect Indeterminatetl tRL.EFH Read Protect Indeterminate!FR tFFH-WL Full Flag RecoverytFR tEFH-RL Empty Flag RecoverytRS tRSL-RSH Reset Pulse Width55 70MIN MAX MIN MAX UNITS NOTES55 70 ns55 70 ns55 70 ns55 70 ns20 25 ns20 25 ns20 25 ns20 25 ns75 95 ns75 95 ns20 25 ns5 5 ns5 5 ns 255 70 ns 35 5 ns 35 5 ns 330 40 ns 245 55 ns 260 80 ns 460 80 ns 450 65 ns 450 65 ns 460 80 ns 560 80 ns 575 95 ns 575 95 ns 525 30 ns 625 30 ns 70 0 ns 60 0 ns 755 70 ns4/18460

MK45264/45265(N)-55noAC ELECTRICAL CHARACTERISTICS(TA = O· to 7O"C. Vee = 5.0 ±10%)ALT. STD.SYMBOL SYMBOLPARAMETERtRSR tRSH.WH Reset Recovery TimetRFV tRSL.FFH Reset to Full Flag ValidtRFV tRSL-AFH Reset to AF Flag ValidtRFV tRSL.EFL Reset to Empty Flag ValidtRFV tRSL-AEL Reset to AE Flag ValidtROX tRSL.QX Outout Hold from AS LowtROZ tRSL.QZ RS Low to Output High Z55 70MIN MAX MIN MAX UNITS NOTES75 95 ns70 90 ns 370 90 ns 370 90 ns 370 90 ns 30 0 ns 340 50 ns 2tFG tWH·GL FIFO Mode to X-ceiver Mode 0 0 nstFG tRH.GL FIFO Mode to X-ceiver Mode 0 0 nstGF tGH-WL X-ceiver Mode to FIFO Mode 5 5 nstGF tGH·RL X-ceiver Mode to FIFO Mode 5 5 nstGOL tGL.QL G to Output Low ZtGQV tGL.QV G to Output ValidtGOX tGH·OX Output Hold from GtGQZ tGH.OZ G to Output High Ztovav tov·av Input to Output Validtoxox tox·ox Input to Output InvalidtOOL tOIRV·OL Rx/DIR to Output Low Ztoav tOIRV.QV Rx/DIR to Output Validtoox tOIRV.QX Output Hold from Rx/DIRtooz tOIRV.QZ Rx/DIR to Output High Z0 0 ns 275 95 ns 30 0 ns 340 50 ns 255 70 ns 310 10 ns 30 0 ns 255 70 ns 30 0 ns 340 50 ns 2NOTES1. All AC Electrical Characteristics measured under conditionsspecified in "AC Test Conditions".2. Measured wl5pf Output Load. See Equivalent Load CircuitB.3. Measured w/30pf Output Load. See Equivalent Load CircuitA.4. Applies to EFX. FFX. FFy. EFy. Measured w/30pf OutputLoad. See Equivalent Load Circuit C.5. Applies to AEX. AFx. AEy. AFy. Measured w/30pf OutputLoad. See Equivalent Load Circuit C.6. Writes beginning a) more than tl (max) before FF goeshigh will be blocked.lliess than tl (max) before and lessthan tFR (min) aft~F goes high may be performed.c) tFR (min) after FF goes high will be performed.7. Reads beginning a) more than tl (max) before EF goeshigh will be blocked.lliess than tl (max) before and lessthan tFR (min) aft~EF goes high may be performed.c) tFR (min) after EF goes high will be performed.~ SGS-tHOMSON"1l lIID©lIII@rn~l

MK45264/45265(N)-55noReadlWriteThe FIFOs utilize separate Read and Write enableinputs to control port activity and direction. A lowon a Read Enable reads a port's receive FIFO. Ahigh on a Read Enable or a low on a Write Enabledisables a port's data outputs to a high impedancestate. A low on a Write Enable initiates a write toa port's transmit FIFO, regardless of the state ofRead Enable. Input data is latched into the FIFOon the rising edge of a Write Enable.Full/Empty FlagsAn active Full Flag indicates that a port's transmitFIFO is full and will accept no more data. Writesdone to a FIFO while full are blocked. Once a readhas occurred on a full FIFO, clearing a location inthe FIFO, the Full Flag will go inactive, allowinganother write to begin on the next falling edge ofWrite Enable.An active Empty Flag indicates a port's receive FIFOis empty and can send no more data. Any readsdone on a FIFO while empty are blocked. Once awrite to an empty FIFO has occurred, the EmptyFlag will go inactive, allowing another read to beginon the next falling edge of Read Enable.FIGURE 4. WRITE TIMINGAlmost FlagsAn inactive Almost Full flag indicates a port's transmitFIFO has room for at least four (4) more bytes,which is to say the flag will go active during thefourth write from full and stay active until after thefourth location from full has been vacated (read).An inactive Almost Empty flag indicates a port'sreceive FIFO has at least four (4) bytes of data inmemory, ready to be read, which is to say that theflag will go active while reading the fourth remainingbyte and remain active until after the fourth bytehas been stored (written).ResetReset is initiated by a low on the Master Reset (RS)input. A reset returns all data outputs to a high impedance..,§!ate, takin9...Preced~nce over the readstrobes (Rx/DIR andfu) and§.:. The states of theFIFO control inputs (Rx/DIR, Wx, Ry and Wy) area Don't Care throughout reset. The read strobes area Don't Care at the end of reset because the EmptyFlag becomes active (goes low) during reset,blocking ~ attempted reads. The write strobes(Wx and Wy) may fall any time during....Q!. afterreset, but must not go high until t RSR after RS goeshigh.tet. tAt.WxtOHtOHDOxDATA INDATA IN6118462

--------~----~------~~-.------------~MK4S264/4S26S(N)-SSnoFIGURE 5. READ TIMINGI+------'c-----+-IDO. ------tHFIGURE 6. WRITE/READ TIMING14----,p----+-IDO. ------+-FIGURE 7. READ/WRITE TIMING14-----'c-----+\DATA IN7/18463

MK45264/45265(N)-55noFIGURE 8. FULL (ALMOST FULL) FLAG TIMINGliyWxFFX(AI'x)t'"lIILIFIGURE 9. EMPTY (ALMOST EMPTY) FLAG TIMINGIFIGURE 10. FIRST WRITE AFTER FULL TIMINGI=-1 ___ I_FH _-_____8/18464

MK45264/45265(N)-55nOFIGURE 11. FIRST READ AFTER EMPTY TIMING/'----__ J~ ~I_FH ___---_______________________'ii, \ __FIGURE 12. FIFO RESET TIMINGRsR,/DIRANDRy'ii,ANDWyALL FF& Ai'XXRXXXXXXxxXXXXXXXXXXXI ~'"' 1-~ 1ALL ifF&AEALL DQ------------------- ~~~tm?:~~ ________________ ~9/~18465

MK4S264/4S26S(N)-SSnoFIGURE 13. TRANSCEIVER RESET TIMING(EXAMPLE SHOWN WITH Rx/DIR HIGH)DQX .....--~(~__....................____.....D_~_A_IN .....____________ ~)~------DQ y ..... ---------(FIGURE 14. FIFO MODE/TRANSCEIVER MODE TRANSITIONFIGURE 15. TRANSCEIVER G TIMING(EXAMPLE SHOWN WITH Rx/DIR HIGH)DQ y ............... ------0{ DATA OUTDQ X --------I-DATA IN10118466

MK45264/45265(N)-55noFIGURE 16. TRANSCEIVER Rx/DIR TIMING(EXAMPLE SHOWN WITH GLOW)DATA INDATA OUTDATA OUTFIGURE 17. WRITE/ALMOST FULL/FULL FLAG TIMING SUMMARYFIFO CONTENTS59 60 61 6263 6411/18467

MK45264/45265(N)-55noFIGURE 18. WRITE/ALMOST EMPTY/EMPTY FLAG TIMING SUMMARY2 5IPH• r---t------FIGURE 19. READ/ALMOST EMPTY/EMPTY FLAG TIMING SUMMARY3-----LFIGURE 20. READ/ALMOST FULL/FULL FLAG TIMING SUMMARY64 63 62 61 60 59R.----~~.f=----~~----12/18468

MK45264/45265(N)-55noABSOWTE MAXIMUM RATINGSVoltage on any pin relative to Vs§.. .......................................... -1.5V to +7.0VAmbient Operating Temperature (I A> .......................................... 0° to +70 'CAmbient Temperature under Bias ......................................... -55° to +125'CAmbient Storage Temperature (Plastic) ..................................... -55° to +125'CAllowable Total Device Power DiSSipation ........................................... 1 WattAllowable RMS Output Current per pin ............................................. 80 mARECOMMENDED DC OPERATING CONDITIONS(TA = 0° to +70OC)SYMBOL PARAMETERVccVSSVIHVILSupply VoltageSupply VoltageLogic 1 InputLogic 0 InputNOTE: 1. All voltages referenced to VSS.DC ELECTRICAL CHARACTERISTICS(TA = 0° to 70° C. Vcc = 5.0 ± 10%)MIN4.502.2-0.3LIMITSTYP MAX UNITS NOTE5.0 5.5 V 10 0 V 1Vcc+0.3 V 10.8 V 1SYMBOL PARAMETERLIMITSMIN TYP MAX UNITS NOTEIccQ Quiescent Power Supply Current. per Port 5 mA 1.2ICCA Active Power Supply Current. per Port 10 mA 1.3ICCD Dynamic Power Supply Current. per Port 1.2 mA/MHz 1,4IcerIlLIOLVOHVOLTotal Power Supply Current. both PortsInput Leakage CurrentOutput Leakage CurrentLogic 1 Output VoltageLogic 0 Output VoltageNOTES1. Measured with outputs open.2. Measured with opposite port quiescent; R. Wand G ~VIH (Min). _ _3. Measured \!!!th opposite port quiescent; R or W s VIL(Max) and G ~ VIH (Min.). _ _4. Me~red with opposite port quiescent; R or W togglingaDd G ~ VIH (Min.).CAPACITANCETA = 0° to 7OOC. Vr.r. = 5.0 ± 10%)SYMBOL PARAMETERCI Input CapacitanceCo Output CapacitanceNOTE: 1. Sampled. not 100% tested. Measured at 1MHz.60 mA 1.5-1 +1 pA. 6-10 +10 pA. 72.4 V 7.80.4 V 7.95. Measured with both ports operating at te (Min.).6. Measured wilh VIN = OJN to Vee.7. All voltages referenced to VSS.8. Oala Output Pins (OQxo-OQ)C4 and OOyn-DQy4) louT.=...-12mA; F~ Output Pins EFX. EFy. FFX. FFy. AEX.AEy. AFX. AFy) lOUT = -1mA.9. Data Outputs (OQXO-OQX4..!Ind OQya:QOvAl,IOUI. =12mA; Flag..Q.utput Pins EFX. EFy. FFX. FFy. AEX.AEy. AFX. AFy) lOUT = 4mA.LIMITSMIN TYP MAX . UNITS NOTE4 5 pf 18 10 pf 113118469

MK4S264/4S26S(N)-SSI7OAC TEST CONDITIONSInput Levels ............................................................... 0 to. 3 VoltsTransition Times ................................................................. 5 nsInput and Output Reference Levels ............................................... 1.5 VoltsAmbient Temperature ........................................................ 0° to 7O"CVee = 5.0 Volts ± 10%FIGURE 21, EQUIVALENT OUTPUT LOAD CIRCUIT+5V+5V298 OHMS298 OHMSDUT--+------,116 OHMS =p 30pF'OUT116 OHMSt~·(A)v,,(8)+5VlK OHMSDUT--+------,667 OHMS = = 30pPv,,(C)'INCLUDES SCOPE AND TEST JIG.APPLICATION ISSUESWidth ExpansionThe MK45264/65 is designed to be used in sets oftwo or more, as shown below. The MK45264/65 issupplied in two configurations, MK45264 andMK45265; the MK45264 having Empty and FullFlags, the MK45265 having Almost Empty andAlmost Full Flags. This scheme allows a pair ofdevices to be connected in such a way as to assurethat the PAIR present a full complement of statusflags in BOTH directions, that is, both to the leftand to the right.The resulting 10 bit wide configuration allows bothparity AND beginning or end of message flag bitsto be carried along with an 8 bit byte of data. The20 bit wide configuration allows carrying 2 bits ofparity AND separate message start and stop bitsin 16 bit applications.The MK45264/65 was designed as a 5 bit widedevice in order to allow the use of a 300 mil DIPpackage; allowing the MK45264/65 to: a) achievethe highest function/board space ratio possible fora fully featured bidirectional BiPORT FIFO, b) providehigher performance with improved noise marginsthan would be possible in higher pin countpackages, and c) provide greater flexibility to usersof various bus widths.14118470

MK4S264/4S26S(N)-SSI7OFIGURE 22. (64x10)x2 WIDTH EXPANSIONDOo·DQ. ..AILI5,. .. DO,ii,W,'DO,W,ii,DOo·OO.WCIIIEFCL)"ILl",if,r--- ii-iiGVi"" W,ii,M1

MK45264/45265(~)-5snoWidth Expansion and Word-SkewWord-skew, in this context, is defined as what happenswhen FIFOs that are wired in parallel for widthexpansion get out of sync with one another. Haltingwrites when full and reads when empty circumventsthe problems altogether. Reading while emptyand writing while full should, therefore, be avoided.The problem of word-skew can emerge if oneis using the MK45264/65 in width expansion modeAND writing (or reading) WHILE full (or WHILEempty).Slight differences in Full (or Empty) Flag responsedelays between different devices may result in "disagreements"between adjacent devices as they gofrom Full to Not Full or from Empty to Not Empty;resulting in one device accepting an attempted write(or read) while an adjacent device blocks the cycle.The simplest approach to avoiding word skewis configuring the system using the FIFOs to beginreading only when the Almost Empty flag has gonehigh, rather than right after the Empty flag has gonehigh. In like manner, waiting to write until the AlmostFull flag goes high, rather than right after the Fullflag goes high will prevent the problem, which iswhy the Almost flags are provided. However, shouldsuch a scheme prove unworkable in a particular appication,the addition of an external flag latchingcircuit can also solve the problem.The circuit shown below, when connected to theWrite strobe and Full Flag, latches the status of theflag at the beginning of a write. If the flag is inactive,the Write strobe is passed through to the FIFO.When the flag goes active (low) the falling-edge triggeredflop is reset. The reset flop, in concert withthe level-sensitive latch and the OR gate block thewrite strobe.Tying the Flag to the Reset input of the edgetriggeredflop assures that the Write strobe isblocked on the first write attempted after the flagfalls. The level sensitive lat~h also prevents transitionsin the flag from disturbing cycles ,hat are alreadyin progress. In the event that a write is begunjust as the flag is gQing inactive (high) the fallingedge-triggered flop will latch its interpretation of themetastable flag. If it interprets the metastable inputas being low, the present and next cycle areblocked, as were their predecessors. If it interpretsthe flag as being high, the present cycle is stillblocked, because the the level sensitive latch wasstill seeing an active flag as the cycle began.However, the next attempted cycle is passedthrough.Although "throwing away" write cycles goes againstthe grain conceptually, it does not actually presenta problem in this situation. It must be assumed thatWriting while Full or Reading while Empty wouldonly be allowed in applications where the writeand/or read strobes are proceeding regardless ofFIFO status anyway.· "Throwing away" reads orwrites cannot, by definition, be considered an error.Remember, overall signal timing must comprehendthe delays of the particular components chosen toimplement the external circuit.FIGURE 24. EXTERNAL ANTI-WORD·SKEW CIRCUITFALLING EDGE· TRIGGEREDD·TYPE FLIP.FLOPLEVEL SENSITIVED-TVPE LATCH----_ .. D QI---t-iD Qcw16/184-72

MK45264/45265(N)-55noOverlapping Read and Write StrobesOverlapping Read and Write strobes on a given port timing diagrams are provided only to illustrate theis neither tested nor recommended. The following relationship between the control functions.FIGURE 25. OVERLAPPING READIWRITE TIMING~ _____________________ tp ______________________ ~DOx -------< DATA OUTDATA INNOTE: THE SECOND D OUT IS THE SAME AS THE FIRST. AOVERLAPPING WRITE DOES NOT INCREMENT THE READ AD·DRESS COUNTER.FIGURE 26. OVERLAPPING READIWRITE TIMINGI-+------tp---........,~DOX -------{NOTE: THE SECOND D OUT IS NOT THE SAME AS THE FIRST.IT IS, IN. FACT, THE NEXT READ DATA. AN OVERLAPPING WRITEDOES NOT BLOCK THE READ STROBE FROM INCREMENTINGTHE READ ADDRESS COUNTER.17/18473

MK45264/45265(N)-55noORDERING INFORMATIONPART NO. ACCESS TIMERIW CYCLETEMPERATURECLOCK FREQ. PACKAGE TYPETIMERANGEMK45264N·55 55 ns 75 ns 13.3 MHz 24 Pin Plastic DIP 0° to 70°CMK45265N-55 55 ns 75 ns 13.3 MHz 24 Pin Plastic DIP 0° to 70°CMK45264N-70 70 ns 95 ns 10.5 MHz 24 Pin Plastic DIP 0° to 70°CMK45265N-70 70 ns 95 ns 10.5 MHz 24 Pin Plastic DIP 0° to 70°C18/18474

STATIC RAM DEVICESVERY FAST STATIC RAM475

MK41H661M K41 H67(N, P)-20/25/3516K x 1 CMOS STATIC RAM• 20, 25, AND 35 ns ADDRESS ACCESS TIME• EQUAL ACCESS AND CYCLE TIMES• 20-PIN, 300 MIL PLASTIC AND CERAMIC DIP• ALL INPUT AND OUTPUT PINS TIL COMPATI­BLE, LOW CAPACITANCE, AND PROTECTEDAGAINST STATIC DISCHARGE• 50 pA CMOS STANDBY CURRENT (MK41H67)NDIP-20(Plastic Package)PDIP-20(Ceramic Package)• HIGH SPEED CHIP SELECT (MK41H66)FIGURE 1. PIN CONNECTIONS• JEDEC STANDARD PINOUTMK41H66 TRUTH TABLE~ WE Mode DQH X Deselect High ZL L Write High ZL H Read Data Outx = Don't CareMK41H67 TRUTH TABLEPowerActiveActiveActiveA. 1A, 2A, 3A, 4A. 5A, 6A. 7Q 8WE 9GND 1020 Vee19 A1318 A1217 A"16 A,.15 A,14 A,13 A,12 011 CS~ WE Mode DQH X Deselect High ZL L Write High ZL H Read Data OutDESCRIPTIONPowerStandbyActiveActiveThe MK41H66 and MK41H67 feature fully staticoperation requiring no external clocks or timingstrobes, and equal address access and cycle times.Both require only a single +5V ± 10 percent powersupply. Both devices are fully TIL compatible.The MK41H67 has a Chip Enable power down featurewhicwtomatically reduces power dissipationwhen the CE pin is brought inactive (high). Standbypower can be further reduced to microwatt levelsby holding the Address and CE pins at full supplyrail voltages.A. 1A, 2A, 3A, 4A. 5A, 6A. 7Q 8WE 9GND 10PIN NAMESAo -~ - AddressCE - Chip Enable(MK41H67)CS - Chip Select(MK41H66)20 Vee19 A1318 A1217 A"16 AlO15 A,14 A,13 A,12 011 CE~ - Write EnableGND - GroundVcc - + 5 voltsD - Data InQ - Data OutJune 19881/10477

MK41 H66/MK41 H67(N, P)-20/25/35The MK41H66. Chip Select pin provides a highspeed chip select access, allowing fast read cyclesdespite decoder delays.OPERATIONSREAD MODEThe MK41H6617 is in the Read Mode whenever WE(Write Enable) is high and CE/CS (Chip Enable/Select)is low, providing a ripple-through accessFIGURE 2. READ-READ-READ-WRITE TIMING.. to anyone of 16,384 locations in the static storagearray. Valid data will be available at the Data Outputpin (a) within tM after the last address inputsignal is stable, provld!!]g that the CE/CS accesstime is satisfied. If CE/CS access time is not met,data access will be measured from the limitingparameter (tCM rather than the address. The stateof the Data Output pin is controlled by the CE/CS,and WE control signals. The a may be in an indeterminatestate at tCL' but the a will always have validdata at tAA.t,, __ ~ __ t,, __ ~ __'"=1 -'"=~-~~---~~---~I toe H-I----1 too------'-------'--'----~_____'___'__r t" r----------,--,---------------:---~--j toeQREAD CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(OOCsTAs70OC) (Vcc = 5.0 V ± 10 percent)SYM PARAMETER MIN MAXtRC Read Cycle Time 20tAA Address Access Time 20teL Chip Enable to Low-Z (MK41H67) 5tCL Chip Select to Low-Z (MK41 H66) 5teA Chip Enable Access Time (MK41H67) 20tCA Chip Select Access Time (MK41H66) 10tRCS Read Command Setup Time 0tRCH Read Command Hold Time 0tOH Valid Data Out Hold Time 5tcz Chip Enable to High-Z (MK41H67) 8tez Chip Select to High-Z (MK41H66) 7twEZ Write Enable to High-Z 8MK41H6X-20 MK41H6X-25 MK41H6X-35MIN MAX MIN MAX UNITS NOTES25 35 ns25 35 ns 15 5 ns 25 5 ns 225 35 ns 112 15 ns 10 0 ns0 0 ns5 5 ns 110 13 ns 28 10 ns 210 13 ns 22110478

MK41H66/MK41 H67(N, P)-20/25/35WRITE MODEThe MK41H66n is in the Write Mode whenever theWE and 'CE/es inputs are in the low state. CE/~or WE must be high during address transitions. Addressesmust be held valid throughout a write cycle.The Write b~s with the concurrence of a lowon WE and 'CE les. Therefore, tAS is referenced tothe latter occurring edge of CE/es, or WE.If the output is enabled (CE/es is low), then WEwill return the output to high impedance withintWEz of its falling edge. Data-In must remain validtOH after the rising edge of CE/es or WE.FIGURE 3. WRITE-WRITE-WRITE-READ TIMING-----o-f+---.. ,I IQWRITE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O"CsTAs70"C) (Vee = 5.0 V ± 10 percent)SYM PARAMETERMK41H6X-20 MK41H6X-25 MK41H6X-35MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 20 25 35 nstAS Address Setup Time 0 0 0 nstAW Address Valid to End of Write 16 20 30 nstAH Address Hold after End of Write 0 0 0 nstew Chip Enable/Select to End of Write 18 22 32 nstWEW Write Enable to End of Write 16 20 30 nstos Data Setup Time 12 14 15 nstoti Data Hold Time 0 0 0 nstWEL Write Enable to Low-Z 5 5 5 ns 23110479

MK41H66/MK41 H67(N ,P)-20/25/35FIGURE 4. DATA RETENTION TIMINGLOW Vee DATA RETENTION TIMING (MK41H67)1+---- DATA RETENTION MODE -----,10-1Vee------~IVee (MIN)- -ao----Jw-------------------------LOW Vee DATA RETENTION CHARACTERISTICS(O°CsTAs70°C)VORSYMICCORtcoRtRPARAMETERSV cc for Data RetentionData Retention Power Supply CurrentChip Deselection to Data Retention TimeOperation Recovery TimeSTANDBY MODE (MK41H67 Only)The MK41H67 is in Standby Mode whenever CE isheld at or above V 1H.FIGURE 5. STANDBY MODE TIMINGCe_--/1MIN MAX UNIT2.0 Vcc (min) V- 50 pA0 - nstRC - ns\\'-------NOTES77\ ------ACTIVE---·--- /50%\STANDBY/STANDBY MODEAC ELECTRICAL CHARACTERISTICS(OOCsTAS70OC) (Vcc = 5.0 V ± 10 percent)MK41H67-20 MK41H67-25 MK41H67-35SYM PARAMETER MIN MAX MIN MAX MIN MAXtpo Chip Enable High to Power Down 20 25 35tpu Chip Enable Low to Power Up 0 0 0UNITSnsnsNOTES4110480

MK41H66/MK41H67(N,P)-20/25135APPLICATIONThe MK41H6617 operates from a 5.0 volt supply. Itis compatible with all standard TIL families on allinputs and outputs. The device should share a solidground plane with any other devices interfaced withit, particularly TIL devices. Additionally, becausethe outputs can drive rail-to-rail into high impedanceloads, the 41H6617 can also interface to 5 volt CMOSon all inputs and outputs. Refer to the normalizedperformance curves that follow.Since very high frequency current transients will beassociated with the operation of the MK41H6617,power line inductance must be minimized on thecircuit board power distribution network. Power andground trace gridding or separate power planes canbe employed to reduce line inductance. Additionally,a high frequency decoupling capacitor shouldbe placed next to each RAM. The capacitor shouldbe 0.1 pF or larger.Though often times not thought of as such, thetraces on a memory board are basically unterminated,low impedance transmission lines. As suchthey are subject to signal reflections manifested asnoise, undershoots and excessive ringing. Seriestermination in close proximity to the TIL drivers canimprove driver/signal. path impedance matching.While experimentation most often proves to be theonly practical approach to selection of series resistors,values in the range of 10 to 33 ohms oftenprove most suitable.ABSOWTE MAXIMUM RATINGS·Voltage on any pin relative to GND ....................................... -1.0 V to +7.0 VAmbient Operating Temperature (T,v ......................................... OOC to +70OCAmbient Storage Temperature (Plastic) .................................... -55OC to +125'CAmbient Storage Temperature (CeramiC) .................................. -65OC to +150OClbtal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 50 mA·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or other conditions beyond those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(OOCsT A s70OC)SYMVccGNDVIHVILPARAMETERSupply VoltageSupplX VoltageLogic 1 Voltage, All InputsLogic 0 Voltage, All InputsMIN TYP4.5 5.00 02.2-0.1MAX UNITS NOTES5.5 V 30 VVcc +1.0 V 30.8 V 3,4DC ELECfRICAL CHARAcrERISTICS(OOCsT A s70OC) (Vcc = 5.0 V ± 10 percent)SYMPARAMETERMINMAX UNITS NOTESICclAverage Power Supply Current120 mA 5Icc2ICC3IlL10LVOHTIL Standby Current (MK41H67 only)CMOS Standby Current (MK41H67 only)Input Leakage Current (Any Input Pin)Output Leakage Current (Any Output Pin)Output Logic 1 Voltage (lOUT = -4 mA)-1-102.410 mA 650 pA 7+1 pA 8+10 pA gV 3VOLOutput Logic 0 Voltage (lOUT = +8 mA)0.4 V 3511048'1

MK41H66/MK41H67(N,P)-20/25/35CAPACITANCE(TA = 25OC, f = 1.0 MHz)SYM PARAMETERC, Capacitance on input pinsC2 Capacitance on Q pinsTYP MAX UNITS NOTES4 5 pF 108 10 pF 5, 10NOTES1. Measured with load shown in Figure 6(A).2. Measured with load shown in Figure 6(B).3. All voltages referenced to GND.4. VIL may undershoot to -2.0 volts for 200ns or less duringinput transitions.5. ICCl is measured as the average AC current with VCC= V CC (max) and with the outputs open circuit. tcycle= min. duty cycle 100%.6. CE = VIH, All Other Inputs = Don't Care.7. VCC (max) «CE«VCC - 0.3 VGND + 0.3 V«AO-A13«VIL (min) or VIH (max)«AQ-A13"'VCC -0.3 V. All Other Inputs = Don't Care.8. Input leakage current specifications are valid for all VINsuch that 0 V

MK41H66/MK41H67{N,P)-20/25/35NORMALIZED DC AND AC PERFORMANCE CHARACTERISTICS'208NORMALIZED CHIP ENABLE ACCESS TIME VS.AMBIENT TEMPERATURE Vee o5.0V0.7-j-+-+-t-t-H-t-++-+-+-+-t-I-HH-f....,~60 -40 20 40 60 80 100 120E 1.7~ 1.6~U§~ 1.3LOGIC THRESHOLD VOLTAGE VS.SUPPLY VOLTAGE TA ~25°CIIlvv IIIV 1H ~ -- - .I> --, .----l-~~---_.-:.~----.,. ... --VI-- ~Jr---44 4.8 5.2 5.6 5.8AMBIENT TEMPERATURE ('C)SUPPLY VOLTAGE (V)LOGIC THRESHOLD VOLTAGE VS.AMBIENT TEMPERATURE Vtto5.0V- ! r-+- t~ 1.6 +-+-t-t-H-+-+-,-++=!"'"....kH-+-+-+~I-~ i -~ I9 l.4+-+-t-t-H-+-+-++++-+-I--iH-+-+-+~~t­---- -.- --- --: ---,--- ---f- ---t'-- ----60 -40 -20 20 40 80 100AMBIENT TEMPERATURE (OC)~~4.53.5~ 2.5~~0.5-NORMALIZED ACCESS TIME VS.OUTPUT LOADING Vcc~5.0 V TA~25°C---+-V/'""V~ .. -.- -_._-- -.-'.~ .-V- _.j/I---200 400 600 800CAPACITANCE (pF)-- --".- -- .--- ----;7"---...1000'.3'2,0.80.70.6/NORMALIZED SUPPLY CURRENT VS.SUPPLY VOLTAGE T A ~O°C//"'"vr/' I4,2 4.4 4.6 4.8 5.2 5.6 5.8,/_8S~~~'.21.150.950.9I,,~ ..'"-1--NORMALIZED SUPPLY CURRENT VS.AMBIENT TEMPERATURE Vee ~5.0Vj'" , "',,1-"-0.85'"0.80.75I-60 -40 -20 20 60 80 100 120-~SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE (OC)7/10483

MK41H66/MK41H67(N,P)-20/25/35NORMALIZED DC AND AC PERFORMANCE CHARACTERISTICS_8~i0.990.980.970.960.950.940.930.920.910.'0.890.880.870.860.850.840.830.820.810.8NORMALIZED SUPPLY CURRENT VS.CYCLE TIME Vee =5.0V T. =25 °C-t-- r- 7~r- ._----- I/'I· - --- -- I--- .. .. - I--- .. _-- I---"-..... -- I-----I---26 30"CYCLE FREQUENCY (MHz)38 42 46 '0.:~US1.'1.151.05-- r-...NORMALIZED ACCESS TIME VS.SUPPLY VOLTAGE T. =250(;......! 0.95............ I0.'"-0.85f"i--.0.80.754.2 4.4 4.6 4.8 5.2 5.4 5.6 5.8SUPPLY VOLTAGE (V)~j~INORMALIZED SOURCE AND SINK CURRENTS VS.OUTPUT VOLTAGE VOLTAGE \Icc =5.0V T. =25 °C_.f- .f... - I---'r-;:-,.2+--1---r-......... -"'............0.'0.807...0.'0.'0.'...0.3..~---+--___ -________ +-"",,"'"''--::--l..........-_.,0'./0.1'\...'\j1.'1.91.81.7"1.3010.'~0.8~ 0.7Z0.'NORMALIZED SOURCE AND SINK CURRENTS VS.SUPPLY VOLTAGE T. =25°C/'L/'SOURCE/./' /'0.'0.'0.3 /' --OUTPUT VOLTAGE (V)SUPPLY VOLTAGE (V)NORMALIZED SOURCE AND SINK CURRENTS VS.AMBIENT TEMPERATURE V cc =5_0V20 .0'080AMBIENT TEMPERATURE ('C)8110484

MK41 H66/MK41 H67(N ,P)-20/25/35ORDERING INFORMATIONPART NUMBERMK41H67N·20MK41H67N·25MK41H67N·35MK41H66N·20MK41H66N·25MK41H66N·35MK41H67p·20MK41H67p·25MK41H67p·35MK41H66p·20MK41H66p·25MK41H66p·35ACCESS TIME PACKAGE TYPE TEMPERATURE RANGE20 ns 20 pin Plastic DIP OOC to 700C25 ns 20 pin Plastic DIP OOC to 700C35 ns 20 pin Plastic DIP OOC to 700C20 ns 20 pin Plastic DIP O°C to 700C25 ns 20 pin Plastic DIP OOC to 70°C35 ns 20 pin Plastic DIP O°C to 700C20 ns 20 pin Ceramic DIP OOC to 700C25 ns 20 pin Ceramic DIP OOC to 700C35 ns 20 pin Ceramic DIP OOC to 700C20 ns 20 pin Ceramic DIP OOC to 70°C25 ns 20 pin Ceramic DIP O°C to 700C35 ns 20 pin Ceramic DIP OOC to 700CMKNSpeed grade'--________________ Package TypeN: Plastic DIPP: Ceramic DIP'--___________________ Device family andidentification numberSGS·THOMSON'--_______________________ prefix9/10485

MK41H66/MK41H67(N,P)-20/25/3520 PIN "N" PACKAGE, PLASTIC DIPNOTES1. OVERALL LENGTH INCLUDES .010 IN.FLASH ON EITHER END OF THE PACKAGE.2. PACKAGE STANDOFF TO BE MEASUREDPER JEDEC REQUIREMENTS.3. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. WHENSOLDER LEAD FINISH IS SPECIFIED.Dim.AA1A2881CDD1EE161eALMinmmMax- 5.3340.381 -3.048 3.5560.381 0.5331.27 1.7780.203 0.30425.908 26.671.524 1.9057.62 8.2556.096 6.8582.286 2.7947.62 10.163.048 -MininchesMaxNoles- .210 2.015 - 2.120 .140.015 .021 3.050 .070.008 .012 31.020 1.050 1.060 .075.300 .325.240 .270.090 .110.300 .400.120 -20 PIN "P" PACKAGE, SIDE BRAZED CERAMIC DIPDim.MinmmMaxMininchesMaxNolesNOTES1. PACKAGE STANDOFF TO BE MEASUREDPER JEDEC REQUIREMENTS.~1~R-I'~ I~'A--4AA1A2881CDD1EE1e1eALQ1- 4.4450.508 -2.032 2.7940.381 0.5330.965 1.4470.203 0.30424.511 25.2730.635 1.3977.493 8.2557.112 7.8742.286 2.7947.366 9.2713.048 -0.127 -- .175 1.020 - 1.080 .110.015 .021 2.038 .057.008 .012 2.965 .995.025 .055.295 .325.280 .310.090 .110.290 .365.120 -.005 -2. THE MAXIMUM LIMIT SHALL BEINCREASED BY. 003 IN. WHENSOLDER LEAD FINISH IS SPECIFIED.10/10486

MK41H681MK41H69(N,P)-20/25/354K x 4 CMOS STATIC RAM• 20, 25, AND 35 ns ADDRESS ACCESS TIME• EQUAL ACCESS AND CYCLE TIMES• 20-PIN, 300 MIL PLASTIC AND CERAMIC DIP• ALL INPUTS AND OUTPUTS TIL COMPATIBLE,LOW CAPACITANCE, AND PROTECTEDAGAINST STATIC DISCHARGE• 50 pA. CMOS STANDBY CURRENT (MK41H68)• TIL STANDBY CURRENT UNAFFECTED BYADDRESS ACTIVITY (MK41H68)• HIGH SPEED CHIP SELECT (MK41H69)• JEDEC STANDARD PINOUTMK41H68 TRUTH TABLE~ WE Mode DO PowerH X Deselect High Z StandbyL L Write DIN ActiveL H Read DnllT ActiveNDIP-20(Plastic Package)PDIP-20(CeramiC Package)FIGURE 1. PIN CONNECTIONSA. 1A. 2A, 3A7 4A. 5As 6A,. 7A" 8CE 9GND 1020 Vee19 A,18 A,17 A,16 A.15 D0314 DO,13 DO,12 DO.11 WEMK41H69 TRUTH TABLE~ WE Mode DO PowerH X Deselect High Z ActiveL L Write DIN ActiveL H Read DaUT Activex = Don't CareDESCRIPTIONThe MK41H68 and MK41H69 feature fully staticoperation requiring no external clocks or timingstrobes, and equal address access and cycle times.Both require only a single +5V ± 10 percent powersupply. Both devices are fully TIL compatible.The MK41H68 has a Chip Enable power down featurewhich automatically reduces power dissipationwhen the CE pin is brought inactive (high). StandbyA. 1As 2A. 3A7 4A. 5A. 6A,. 7A" 8CS 9GND 10PIN NAMESAo -. A" - Address00 0 - D~ - Data 1/0GE - Chip Enable(MK41H68)CS - Chip Select(MK41H69)20 Vee19 A318 A,17 A,16 A.15 D0314 DO,13 DO,12 DO.11 WEWE - Write EnableGND - GroundVcc - + 5 voltsJune 19881110487

MK41 H68/MK41H69(N, P)-20/25/35power can be further reduced to microwatt levelsby raising the CE pin to the full Vcc voltage.The MK41H69 Chip Select pin provides a highspeed chip select access, allowing fast read cyclesdespite decoder delays.OPERATIONSREAD MODEThe MK41H6819 is in the Read Mode whenever WE(Write Enable) is high and CE/CS (Chip Enable/Select)is low, providing a ripple-through accessFIGURE 2. READ-READ-READ·WRITE TIMINGto data from four of 16,384 locations in the staticstorage array. The unique address specified by the12 Address Inputs defines which one of 4096 nibblesof data is to be accessed.Valid data will be available at the four Data Outputpins within tAA after the last address input signalis stable, providJ!!g that the CE/CS access time issatisfied. If CE/CS access time is not met, data accesswill be measured from the limiting parameter(tcA> rather than the address. The state of the fourData I/O pins is controlled by the CE/CS, and WEcontrol signals. The data lines may be in an indeterminatestate at tCL' but the data lines will alwayshave valid data at tAA--~-I+---I~ -----'-t-----I~-~+O---READ CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O·CsTAs70OC) (Vcc = 5.0 V ± 10 percent)MK41H6X-20SYM PARAMETER MIN MAXtRC Read Cycle Time 20tAA Address Access Time 20tCL Chip Enable to Low·Z (MK41H68) 7tCL Chip Select to Low-Z (MK41H69) 5leA Chip Enable Access Time (MK41H68) 20leA Chip Select Access Time (MK41H69) 10tRcs Read Command Setup Time 0tRCH Read Command Hold Time 0tOH Valid Data Out Hold Time 5lez Chip Enable to High-Z (MK41H68) 8tcz Chip Select to High-Z (MK41H69) 7tWEz Write Enable to High-Z 8MK41H6X-25 MK41H6X-35MIN MAX MIN MAX UNITS NOTES25 35 ns25 35 ns 17 7 ns 25 5 ns 225 35 ns 112 15 ns 10 0 ns0 0 ns5 5 ns 110 13 ns 28 10 ns 210 13 ns 22110488

MK41 H68/MK41 H69(N, P)-20/25/35WRITE MODEThe MK41H6819 is in the Write Mode whenever theWE and CE/CS inputs are in the low state. CE/CSor WE must be high during address transitions. Addressesmust be held valid throughout a write cycle.The Write b~s with the concurrence of a lowon WE and CE lCS. Therefor~ referenced tothe latter occurring edge of CEfCS, or WE.FIGURE 3. WRITE-WRITE-WRITE-READ TIMINGIf the output is enabled (CEfC"S is low), then WEwill return the outputs to high impedance withintWEZ of its falling edge. Care must be taken to avoidbus contention in this type of operation. Data-Inmust remain valid tOH after the rising edge ofCE/C"S or WE.CE/CSWEf---twC_________.I---twC------.I---Iwc----I-oo__--I.c-----I'",I.H"'_1Icw __ 1I I000·OQ3-----+ .)f-----f- VALtD IN -,\-----f:-WRITE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O°CSTAS70°C) (Vee = 5.0 V ± 10 percent)MK41H6X-20 MK41H6X-25 MK41H6X-35SYM PARAMETER MIN MAX MIN MAX MIN MAX UNITStwe Write Cycle Time 20 25 35 nstAS Address Setup Time 00 0 nstAW Address Valid to End of Write 16 20 30 nstAH Address Hold after End of Write 00 0 nstew Chip EnablefSelect to End of Write 1822 32 nstWEW Write Enable to End of Write 16 20 30 nstos Data Setup Time 1214 15 nstOH Data Hold Time 00 0 nstWEL Write Enable to Low-Z 55 5 nsNOTES23110489

MK41 H68/MK41 H69(N,P)-20/25/35FIGURE 4. DATA RETENTION TIMINGLOW Vee DATA RETENTION TIMING (MK41H68)i4----DATA RETENTION MDDE----~Vee -------"\Vee (MIN)-cr------'ov-------------LOW Vee DATA RETENTION CHARACTERISTICS(0°C

MK41H68/MK41 H69(N ,P)-20/25/35APPLICATIONThe MK41H6819 operates from a 5.0 volt supply. Itis compatible with all standard TTL families on allinputs and outputs. The device should share a solidground plane with any other devices interfaced withit, particularly TTL devices. Additionally, becausethe outputs can drive rail-ta-rail into high impedanceloads, the 41H6819 can also interface to 5 volt CMOSon all inputs and outputs. Refer to the normalizedperformance curves that follow.Since very high frequency current transients will beassociated with the operation of the MK41H68/9,power line inductance must be minimized on thecircuit board power distribution network. Power andground trace gridding or separate power planes canbe employed to reduce line inductance. Additionally,a high frequency decoupling capacitor shouldbe placed next to each RAM. The capacitor shouldbe 0.1 pF or larger.Though often times not thought of as such, thetraces on a memory board are basically unterminated,low impedance transmission lines. As suchthey are subject to signal reflections manifested asnoise, undershoots and excessive ringing. Seriestermination in close proximity to the TTL drivers canimprove driver/signal path impedance matching.While experimentation most often proves to be theonly practical approach to selection of series resistors,values in the range of 10 to 33 ohms oftenprove most suitable.ABSOWTE MAXIMUM RATINGS·Voltage on any pin relative to GND ....................................... -1.0 V to +7.0 VAmbient Operating Temperature (T A> ......................................... O°C to +70'CAmbient Storage Temperature (Plastic) .................................... -55°C to +125'CAmbient Storage Temperature (Ceramic) .................................. -65°C to +150'CTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 50 mA'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or other conditions beyond those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(O°C sT A s70°C)SYMPARAMETERMINTYPMAX UNITS NOTESVccSupply Voltage4.5 5.05.5 V 3GNDSupply Voltage0 00 VVIHLogic 1 Voltage, All Inputs2.2Vcc+1.0 V 3VILLogic 0 Voltage, All Inputs-0.30.8 V 3DC ELECTRICAL CHARACTERISTICS(O'CsT A s70°C) (Vcc = 5.0 V ± 10 percent)SYMPARAMETERMINMAX UNITS NOTESICClAverage Power Supply Current120 mA 4Icc2TTL Standby Current (MK41H68 only)8 mA 5ICC3CMOS Standby Current (MK41H68 only)50 pA 6IlLInput Leakage Current (Any Input Pin)-1+1 pA 7IOLOutput Leakage Current (Any Output Pin)-10+10 pA 8VOHOutput Logic 1 Voltage (lOUT = -4 mAl2.4V 3VOLOutput Logic 0 Voltage (lOUT = +8 mAl0.4 V 35110491

MK41H68/MK41H69(N,P)-20/25/35CAPACITANCE(TA = 25"C, f = 1.0 MHz)SYMC 1C 2PARAMETERCapacitance on input pinsCapacitance on DQ pinsTYP MAX UNI,TS NOTES4 5 pF 98 10 pF 5,9NOTES1,. Measured with load shown in Figure 6(A).2. Measured with load shown in Figure 6(8).3. All voltages referenced to GND.4. ICC1 is measured as the average AC current with VCC= VCC (max) and with the outputs open circuit. tcycle= min. duty cycle 100%.5. CE = VIH, All Other Inputs = Don't Care.6. VCC (max) -.;CE-.;VCC - 0.3 V, All Other Inputs =Don't Care. ,7. Input leakage current specificatIOns are validfor all VINsuch that 0 V

MK41 H68/MK41 H69(N ,P)-20/25/35NORMALIZED DC AND AC PERFORMANCE CHARACTERISTICSNORMALIZED SUPPLY CURRENT VS.SUPPLY VOLTAGE TA =O'C1.41.3 - II7'kiI1.2j 1.1_. V/ 1I~~V~~0.'- ~V~VtT0.8 - -7'",/"110.64.2 4.6 4.8 5.2 5.6SUPPL.Y VOLTAGE (V)J~1.181.161.14 -~1.11.081.061.041.021S 0.980.960.940.920.'0.880.860.84-601---NORMALIZED SUPPLY CURRENT VS.AMBIENT TEMPERATURE V cc ~5.0V--I'- -'",1----1---I---r-...-20 20 60 100 120AMBIENT TEMPERATURE ('C)NORMALIZED SUPPLY CURRENT VS.CYCLE TIME V cc ~5.0V T A ~25 'C0.98 O.99E=tE~EE=~0.97 -j-----j---t---i-t--0.96 --1---1-- - 1---- -1=+=j:::::j:=h~+= -- t~ ~0.95 C··· 1 .----- --j ::: -::f:::::1-1--- _..:~__-~ ~~:~ -1-,-·-+----1_+-__ +-+-+7"'1_+--+-+----11--_+---11---_--1i O~: =1 ./ f -" _._.~ ~:~ f-~- :::p~-++··_I·--I-~-_i_--·-I-·--+··-·--+~-i0.86 V --r-r- --O.BS -j--·-t7"9-t-++--+-+-++--+-+-+-+---1:::~Iz'~-l~I~-f~ggB~-l+~-;--f-!-30.82 _._0.81 r--0.826 30 38 42 50CYCL.E FREQUENCY (MHz)1.21.151.11-'" 1.05Q~~~0.950.90.850.81'\'\NORMALIZED ACCESS TIME VS.SUPPLY VOLTAGE TA ~25'C1'\SUPPLY VOLTAGE (V)5.2 5.81.20NORMALIZED ACCESS TIME VS.AMBIENT TEMPERATURE Vcc~5.0VNORMALIZED ACCESS TIME VS.OUTPUT LOADING VCC~5.0V TA~25'C~~~1.101.15~ 1.05~:5 z 1.000.950.90'"/V V"""/'"V //v V"""10 20 30 40 50 60 70 80~~u~~~2.51.50.5.....-1-"'"V.//,/400 600 800,//AMBIENT TEMPERATURE eelCAPACITANCE (pF)7110493

MK41 H68/MK41 H69(N,P)-20/25/35NORMALIZED DC AND AC PERFORMANCE CHARACTERISTICSLOGIC THRESHOLD VOLTAGE VS.AMBIENT TEMPERATURE Vee ~5.DV2.2-.,--,-,-r--r-r-,--;-r--r-r-,.-, ,-;,-;---;-,--,-,2.,+::r-4-.::l--j.-..H--+-+-+++++-+-+-H-l-l+-H-++-+--I-+i'---,+"okcH- V!, +--I-++-H-jE ,.. ......~ ' .• ++-+-+-H-l-+-+++-+=::r--k+-,,++++-i~ ,.7+-+-+-+-H-l-+-+-++++-+-+-j:::::,hJ-+-j~ ,.s+-+-+-H -+-++++-+-+-H-!-+-+-+-+~-l9I- 1.5+-+-t-H-+-+-+-+-+-t-H-+-+-+-+-!-+~~ 1.4++-+-+-H-l-+-+++++-+-+-hH--+--l,.,+-+-+-+-H-l-+-+++++-+-+-H--l-+-j:::+-.+, ---'+'---+-'---"'---1'-''+' _--+,_--+-,,_''''''-I~t_---+' ---+-----+-'-'+----''''''...,' ---+' -+-1-60 -40 -20 20 40 60 80 100 120E~~~i2.'2.22.',.•'.7,..,.•LOGIC THRESHOLD VOLTAGE VS.SUPPLY VOLTAGE T.~25'C+-H-++t-1-+-+-+-H-+ v~ H...-f+-H-j,.S ~'.3'.24.2 4.4 4.6 4.8 5.2 5.4 5.6 5.8AMBIENT TEMPERATURE ("C)SUPPL.Y VOLTAGE (V)NORMALIZED SOURCE AND SINK CURRENTS VS.OUTPUT VOLTAGE V cc ~5.DV T A ~25"C,.,--r-----;----r-----,----,----~'.2--f'''''--='t------+----+lsINK--,-,,''',-'''-,,-,,------,-l.0.90.',/0.70.'O.S0.',/0.3 .'0.2 ..0.' ...,/./\.\.\.NORMALIZED SOURCE AND SINK CURRENTS VS.SUPPLY VOLTAGE TA ~25"C..-,--,---,---,----,--,--,--..,.---,,"'+--+--+--+---j--f--t--+-....,"'1'.7+--+--+--+--!--f---lISOUACE V,.• +--+--+--+--!--f--+---,4---""'.s +---!---+--+--!--f--h-L.':,.··+--...,,.• +-+--t---+--l-,-r--,.-7' fo'_' --'-+---1~:: ~===~~===t===:j:===~===~~o':' .,,' ~=t===:j:===~"'Et$SE::"-ffit=j1 t---- ISINK0.9 ,.'/,-0.'0.70.'o.s0.'0.'...0.2 ....OUTPUT VOLTAGE (V)SUPPLY VOLTAGE (V)NORMALIZED SOURCE AND SINK CURRENTS VS.AMBIENT TEMPERATURE V cc ~5.DV1.07l'081~~~~~~l~l~1~1~~~l:~~ ~_I,,"~,::~: -'-"1.021.01 ', ••0.99'SINK-000.96.. 9.7."11"'"-'"0.950.94 "-"0.93 -••••0.920.910.90.890.8820 40AMBIENT TEMPERATURE (OC)••808/10494

MK41H68/MK41H69(N,P)-20/25/35ORDERING INFORMATIONPART NUMBERMK41H68N-20MK41H68N-25MK41H68N-35MK41H69N-20MK41H69N-25MK41H69N-35MK41H68P-20MK41H68P-25MK41H68P-35MK41H69P-20MK41H69P-25MK41H69P-35ACCESS TIME PACKAGE TYPE TEMPERATURE RANGE20 ns 20 pin Plastic DIP O°C to 70°C25 ns 20 pin Plastic DIP O°C to 70°C35 ns 20 pin Plastic DIP O°C to 70°C20 ns 20 pin Plastic DIP O°C to 70°C25 ns 20 pin Plastic DIP O°C to 70°C35 ns 20 pin Plastic DIP O°C to 70°C20 ns 20 pin Ceramic DIP O°C to 70°C25 ns 20 pin Ceramic DIP O°C to 70°C35 ns 20 pin Ceramic DIP Ooc to 700C20 ns 20 pin Ceramic DIP O°C to 70°C25 ns 20 pin Ceramic DIP O°C to 70°C35 ns 20 pin Ceramic DIP O°C to 70°CMKNSpeed grade'--_________________ Package TypeN: Plastic DIPP: Ceramic DIPL-____________________ Device family andidentification numberSGS-THOMSON'--________________________ prefix9/10495

MK41 H68/MK41 H69(N, P)-20/25/3520 PIN "N" PACKAGE, PLASTIC DIPNOTES1. OVERALL LENGTH INCLUOES .010 IN.FLASH ON EITHER END OF THE PACKAGE.2. PACKAGE STANDOFF TO BE MEASUREDPER JEOEC REQUIREMENTS.3. THE MAXIMUM LIMIT SHALL BEINCREASEO BY .003 IN. WHENSOLDER LEAD FINISH IS SPECIFIED.Dim.AAIA2881C001EElaleALMinmmMax- 5.3340.381 -3.048 3.5560.381 0.5331.27 1.7780.203 0.30425.908 26.671.524 1.9057.62 8.2556.096 6.8582.286 2.7947.62 10.163.048 -MininchesMaxNotes- .210 2.015 - 2.120 .140.015 .021 3.050 .070.008 .012 31.020 1.050 1.060 .075.300 .325.240 .270.090 .110.300 .400.120 -[a::::D]I D ~ ~Dl20 PIN "P" PACKAGE, SIDE BRAZED CERAMIC DIPNOTES--H--.1. PACKAGE STANDOFF TD BE MEASUREDPER JEDEC REQUIREMENTS.2. THE MAXIMUM ,LIMIT SHALL BEINCREASEO BY .003 IN. WHENSOLOER LEAD FINISH IS SPECIFIED.Dim.AAIA2881C001EEl01oALQlMinmmMax- 4.4450.508 -2.032 2.7940.381 0.5330.965 1.4470.203 0.30424.511 25.2730.635 1.3977.493 8.2557.112 7.8742.286 2.7947.366 9.2713.048 -0.127 -MinInchesMaxNotes- .175 1.020 - 1.080 .110.015 .021 2.038 .057.008 .012 2.965 .995.025 .055.295 .325.280 .310.090 .110.290 .365.120 -.005 -10/10496

t==' SGS-1HOMSON. ..,1. ~o©oo@rn[]J~©'iJ'OO@~O©®• 20, 25, AND 35 ns ADDRESS ACCESS TIMEMK41H79(N,P)-20/25/354K x 4 CMOS STATIC RAMPRELIMINARY DATA• EOUAL ACCESS AND CYCLE TIMES• 22-PIN, 300 MIL PLASTIC AND CERAMIC DIP• ALL INPUTS AND OUTPUTS TTL COMPATIBLE,LOW CAPACITANCE, AND PROTECTEDAGAINST STATIC DISCHARGENDIP-22(Plastic Package)PDIP-22(Ceramic Package)• TTL STANDBY CURRENT UNAFFECTED BYADDRESS ACTIVITY• SEPARATE OUTPUT ENABLE CONTROL• FLASH CLEAR FUNCTIONTRUTH TABLECE DE WE eLRModeH X X X DeselectL X L H WriteL L H H ReadL H H H ReadL X L L Flash ClearL L H L Flash ClearL H H L Flash Clearx = Don't CareDESCRIPTIONDOHigh ZDINDOUTHigh ZHigh ZLow ZHigh ZPowerStandbyActiveActiveActiveActiveActiveActiveThe MK41H79 features fully static operation requiring.noexternal clocks or timing strobes, and equaladdress access and cycle times. It requires a single+5V ± 10 percent power supply and is fully TTLcompatible.The device has a Chip Enable power down featurewhich automatically reduces power dissipationwhen the CE pin is brought inactive (high). Standbypower can be further reduced by raising the CEpin to the full Vce Voltage. An Output Enable (OE)pin provides a high speed tristate contrOl, allowingfast read/write cycles to be achieved with thecommon-I/O data bus.Flash Clear operation is provided on the MK41H79via the CLR pin, and CE active (lOW). A low appliedJune 1988PIN NAMESFIGURE 1. PIN CONNECTIONSA, 1As 2A. 3A, 4A, 5A, 6A" 7A" 8CE 9OE 10GND 11AO - A11 - AddressDOo - D0 3 - Data 1/0CLR - Flash ClearCE - Chip Enable22 vee21 A,20 A,19 A,18 Ao17 CLR16 00 015 DO,14 DO,13 DO,12 WEOE - Output- EnableWE - Write EnableGND - GroundVec - + 5 voltsto the CLR pin clears all RAM bits to zero, makingit especially useful for high speed cache and bufferstorage applications.OPERATIONSREAD MODEThe MK41H79 is in the Read Mode whenever WE(Write Enable) is high and CE (Chip Enable) is low,providing a ripple-through access to data from fourof 16,384 locations in the static storage array. Theunique address specified by the 12 Address Inputsdefines which one of 4096 nibbles of data is to beaccessed.1/10497

MK41 H79(N, P)-20/25/35Valid data will be available at the four Data Outputpins within tAA after the last address input signalis stable, providing that the CE and DE (OJ!!put Enable)access times are satisfied. If CE or OE accesstimes are not met, data access will be measuredfrom the limiting parameter (tCEA or tOEAl ratherREAD CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O°C:s;T A :s; 70 0C) (Vcc = 5.0 V ± 10 percent)than the address. The state of the four Data 110 pinsis controlled by the CE, WE and OE control signals.The data lines may be in an indeterminate state attCEL and tOEL' but the data lines will always havevalid data at tAA.MK41H79-20 MK41H79-25 MK41H79-35SYM PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStRC Read Cycle Time 20 25 35 nstAA Address Access Time 20 25 35 ns 1tCEL Chip Enable to Low-Z 7 7 7 ns 2tCEA Chip Enable Access Time 20 25 35 ns 1tOEL Output Enable to Low-Z 2 2 2 ns 2tOEA Output Enable Access Time 10 12 15 ns 1tRCS Read Command Setup Time 0 0 0 nstRCH Read Command Hold Time 0 0 0 nstOH Valid Data Out Hold Time 5 5 5 ns 1tCEz Chip Enable to High-Z 8 10 13 ns 2tOEZ Output Enable to High-Z 7 8 10 ns 2tWEZ Write Enable to High-Z 8 10 13 ns 2FIGURE 2. READ-READ-READ-WRITE TIMINGt .. ~-'-lCE I r-OE I I IWE1-1-+--'*'CHI2110498

MK41 H79(N,P)·20125/35WRITE MODEThe MK41H79 is in the Write Mode whenever theWE and aE inputs are in the low state. aE or WEmust be high during address transitions. Addressesmust be held valid throughout a write cycle. TheWrite begins with the concurrence of a low on WEand ~. Therefor!!...!As is referenced to the latteroccurring edge of CE or WE. The write ~Ie is terminatedby the earlier rising edge of CE or WE.If the output is enabled (~ and ~ low). then WEwill return the outputs to high impedance withintwez of its falling edge. Care must be taken to avoidbus contention in this type of operation. Data-Inmust remain valid tOH after the rising edge of rn:or WE.WRITE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O"C:sT A:s70"C) (Vee = 5.0 V ± 10 percent)MK41H79·20 MK41H79·25 MK41H79-35SYM PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStwc Write Cycle Time 20 25 35 nstAS Address Setup Time 0 0 0 nstAW Address Stable to End of Write 16 20 30 nstAH Address Hold after End of Write 0 0 0 nsteEw Chip Enable to End of Write 18 22 32 nstWEw Write Enable to End of Write 16 20 30 nstos Data Setup Time 12 14 15 nstOH Data Hold Time 0 0 0 nstWEL Write Enable to Low-Z 5 5 5 ns 2FIGURE 3. WRITE·WRITE·WRITE·READ TIMINGI+-------.~ ------ooJ----.~------ooJ----;{-... ----

MK41 H79(N, P)-20/25/35CLEAR CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O"CsT As70"C) (Vcc = 5.0 ± 10%)MK41H79.20MK41H79·25 MK41H79·35SYMPARAMETERMINMAXMIN MAX MIN MAX UNITS NOTEStFceFlash Clear Cycle Time4050 70 nstCECChip Enable low to End of Clear4050 10 nstClPFlash Clear low to End of Clear3848 68 nstexClear to Inputs Don't Care00 0 nstCREnd of Clear to Inputs Recognized00 0 nstcwxClear to Write Enable Dori't Care00 0 nstOHCValid Data Out Hold from Clear55 5 ns 1FLASH CLEARA Flash Clear cycle sets all 16,384 bits in the RAMto logic zero. A Clear b.!!9!ns at the concurrence ofa low on Chip Enable (CE) and Flash Clear (ClR).A Clear may be ended by a high on either CE orCLR. A low on CLR has no effect if the device isFIGURE 4. lAST READ·FlASH ClEAR·FIRST WRITE------,~'Re• ..---tFCCLAST READ ADDRESS..........JI~'exdisabled (CE high). A Clear may be executed withineither a Read or a Write cycle. Figure 4 illustratesa Clear within a Read cycle. Clears withinWrite cycles are constrained only in that Write timingparameters must be observed as soon as theFlash Clear pin returns high.00II--I+-~1-.---""0-'-___ -t.1I--- fcu,---------------"l V,. MIN1\., . Iwc_FIRST WRITE ADDRESS1---' 0./CAUTION: APPLICA.IImI OF TRANSIENT LEVELS BELOW V,H MINIMUMON THE CLR INPUT DURING NORMAL OPERATIONMAY RESULT IN PARTIAL FLASH CLEAR.4110500

MK41 H79(N, P)-20/25/35ITANDBY MODE·he MK41H79 is in Standby Mode whenever CE isleld at or above V IH •:IGURE 5. STANDBY MODEIcc 50%'------STANOBY----....JITANDBY MODEDOC:s;T A:s;7DOC) (Vce = 5.0 V ± 10 percent)MK41H79-20 MK41H79-25 MK41H79-35SYM PARAMETER MIN MAX MIN MAX MIN MAX UNITS NOTEStpoChip Enable High to PowerDowntpu Chip Enable Low to Power Up 020 25 35 ns0 0 ns~PPLICATION;he MK41H79 operates from a 5.0 volt supply. It is:ompatible with all standard TTL families on all inlutSand outputs. The device should share a solidJround plane with any other devices interfaced witht;- particularly TTL devices. Additionally, becausehe outputs can drive rail-to-rail into high impedanceoads, the 41H79 can also interface to 5 volt CMOSIn all inputs and outputs. Refer to the normalizedlerformance curves that follow.;ince very high frequency current transients will beISsociated with the operation of the MK41H79, pow­Ir line inductance must be minimized on the cir­:uit board power distribution network. Power andJround tracegridding or separate power planes canIe employed to reduce line inductance. Addition­Illy, a high frequency decoupling capacitor shouldbe placed next to each RAM. The capacitor shouldbe 0.1 pF or larger. A pull-up resistor is also recommendedfor CLR on the MK41H79. This will ensurethat any low going system noise, coupled onto theinput, does not drive CLR below V 1H minimumspecifications.Though often times not thought of as such, thetraces on a memory board are basically untermi·nated, low impedance transmission lines. As suchthey are subject to signal reflections manifested asnoise, undershoots and excessive ringing. Seriestermination in close proximity to the TTL drivers canimprove driver/signal path impedance matching.While experimentation most often proves to be theonly practical approach to selection of series resistors,values in the range of 10 to 33 ohms oftenprove most suitable.5/10501

MK41H79(N, P)-20/25/35ABSOWTE MAXIMUM RATINGS'Voltage on any pin relative to GND ....................................... -1.0 V to +7.0 VAmbient Operating Temperature (TA) ......................................... O°C to +70OCAmbient Storage Temperature (Plastic) .................................... -55OC to +125OCAmbient Storage Temperature (Ceramic) .................................. -65OC to +150OCTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 50 mA'Stresses greater than those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or other conditions beyond those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(O"CsTAS70°C)SYMPARAMETERMINTYPMAX UNITS NOTESVccSupply Voltage4.5 5.05.5 V 3GNDSupply Voltage0 00 VVIHLogic 1 Voltage, All Inputs2.2Vcc+1.0 V 3VILLogic 0 Voltage, All Inputs-0.30.8 V 3DC ELECTRICAL CHARACTERISTICS(OOCsT A s70OC) (Vcc = 5.0 V ± 10 percent)SYMIcelICC2ICC3IlLPARAMETERAverage Power Supply CurrentTIL Standby CurrentCMOS Standby CurrentInput Leakage Current (Any Input Pin)MIN-1MAX UNITS NOTES120 mA 416 mA 58 mA 6+1 pA 710L Output Leakage Current (Any Output Pin) -10 +10 pA- 8VOHVOLOutput Logic 1 Voltage (lOUT = -4 mAlOutput Logic 0 Voltage (lOUT = +8 mAlCAPACITANCE(TA = 25°C, f = 1.0 MHz)2.4 V 30.4 V 3SYMClC2PARAMETERCapacitance on input pinsCapacitance on DQ pinsTYP MAX UNITS NOTES4 5 pF 98 10 pF 9NOTES1, Measured with load shown in Figure 6(A).2. Measured with load shown in Figure 6(8).3. All voltages referenced to GND ..4. rCC1 is measured as the average AC current with V CC= VCC (max) and with the outputs open circuit. tRC ..!Be (min) is used.5. CE = VIH, all other inputs = Don't Care.6. VCC (max) 2:CE2:VCC - 0.3 V, all other inputs =Don't Care.7. Input leakage current specifications are valid for all VINsuch that 0 V

MK41 H79(N ,P)-20/25/35"C TEST CONDITIONSnput Levels ............................................................. GND to 3.0 Vrransition Times ................................................................. 5 nsnput and Output Signal Timing Reference Level ...................................... 1.5 V~mbient Temperature ....................................................... oce to 7O"C'cc ............................................................... 5.0 V ± 10 percent:IGURE 6o OUTPUT LOAD CIRCUITS+5.0 V +5.0 V470 OHMS 470 OHMS~~~Ii: 1---+------,TESTDEVICEUNDERTESTI---+~----,240 OHMS30. pFo240 OHMS5pF°GNDOND• INCWOES SCOPE AND TEST JIG.(A) (8)~ORMALIZED DC AND AC PERFORMANCE CHARACTERISTICSNORMALIZED SUPPLY CURRENT VS.SUPPLY VOLTAGE T A =o

MK41 H79(N, P)-20/25/35NORMALIZED DC AND AC PERFORMANCE CHARACTERISTICS10.990.980.970.960.95jj B.940.930.92!0.910.'S 0.890.88f-f-0.870." f-0.850.840.83 Iz'0.820 .•'0.822NORMALIZED SUPPLY CURRENT VS.CYCLE TIME V cc =5.OV T. =25"C././- f-P"" c- ----o- f-- f--26 30 34 3. 42CYCLE FREQUENCY (MHz)._- -•• ..~~!~Z1.21.15t\'\1.11.05Q.950.90.850.8NORMALIZED ACCESS TIME VS.SUPPL'( VOLTAGE T. =25"C'\.... 1---I---I---4.2 4.4 ".6 4.8 5.2 5.4 5.& 5.1SUPPLY VOLTAGE (V)NORMALIZED ACCESS TIME VS.AMBIENT TEMPERATURE V cc =5.0VNORMALIZED ACCESS TIME VS.OUTPUT LOADING V cc =5.OV T. =25 °C1.201.10J 1.15~1.05I 1.000.950.90......V- ......1/...... Vi-"i--" V-V-10 2. 30 50 60AMBIENT TEMPERATURE lOCI...... V- V"71l 80~a~!2.5 vV.....-/"1.5 ,....-V./ V"'.5200 ...8"CAPACITANCE (pF)~~§2.22.11 .•1.81.71.'LOGIC THRESHOLD VOLTAGE VS.AMBIENT TEMPERATURE Vcc =5.0V"I"--IV~... 1.S++-+-+-+-f--H--+--+--+-++++++-+-+-I~ 1.4++-+-+-+-+-H--+--+--+-++++++-+-+-I1.3+-+-+-+-+--+--HH-+-+--++++++--1-+-I:: .' ...... " ......... " .....--.~\' .. c!. cc .. c!. = .. ± ..:-;.t..O"..*,·=··~··_·HH-60 -40 -20 20 40 60 80 100 120AMBIENT TEMPeRATURE (0C)LOGIC THRESHOLD VOLTAGE VS.SUPPLY VOLTAGE T. =25'C2.3 ,-,-,-,--r-T-,-,-,--,-,-,-,----,--,--,-,-,--,-,2.2 +-H-+-t-++-t-++-+-+-+-+-+I-+-+-+~'t-l'"2.1 ++-I-+++H-+++-H V~ H...-r"'+-+-H1 .• -+-H-t-+H-t-++-V-:J..-of-"'+H-t--+-H-t--+1.8 +++-t--H-t--+..!''+-+-+-+---+--+++++-I1.7 ++-I-+-+:;;;I-""fV++--+++H-+++-H--l1.' ++V--:b--f'-H-t++--++-t-H-+++-H--l1.5 +"'!-+-t--H-+--++++--J-.HH--++++--l--l1.4 ++-+-+--HH--++++--J-.HH-++++-+-I1.3 ++--J-.+--HH--++++c:!-HH-++++-t-IV.1.2 ++-+-+--HH-+-+++:i.-c.~-t-+++::t=R1.1 +-t=t=HR4-+-+++-+-H--+-++++-+-l4.2 ".4 4.6 4.8 5.2 5.4 5.8 5.'SUPPLY VOLTAGE (V)8110504

MK41H79(N,P)-20/25/35~ORMALIZED DC AND AC PERFORMANCE CHARACTERISTICSNORMALIZED SOURCE AND SINK CURRENTS VS,OUTPUT VOLTAGE Vee =5,OV T. =25'C-F"-..... "'r--I---I---+ ,_ --+---__10.7+---+-7'-"-' +---+,,-" __ ---t~­O.6+---+-,"'-/-+---+-,-",rl-----1O.5+---+"-'/--+---+--,~~--jl.oullCE/O,+-+,/-+---+---+--+--''''\.-+OUTPUT VOLTAGE (V)NORMALIZED SOURCE AND SINK CURRENTS VS,SUPPLY VOLTAGE T A =25°C'.6 1.7tt-~ff-~· =E~i~~;3~":::t-+:;:~='!'=/:::j'-',.--,.• +--+---+--.-+---,+----+--~,.j''-,'-+-__11.3 +--+----+---+---+---+-.,.,'-/+---+---10.6 t--r--,./0.'0.3 pLI-O.,,-f-..../--c--SUPPLY VOLTAGE (V)--NORMALIZED SOURCE AND SINK CURRENTS VS,AMBIENT TEMPERATURE Vee =S.OV....0.960.930.92--'"-' .....0' f--0.89 --I-AMBIENT TEMPERATURE (OCl~2 PIN "N"PACKAGE PLASTIC DIP[::::::::~Dim.INOTES1. OVERALL LENGTH INCLUDES .010 IN.FLASH ON EITHER END OF THE PACKAGE.2. PACKAGE STANDOFF TO BE MEASUREDPEA JEDEC REQUIREMENTS3. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. WHENSOLDER LEAD FINISH IS SPECIFIED~~D1mm inchesMin Max Min MaxNotesA - 5,334 - ,210 2A1 0.381 - .015 - 2A2 3.048 3.556 .120 .140881CDD1EE1e1eAL0.3811.1430.2030,5331.7780.304.015.045.008,021.070.0123325,908 26.67 1.020 1,050 10.2547.626.0962.2867.623.1750.635 .010 .0258.255 .300 .3256.858 .240 .2702.794 .090 .1109.271 .300 ,365- .125 -9/10505

MK41H79(N,P)-20/25/3522 PIN "P"PACKAGE SIDE BRAZED CERAMIC DIP[I:::I]I 0 ~ ~o.~ 11.1 I 4-----1-H--e!!£ill.I. PACKAGE STANDOFF TO BE MEASUREDPER JEOEC REQUIREMENTS.2. THE MAXIMUM LIMIT SHALL BEINCREASED BY .003 IN. WHENSOLDER LEAO FINISH IS SPECIFIED.3. MEASURED FROM TOP OF CERAMICTO NEAREST METALLIZATION.Dim.AAIA2881CDDlEEleleAL01mminchesNotesMin Max Min Max- 4.445 - .175 10.508 - .020 - 12.032 2.794 .080 .1100.381 0.533 .015 .021 20.965 1.447 .038 .0570.203 0.304 .008 .012 227.559 28.321 1.085 1.1150.889 1.651 .035 .0657.493 8.255 .295 .3257.112 7.874 .280 .3102.286 2.794 .090 .1107.366 9.271 .290 .3653.175 - .125 -0.127 - .005 - 3ORDERING INFORMATIONPART NUMBER ACCESS TIME PACKAGE TYPE ~EMPERATURE RANGEMK41H79N-2020 ns 22 pin Plastic DIP O°C to 70°CMK41H79N-2525 ns 22 pin Plastic DIP O°C to 70°CMK41H79N-3535 ns 22 pin Plastic DIP O°C to 700eMK41H79P-2020 ns 22 pin Ceramic DIP O°C to 70°CMK41H79P-2525 ns 22 pin Ceramic DIP O°C to 70°CMK41H79P-3535 ns 22 pin Ceramic DIP O°C to 70°CMKrr;l,-----s, --~ Speed gradePackage TypeN: Plastic DIPP: Ceramic DIPL-______________________ Device family andidentification numberL-___________________________________________ SGS~HOMSONprefix10110506

MK41 H87(N)-25/35/4564K x 1 CMOS STATIC RAMADVANCE INFORMATIONI 25, 35, AND 45 NS ADDRESS ACCESS TIMEI EOUAL ACCESS AND CYCLE TIMESI 22-PIN, 300 MIL PLASTIC DIPI ALL INPUTS AND OUTPUTS TTL COMPATIBLE,LOW CAPACITANCE, AND PROTECTEDAGAINST STATIC DISCHARGEI JEDEC STANDARD PINOUT~ ", ,22 ;' I " I ' ' ,1NDIP-22(Plastic Package)IK41H87 TRUTH TABLEFIGURE 1. PIN CONNECTIONSCE WE Mode -, Q PowerH X Deselect High Z StandbyL L Write High Z ActiveL H Read Data Out Active)ESCRIPTIONrhe MK41H87 features fully static operation requirngno external clocks or timing strobes, and equallddress access and cycle times. The MK41H87 re­~uires only a single +5V ± 10 percent power sup­)Iy, and it is fully TTL compatible.rhe MK41H87 has a Chip Enable power down fea­:ure which automatically reduces power dissipationNhen the CE pin is brought inactive (high). Stand­)y Power can be further reduced by holding the Ad­:tress and CE pins at full supply rail voltages.Ao 1A, 2A. 3A. 4A. 5As 6A6 7A7 8Q 9WE 10GND 1122 vee21 A,s20 A,.19 A,.18 A,.17 A"A,o15 A914 As13 012 CE)PERATIONSPIN NAMES:tEAD MODErhe MK41H87 is in the Read Mode whenever WEWrite Enable) is high and CE (Chip Enable) is low,)roviding a ripple~through access to data from one)f 65,536 locations in the static storage array. Validlata will be available at the Data Output pin (0) wibintAA after the last address input signal is sta­)Ie, providing that the CE access time is satisfied.f CE access time is not met, data access will beneasured from the limiting parameter (teA) ratherJune 1988Ao - A'5 - AddressCE - Chip EnableWE - Write EnableGND - GroundVee - + 5 voltsD - Data In0- Data Outthan the address. The state of the Data Output pinis controlled by the CE and WE control signals. Theo may be in an indeterminate state at tel' but theo will always have valid data at tAA.1/8507

MK41H87(N)-25/35/45FIGURE 2. READ-READ-READ-WRITE TIMINGt AC toe t AC twc~ r--'I.....---tRCS---'~'''1 I+- tCA-'"~ I--'c.~'"l ~'-lItCLr---\I-- --.....--tWEW~II-I_tACH------..-! tDS '---to.oQ--1tCL-W-~tC2--":

MK41H87(N)-25/35/45WRITE MODEThe MK41H87 is in the Write Mode whenever theWE and CE inputs are in the low state. CE or WEmust be high during address transitions. Addressesmust be held valid throughout a write cycle. TheWrite begins with the concurrence of a low on WEand CE. Therefore. tAS is referenced to the latterFIGURE 3. WRITE-WRITE-WRITE-READ TIMINGoccurrl!!g edge of CE or WE. If the output is enabled(CE is low). then WE will return the output tohigh impedance within tWEZ of its falling edge.Data-In must remain valid tOH after the rising edgeof CE or WE.i---'wc---+I------I---'.c---ICEI Ioa3/8509----------- -------------~ ---------~------

MK41 H87(N)-25/35/45WRITE CYCLE TIMINGAC ELECTRICAL CHARACTERISTICS(O"CsTAs70"C) (VCC = 5.0 V ± 10 percent)MK41H87-25MK41H87-35MK41H87-45SYMPARAMETERMINMAXMIN MAX MIN MAX UNITS NOTEStwcWrite Cycle Time2535 45 nstASAddress Setup Time00 0 nstAWAddress Valid to End of Write2030 40 nstAHAddress Hold after End of Write00 0 ns /lewChip Enable to End of Write2030 40 nstWEWWrite Enable to End of Write2025 30 nstosData Setup Time2025 35 nstOHData Hold Time00 0 nstWELWrite Enable to Low-Z55 5 ns 2FIGURE 4. DATA RETENTION TIMINGLOW Vee DATA RETENTION TIMING,,---DATA RETENTION MODE----~Vee ------""""'\.Vee (MIN)- -~----...1fIII------------\'"-'-LOW Vee DATA RETENTION CHARACTERiStiCS(O"C sTAs70°C)SYMVORICCOR!cDRtRPARAMETERSV cc for Data RetentionData Retention Power Supply CurrentChip Deselection to Data Retention TimeOperation Recovery TimeMIN MAX UNIT NOTES2.0 Vee (min) V 6- 500 pA 60 - nstRC - ns418510

MK41H87(N)-25/35/45STANDBY MODEThe MK41H87 is in Standby Mode whenever CE isheld at or above VIH .FIGURE 5. STANDBY MODE TIMINGCE-~/\\'-------tpoIcc 50%'------STANDBy----..JSTANDBY MODEAC ELECTRICAL CHARACTERISTICS(O·CsT A s70OC) (Vee = 5.0 V ± 10 percent)SYM PARAMETER MINtpDChip Enable High to Power Downtpu Chip Enable Low to Power Up 0MK41H87·25 MK41H87·35 MK41H87·45MAX MIN MAX MIN MAX UNITS NOTES25 35 45 ns 100 0 ns 10APPLICATIONThe MK41H87 operates from a 5.0 volt supply. It iscompatible with all standard TIL families on all inputsand outputs. The device should share a solidground plane with any other devices interfaced withit, particularly TIL devices. Additionally, becausethe outputs can drive rail-te-rail into high impedanceloads, the 41H87 can also interface to 5 volt CMOSon all inputs and outputs.Since very high frequency current transients will beassociated with the operation of the MK41H87, powerline inductance must be minimized on the circuitboard power distribution network. Power andground trace gridding or separate power planes canbe employed to reduce line inductance. Additionally,a high frequency decoupling capacitor shouldbe placed next to each RAM. The capacitor shouldbe 0.1 pF or larger.Though often times not thought of as such, thetraces on a memory board are basically unterminated,low impedance transmission lines. As suchthey are subject to signal reflections manifested asnoise, undershoots and excessive ringing. Seriestermination in close proximity to the TIL drivers canimprove driver/signal path impedance matching.While experimentation most often proves to be theonly practical approach to selection of series resistors,values in the range of 10 to 33 ohms oftenprove most suitable.5/8511

MK41 H87(N)-25/35/45ABSOWTE MAXIMUM RATINGS·Voltage on any pin relative to GND ....................................... -1.0 V to +7.0 VAmbient Operating Temperature (TA) ......................................... OOC to + 700CAmbient Storage Temperature (Plastic) .................................... -55°C to +125OCAmbient Storage Temperature (Ceramic) .................................. , ,...65°C to +150OCTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 50 mA'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or other conditions beyond those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(O°C~TA~70OC)SYMPARAMETERMINTYP MAX UNITS NOTESVccSupply Voltage4.55.0 5.5 V 3GNDSupply Voltage00 0 VVIHLogic 1 Voltage, All Inputs2.2Vcc+1.0 V 3VILLogic 0 Voltage, All Inputs-0.30.8 V 3DC ELECTRICAL CHARACTERISTICS(O°C ~T A ~70°C) (VCC = 5.0 V ± 10 percent)SYMICClIcc2ICC3IlLPARAMETERAverage Power Supply CurrentTTL Standby CurrentCMOS Standby CurrentInput Leakage Current (Any Input Pin)MIN MAX UNITS NOTES70 mA 48 mA 51.5 mA 6-1 +1 pA 7IOL Output Leakage Current (Any Output Pin) -10 +10 pA 8VOHVOLOutput Logic 1 Voltage (lOUT = -4 mAlOutput Logic 0 Voltage (lOUT = +8 mAlCAPACITANCE(TA = 25°C, f = 1.0 MHz)2.4 V 30.4 V 3SYMClC2PARAMETERCapacitance on input pinsCapacitance on DO pinsTYP MAX UNITS NOTES4 5 pF 98 10 pF 5,9NOTES1. Measured with load shown in Figure 6(A).2. Measured with load shown in Figure 6(B).3. All voltages referenced to GND.4. ICC1 is measured as the average AC current with VCC= VCC (max) and with the outputs open circuit. tcycle= min. duty cycle 100%.5. CE = VIH, AI!.Qther Inputs = Don't Care.6. VCC(max) «CE«VCC - 0.3 VGND + 0.3 V «AO-A15« Vil (min) or VIH(max)«Ao-A15«VCC -0.3 V.All Other Inputs = Don't Care.7. Input leakage current specifications are valid for all VINsuch that 0 V

MK41 H87(N)-25/35/45AC TEST CONDITIONSInput Levels .............................................................. GND to 3.0 VTransition Times ................................................................. 5 nsInput and Output Signal Timing Reference Level ...................................... 1.5 VAmbient Temperature ....................................................... OOC to 700CV cc ............................................................... 5.0 V ± 10 percentFIGURE 6, OUTPUT LOAD CIRCUITS+5.0 V+5.0 V470 OHMS470 OHMS~:~;: ~---

MK41H87(N)-25/35/45ORDERING INFORMATIONPART NUMBER ACCESS TIME PACKAGE TYPE TEMPERATURE RANGEMK41H87N-25 25 ns 22 pin 300 mil Plastic DIP O"C to 7O"CMK41H87N-35 35 ns 22 pin 300 mil Plastic DIP O"C to 70 "CMK41H87N-45 45 ns 22 pin 300 mil Plastic DIP O"C to 70 "CMKNSpeed grade'---________________ Package TypeN: Plastic DIP'-----_________________ Device family andidentificationnumberL-__________________________________________ SGS~HOMSONprefix8/8514

.35, 45, 55, AND 70 ns ADDRESS ACCESS TIME• EQUAL ACCESS AND CYCLE TIMES• STATIC OPERATION - NO CLOCKS OR TIMINGSTROBES REQUIRED• LOW Vcc DATA RETENTION 2 VOLTS• ALL INPUTS AND OUTPUTS ARE CMOS ANDTTL COMPATIBLE• LaN PaNER OPERATION, 10pA CMOS STAND­BY CURRENT UTILIZING FULL CMOS 6-T CELL• THREE STATE OUTPUTMK48H64/MK48H65(N,P)·35/45/55nO64K (8K x 8-BIT) CMOS FAST STATIC RAMADVANCED DATA~~,~li",NDIP-28(Plastic Package),~W'PDIP-28(Ceramic Package)FIGURE 1. PIN CONNECTIONS• STANDARD 28-PIN PACKAGE IN 600 MIL PLAS­TIC OR 600 MIL CERAMIC DIP. MK48H65 AVAIL­ABLE IN 300 MIL PLASTIC DIP.N/CA12A7123282726VeeViE21IIK48H64/MK48H65 TRUTH TABLEW E1 E2 ~ MODE DQ POWERX H X X Deselect High-Z StandbyX X L X Deselect High-Z StandbyH L H H Read High-Z ActiveH L H L Read Q OUT ActiveL L H X Write DIN Active)ESCRIPTIONA6ASA4A3A2AlADDQOOQlDQ2vss45678910111213142524232221201918171615ASA9A11GAl0E1DQ7OQ6OQ5OQ4OQ3r.htl MK48H64 and MK48H65 are 65,536-bit fastItatic RAMs organized as 8K x 8 bits. ~hey areabricated using SGS-THOMSON's low power, high)erformance, CMOS technology. The devices feaurefully static operation requiring no external:Iocks or timing strobes, with equal address accesslnd cycle times. They require a single +5V ± 10lob supply, and are fully TTL compatible.rhe MK48H64 and MK48H65 have a Chip Enablelower down feature which sustains an automaticstandby mode whenever either Chip Enable goesoactive (E1 goes high or E2 goes lOw). An OutputPIN NAMESAO-A12Doo-DQ7E1, E2WGVCCVssN/CAddress InputsData Input/OutputChip EnableWrite EnableOutput Enable+5VGroundNo Connectionlune 19881/8"his is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.515

MK48H64/MK48H6S(N,P)-3S/4S/SSnoEnable (G) pin provides a high speed tristate control,allowing fast readlwrite cycles to be achievedwith the common-I/O data bus. Operational modesare determined by device control inputs W, G, E1,FIGURE 2_ FUNCTIONAL BLOCK DIAGRAMand E2, as summarized inthe truth table.The MK48H65 is a space saving 300 mil plastic DIP.The MK48H64 offers the standard 600 mil Plasticor Ceramic DIP.AA(256)••••ROWMEMORY ARRAVSELECT (256 x 256)VeeV"CeDODOINPUTDATACONTROL1/0 CIRCUITSCOWMN SELECT(32)CE_ ••••CeAAwE1E22/8516

MK48H64/MK48H65(N,P)-35/45/55noREAD CYCLE TIMINGSYMBOLSALT.tRctAASTD.tAVAVtAvaYtCEA tEtLOV1&2 tE2HQ\toEAtaLOVtCEL tEtLQX1&2 tE2HQXtOELtGLQXtCEZ tEtHQZ1 &2 tE2LQZtOEZtOHtGHQZtAXQXPARAMETERRead Cycle TimeAddress Access TimeChip Enable 1 & 2Access TimeOutput Enable AccessTimeChip Enable 1 & 2 toOutput Low-ZOutput Enable toLow-ZChip Enable 1 & 2 toHigh-ZOutput Enable toHigh-ZOutput Hold FromAddress Change48H6X-35MIN MAX3555053535352015151548H6X-45 48H6X-55 48H6X-70MIN MAX MIN MAX MIN MAX UNITS NOTES45 55 70 ns45 55 70 ns 145 55 70 ns45 55 70 ns 125 30 35 ns 15 5 5 ns5 5 5 ns 20 0 0 ns 220 25 30 ns20 25 30 ns 220 25 30 ns 25 5 5 ns 1OPERATIONSREAD MODEThe MK48H64 and MK48H65 are in the read modewhenever Write Enable rNl is high with OutputEnable (G) low, and both Chip Enables (E1 and E2)are active. This provides access to data from eightof 65,536 locations in the static memory array. Theunique address specified by the 13 Address Inputsdefines which one of the 8192 8-bit bytes is to beaccessed.FIGURE 3. READ TIMING NO. 1 (ADDRESS ACCESS)Valid data will be available at the eight Output pinswithin tAVQlL after the last stable address, providingG is low, E1 is low, and E2 is high. If Chip Enableor Output Enable access times are not met, dataaccess will be measured from the limiting parameter(tEtLQV' tE2HOV' or tGLOV) rather than the address.The state of the DQ pins is controlled by the Ef,E2, G, and Vi control signals. Data out may be indeterminateat tEtLQX, tE2HQX, and tGLax, but datalines will always be valid at tAVOV'\..-------I,VAV ---------"ADDRESS'----- t AVOV ------'DO PREVIOUS DATA DATA VALIDNOTE: Chip Enable and Output Enable are presumed valid.3/8517

MK48H64/MK48H65(N,P)-35/45/55noFIGURE 4. READ TIMING NO.2 (W = VADORE"JI'-~-----tINAv------~l_~~~~~x'--E,DQ -------------+ DATA VALIDWRITE CYCLE TIMINGSYMBOLS 48H6X-35 48H6X-45 48H6X-55 48H6X-70ALT. STD. PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTEStwc tAVAV Write Cycle Time 35 45 55 70 nstAS tAVWL Address Set-up Time 0 0 0 0 nsto Write Enable LowtAS tAVE1L Address Set-up Time 0 0 0 0 nstAVE2H to Chip EnabletAW tAVWH Address Valid to End 25 35 45 60 nsof WritetWEW tWLWH Write Pulse Width 25 35 45 60 nstAH tWHAX Address Hold Time 0 0 0 0 nsafter End of WritetCEw tE1LE1H Chip Enable to End 25 35 45 60 nstE2HE2L of WritetWR tE1HAX Write Recovery Time 0 0 0 0 nstE2LAX to Chip Disabletow tOVWH Data Valid to End of Write 25 30 30 40 nstOH tWHOX Data Hold Time 0 0 0 0 nstWEL tWHOX Write High to Output 0 0 0 0 ns 2Low-Z (Active)tWEZ tWLOZ Write Enable to Output 15 20 25 30 ns 2High-Z418518

MK48H64/MK48H65(N,P)-35/45/55noWRITE MODEThe MK48H64 and MK48H65 are in the Write modewhenever the W and"'E'f pi~ are low, with E2 high.Either Chip Enable pin or W must be inactive duringAddress transitions. The Write begins with the~ncurrence of both Chip Enables being active withW low. Therefore address setup times are referencedto Write Enable and both Chip Enables astAVWL' tAVE1L, and tAVE2H respectively, and is determinedto the latter occurring edge. The Write cycleca'lPe terminated by the earlier rising edge ofE1 or W, or the falling edge of E2.If the Output l! enabled (E1 = low, E2 = high, G= low), then W will return the outputs to high impedancewithin tWLQZ of its falling edge. Care mustbe taken to avoid bus contention in this type of operation.Data-in must be valid for tOVWH to the risi.!!9edge of Write Enable, or to the rising edge of E1or the falling edge of E2, whichever occurs first, a.!Ldremain valid tWHOX after the rising edge of E1 or W,or the falling edge of E2.FIGURE 5. WRITE TIMING NO. 1 (W CONTROL)14---------- t AVAV ---------...;ADDRESS14-------- t AVWH -------~14-------IE1LE1H------.j4-tAVE2H14----- tE2HE2l ----_~/4----- 'WLWH ----~-14--- tGHCZ ---..jDODATA IN VALID5/8519------- ---------------

MK48H64/MK48H65(N,P)-35/45/55noFIGURE 6 WRITE TIMING NO 2 (E E CONTROL)-1' -~'",,,,ADDRESS ~/ \,;----.l\ 11"--t,wWH tEtHAX ......tE1LE1HE,\ /~ /--'",,,,-IUlAk~ t AVE2H ----..E2 V \/ 1\\iiiDQ'GV'H{~IWLWHIUHE2LtOVWHDATA·IN VALIDVJ~I"-~lcLOW Vee DATA RETENTION CHARACTERISTICSSYMBOLS PARAMETERS MIN MAX UNIT NOTESVDR V cc Data Retention 2.0 Vcc

MK48H64/MK48H65(N,P)-35/45/55noABSOLUTE MAXIMUM RATINGSVoltage on any pin relative to GND ....................................... -1.0 V to +7.0 VAmbient Operating Temperature (TAJ ......................................... OOC to +70OCAmbient Storage Temperature (Plastic) .................................... -55OC to +125OCAmbient Storage Temperature (Ceramic) .................................. -65OC to +150'CTotal Device Power Dissipation .................................................... 1 WattOutput Current per Pin .......................................................... 50 rnAStresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or other conditions beyond those indicatedin the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods of time may affect reliability.RECOMMENDED DC OPERATING CONDITIONS(O'C:5T A:570'C)SYMVccGNDVIHVILPARAMETERSupply VoltageSupply VoltageLogic 1 Voltage, All InputsLogic 0 Voltage, All InputsMIN4.502.2-0.3TYP MAX UNITS NOTES5.0 5.5 V 30 0 VVcc+0.3 V 30.8 V 3DC ELECTRICAL CHARACTERISTICS(O'C:5T A:570'C) (Vcc = 5.0 V ± 10 percent)SYMPARAMETERMIN MAX UNITS NOTESIcc1 Average Power Supply Current f = min cycle 90 rnA 4Icc2 Average Power Supply Current f = 0 20 rnA 5IS81 TTL Standby Current 10 rnA 6IS82 CMOS Standby Current 10 pA 7IlL Input Leakage Current (Any Input Pin) -1 +1 pA 8IOL Output Leakage Current (Any Output Pin) -10 +10 pA 9VOHVOLOutput Logic 1 Voltage (lOUT = -4 rnA)Output Logic 0 Voltage (lOUT = +8 rnA)2.4 V 30.4 V 3CAPACITANCE(TA = 25'C, f = 1.0 MHz)SYMC1C2NOTESPARAMETERCapacitance on input pinsCapacitance on DO pins1. Measured with load shown in Figure 8(A).2. Measured with load shown in Figure 8(B).3. All voltages referenced to GND.4. ICCl is measured as the average AC current with VCC= VCC (max) and with the outputs open circuit. tAVAV= tAVAV (min) duty cycle 100%.5. ICC2 is measured with outputs open circuit.TYP MAX UNITS NOTES4 5 pF 108 10 pF 106. ~ = VIH, all other Inputs = Don't Care.7. VCC (max), and E2sVSS + 0.3 V, all other Inputs =Don't Care.8. Input leakage current specifications are valid for all VINsuch that 0 V

MK48H64/MK48H65(N,P)-35/45/55170AC TEST CONDITIONSInput Levels ............................................................. GND to 3.0 VTransition Times ................................................................. 5 nsInput and Output Signal Timing Reference Level ...................................... 1.5 VAmbient Temperature ....................................................... OOC to 700CVee ............................................................... 5.0 V ± 10 percentFIGURE 8. OUTPUT LOAD CIRCUITS+5.0 V +5.0 V470 OHMS 470 OHMSDEVICEUNDERTEST240 OHMS!H~'DEVICEUNDERTEST240 OHMS ==5pF·-=::- GND- -• INCLUDES SCOPE AND TEST JIG.(A) (8)__ GND8/8522

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Information furnished is believed to be accurate and reliable. However. SGS-THOMSON Microelectronics assumes no responsibility forthe consequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previouslysupplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systemswithout express written approval of SGS-THOMSON Microelectronics.© 1988 SGS-THOMSON Microelectronics - Printed in Italy - All rights reserved.'Z8 and Z80 are registered trademark of Zilog Inc.; Z8000 is a trademark of Zilog Inc.TM: MARGIN MODE, Mode. Zeropower. Timekeeper, BYTEWIDE. TAGRAM and BiPORT are trademarks of SGS·THOMSON Microelectronics groupSGS-THOMSON MicroelectronicsAustralia· Belgium· Brazil - Canada - China· Denmark· France· Hong Kong· India· Italy - Japan· Korea· The Netherlands· SingaporeSpain· Sweden· Switzerland· Taiwan - United Kingdom· U.S.A. - West GermanvGarzanti s,p,a, . Cernusco s.lN.Fotocomposizione . Servoffset - Milano