SRAM System Design Guidelines

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SRAM System Design GuidelinesWhat Frequencies to BypassIt is a common misconception that faster clock rates lead tothe need for higher frequency decoupling. This is only partlytrue. Because the frequencies have increased, thetechnology for high-speed memories has been driven toprovide faster rise and fall times. Therefore, a signal whosefrequency is 1 MHz will need the same decoupling as a clockrunning at 50 MHz using the same high-speed buffers. Thedifference may be that there is more timing margin affordedin the slower speed system. A rough generalization suggeststhat frequencies up to one half the fastest signal transitionrate (rise or fall) frequency need to be bypassed:f BYPASS = 0.5/Transition Rate.It should be noted that decoupling is really a four-part systemcomprising the power supply, bulk capacitors, decouplingcapacitors, and intrinsic capacitance in the board. Eachprovides decoupling in its respective frequency bands withthe power supply addressing the very low frequencies and theintrinsic board capacitance addressing the high frequencies.The difference between the capacitance is large enoughbetween each part that the large spiking effect with multiplecapacitor value interaction explained above does not occur.However, between each frequency band there will be smallpeaks. These peaks will always exist but they can be movedslightly.Generally, engineers have limited ability to alter the characteristicsof the power supply and board plane capacitance.But it is possible to vary the bulk and decoupling capacitancevalues. The goal is to have the four-part system provide a lowimpedance path (less than 1 ohm) throughout the frequencyrange. By adjusting the values of the decoupling capacitors,the small impedance peaks can be shifted to allow for thelowest impedance in the frequency ranges of concern.Decoupling Capacitors: Design RecommendationsAs we have now seen, decoupling capacitors play a huge rolein how well the SRAM performs. Along with appropriatelypicking the right value capacitor, connecting them on theboard is of extreme importance in terms of performance.Generally, a PCB should be designed to keep wiring and leadinductances as low as possible. Long, narrow PCB tracesshould be avoided because they increase inductance.Passing through a via is acceptable provided the path is lowerinductance than an alternative longer trace. The following isa list of rules when designing with decoupling capacitors.1. Use only one value capacitor for the component.2. Keep decoupling capacitors as close to the component aspossible.3. Use a minimum of one capacitor on each power pin.4. Keep capacitors on the same side of the board as thecomponent, if possible.5. Minimize the lead and wiring inductance.6. Ensure that the capacitor value meets the voltage swingrequirements, and that it provides a low-impedance pathto ground in the intended frequency range of the application.PCB Layout ConsiderationsThe PCB provides two significant functions in an electricaldesign: mechanical locations for the components that resideon the board, and connectivity between components. Theseconnections play an important role in providing a solidpathway to the power system and ensuring the highestdegree of signal integrity.The traces and planes that comprise a printed circuit boardcan be separated into two categories. There are pathways forthe power source and there are traces required to carry theactual signals. This section of the application note willexamine how both of these directly affect system integrity.Power and Ground PlanesPower planes are large sheets of a conductive material thattypically reside on entire PCB layers. They provide fourprimary functions to the circuit. They are:1. a low-impedance path for power from its source to thecomponents on the PCB.2. a physical channel to vent and move heat from the components.3. electrostatic shielding between the electromagnetic fieldsof signal traces that run on both sides of the planes.4. a sheet capacitance for the ground plane that exists onother layers of the PCB. This in turn provides additional ACbypassing within the power circuitry of the PCB.The primary functionality of a power plane is to reduce theresistance that causes a voltage drop between componentand power source. The thickest power plane available willprovide the best results. For example, using a two-ouncecopper power plane instead of a one-ounce will cut in half anypoint-to-point path resistance. It can be thought of as havingtwo resistors (and inductors) in parallel. The increased planethickness reduces both the DC resistance and AC inductancedrops. The drop in DC resistance allows the power supply toreach the component cleanly, while the reduction in AC inductanceprovides a low-impedance path for signal returncurrents.As a secondary benefit, the thicker plane also increases theability to sink heat out of the component. The bond wires andlead frames are a major thermal path in non-heat-sinkedcomponents.The planes also aid in the reduction of electromagnetic interference(EMI). They provide a lower-impedance path acrosswhich the EMI develops and a larger faraday shield to shortout these radiated fields.The sheet capacitance that the power plane provides isproportional to its size, its distance from the ground plane,and the dielectric constant of the material between them. Ithas the benefit of providing bypass capacitance, particularlyat the high frequencies. While it is far from being sufficient toprovide all of the bypassing needs of a high-speed logicdesign, it should be utilized to its maximum. The capacitanceof the planes can be calculated by the following equation:4
SRAM System Design GuidelinesC = 0.225E R ([( N–1) × A] ⁄ t)where:E R = The relative dielectric constantN = Number of platesA = Area of one side of one plate in square inchest = Thickness (separation of plates) in inches. Eq. 5For example, using a 10-inch by 10-inch FR-4 board with anE R of 4.1 and 0.005-inch separation between the power andground plane, the capacitance is calculated asC = 0.225( 4.1) ([( 2–1) × 100] ⁄ 0.005) = 18,450pF.Eq. 6This is equivalent to 184 pF per square inch. Table 1 showsthe dielectric constants for several common materials used inPCB design today. It is always advisable to consult your fabricatorfor the precise ER value, since different epoxies areused when constructing a PCB. Dielectric constants of PCBsalso change with frequency, as shown in Table 1.Table 1. Dielectric ConstantsMaterialE R@ 1 MHz @ 300 MHzFR-4, Tetra Functional 4.2 – 4.6 4.0 – 4.3FR-4, High-grade Multifunctional 4.2 – 4.6 4.1 – 4.4Polyimide 4.2 – 4.6 4.1 – 4.3GETEK 3.9 – 4.1 3.9 – 4.0BT 3.6 – 4.1 3.55 – 4.0CE 3.6 – 4.0 3.6 – 4.0ViasVias are commonly used to connect the power plane to thepower traces that ultimately attach to the power pins of thecomponents. They can also have an impact on the powersignal quality.First, vias produce a higher resistance than a copper trace.This is due to the material typically used in the fabrication ofthe via, which is plated granular copper. The resistance of avia changes based on the thickness of the copper that isplated in the via hole. Therefore, larger vias have a lower DCresistance and hence develop less of a DC voltage drop forany given current.Vias also add inductance to the power trace. This inductancecauses high-frequency noise that is present on the powerplane to stay on the plane (which is good), but it also isolatesthe capacitance effect of the power plane from the componentson the other ends of the vias. Filling vias with solder,using heavy plating, enlarging their size and using multiplevias per power connection are the preferred methods oflowering both the resistive and inductive parasitic effects theyhave on power connections.Power TracesSimilar to vias, a trace also has some amount of resistance,capacitance, and inductance. The overall resistance must bekept to a minimum to avoid voltage drop on the trace. For thepower plane to reach the power trace and ultimately thecomponent, a via is also required.If connections to the device are made in correct sequence,the resistance and inductance of the trace and via will isolatethe component’s noise from passing into the power plane.This effect increases as the frequency of the noise rises. Toachieve this isolation, the power trace must pass from the viato the decoupling capacitors pad and then to the component.This order is important to create an island of protected tracebetween the decoupling capacitor and the component.It is important to highlight that the trace between componentand bypass capacitor be as short as possible. As we havementioned, the goal is to keep the inductance between thedevices to a minimum. A short, wide trace will produce betterresults than a long, narrow trace.Signal Return PathsThe power planes play a key role in the return currents ofhigh-speed digital signals. At very slow speeds, the returncurrent follows the path of least resistance. At higher speeds,however, the return currents follow the path of least inductance.This can be on either power or ground plane, directlybelow the signal trace. Normally, the return path is on theground plane on standard PCB designs. When the returncurrent reaches the driving component, the decouplingcapacitors provide the bridge to the proper voltage plane.In order to maintain good signal integrity and to minimizecrosstalk, a clean, unobstructed return path needs to beprovided. For example, if a return signal encounters a 5-ohmtrace within the ground plane, the integrity of the normalsignal on the 50-ohm trace can be compromised.There are a few simple rules to follow for planes. First, itshould be as continuous as possible. By placing excessiveclearances around holes that pass through, it may make fabricationeasier but it can cause the return current to travelthrough a non-optimal path. The effect of the clearance holesshould be analyzed. Second, cutouts in the ground planemust be avoided. Similar to the clearance holes for the vias,a ground plane cutout will force the return path current aroundthe cutout if the signal trace crosses above the cutout. Thiswill increase the inductance of the path and decrease the risetime of the digital signal on the trace. It will also increase thepotential for crosstalk.CrosstalkCrosstalk can exist between traces on a PCB. If this occurson a memory signal with sufficiently strong amplitude, a falsetrigger can occur. Crosstalk should therefore be minimized inthe design.As a signal travels through a trace, it creates a magnetic field.It also reacts to other magnetic fields within its path. Thesemagnetic fields have adverse effects on digital signals sincethey create unwanted noise on other signals. This effect isknown as crosstalk. The voltages that external fields causeare proportional to the strength of the external fields and thelength of the trace that is exposed to the field. Often, the tracethat causes the crosstalk is termed the “source” or“aggressor,” and the trace that is affected first is called the“victim.”Crosstalk between traces is a function of both mutual inductanceand mutual capacitance. A model of inductance andcapacitance between traces is shown in Figure 6. Itsmagnitude is proportional to the distance from the sourcetrace, the speed of the signal edge rate, and the impedanceof the victim trace. In digital systems, crosstalk caused bymutual inductance is typically equal to or larger than thecrosstalk associated with mutual capacitance.5
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