SRAM System Design Guidelines

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SourceTraceLInductiveCoupling(L M )CapacitiveCoupling(C M )VictimTraceLFigure 6. Mutual Coupling Between TracesTo illustrate the effects of spacing, the mutual inductance L Mcan be calculated with the following equation:LLM = -----------------------⎛ s1 + --⎝ ⎝ ⎛ h⎠⎞2 ⎞⎠where:L = Inductance of the wires = separation between the wiresh = height above the plane. Eq. 7Figure 8. Crosstalk versus Impedance and SpacingThis shows that moving the traces away (value s) from eachother or by moving the traces closer (value h) to the plane,the mutual inductance is reduced by the square of the charge.And, since crosstalk is proportional to the mutual inductance,the magnitude of the crosstalk is also reduced. Figure 7below illustrates this model.STrace AWHGround PlaneFigure 7. Trace and Ground PlanesTrace BThe mutual capacitance C M injects current I M into the victimtrace and can be calculated as:dVsI M = C M × ---------dt. Eq. 8where:dVs = Vs is the source voltageFigure 8 illustrates the effects of trace impedance oncrosstalk coupling. The higher the impedance of the victimtrace, the more susceptible it is to noise from crosstalk.Figure 9 shows a similar effect but with varying the width ofthe trace line. Wider traces produce less crosstalk coupling.Therefore, minimum coupling is created with maximumspacing, maximum trace widths, and minimum impedance.To minimize the effects of magnetic field coupling, three basicrules should be followed.First, separate the traces with more distance. The effect thatis seen is directly proportional to the square of the distance ofthe elements and therefore doubling the distance will reducethe coupling by a factor of four.Figure 9. Crosstalk versus Width and SpacingThe second method of decreasing the coupling is to shield thetarget trace. Either routing it on another layer or placingprotective guard traces between the two does this. In this waythe magnetic lines will have a portion of their energydeveloped in the protective traces, usually at groundpotential, and the field that cuts across the trace beingshielded is less.A third way to reduce the impact of crosstalk is to use differentialsignaling. This type of signal rejects noise fromcrosstalk if both true and complement signals are equallyaffected. This is commonly called common-mode noiserejection. However, if the crosstalk affects one trace of thedifferential pair and not the other, noise coupling can be afactor.LayersIn order to keep noise at a minimum and to achieve the bestin signal integrity, control of the PCB layers is required.As was mentioned above, spacing power and ground planesclose together gains additional bypassing capacitance. Ofmore importance is the creation of a reference plane thatprovides constant trace impedance. The reference plane isusually the ground plane. The thickness of the substratebetween controlled impedance traces and the ground planemust be selected to be both manufacturable and able to keepthe desired characteristic trace impedance within acceptablelimits. As the spacing of layers decreases, the ability to holdtight, repeatable spacing value decreases. A 1-mil variationon a 10-mil spacing is 10% and on a 20-mil spacing it is only5%. You should consult with your manufacturer on the tolerances.
SRAM System Design GuidelinesWhen power planes are correctly bypassed, they are at thesame AC potential as ground planes. Therefore, they can beused as a reference for controlled impedance traces. Usingboth power and ground planes, however, is unwise becausethe transition between the two has a high potential of causingnoticeable impedance discontinuities in trace impedance,which is a source of unwanted reflections. (This applicationnote will explain reflections in more detail in the next section.)Vias in TracesWhen routing a trace, the signal should remain on the samesignal plan. Using a via to route to another plane diminishessignal quality. Vias should therefore be avoided as much aspossible. If vias have to be used in a high-speed design, thefollowing guidelines should be considered.1. Make vias as large as possible (more area equals lessinductance and resistance).2. Plate external layers with the maximum thickness ofcopper during fabrication.3. Plating of filling the via holes solid.+ _Distance(Y-X)XYStep Voltage: VAt point X, the step is still ofsize V, but is now delayedAt point Y, the step isdelayed even furtherReflections and TerminationsAnother problem that arises in digital signal systems involvesreflections due to poorly terminated transmission lines. Thissection will discuss a few important points to remember whendesigning with long wiring networks. For a full discussion ontransmission lines, please refer to the Terminations applicationnote available on the Cypress web site.What is a Reflection?A reflection is an unwanted pulse on a transmission line thatis a result of an unmatched source or load impedance. Thetransmission line has an intrinsic value called its characteristicimpedance. A reflection back toward the driver sourcecan occur if the line’s load and characteristic impedances arenot matched, and a second reflection back toward the loadcan occur if the source and characteristic impedances arealso not matched.Why do Reflections Occur?Reflections occur because of impedance mismatches thatcause a disproportion of energy transfer. If the line is ideal,and the source impedance Z S equals the load impedance Z L ,then half the energy in the propagating signal will be lost inthe source impedance, and the other half in the loadimpedance (since the ideal line is lossless). However, if theload resistor at the end of the line is larger than the line’scharacteristic impedance, there will be extra energy availablethat is “reflected” back toward the source. That is, there isanother signal that propagates down the line that “bounces”off the load if there is an impedance mismatch.Characteristic ImpedanceThe most important variable of any line is its characteristic, orinput, impedance. This is the impedance seen looking into thetwo left-hand terminals of the line.t 0 t 1Figure 10. Voltage Step Input to an Ideal LineFigure 10 below illustrates how a digital pulse propagatesdown an ideal line. The pulse is set onto the beginning of theline by the source at time t = 0. This pulse is then transferreddown the line without being distorted or attenuated while it isdelayed in time according to the line’s propagation delay. Atpoint X, the voltage on the line is low, until time t 0 at whichtime the signal passes point X on the line, and we can seethat the pulse drives the voltage up to the high level. A similarsituation exists for point Y, except that the signal stays lowlonger while it waits for the pulse to propagate down the line.We can find the characteristic impedance of this line byfinding the amount of current it takes to impress the stepvoltage on a given length of the line, in this case betweenarbitrary points Y and X.The capacitance of the length of line between points X and Yis given as:CC xy = ⎛----⎞×( Y–X)⎝in·⎠. Eq. 9The total additional charge necessary to charge the capacitancebetween these points is equal to:CCharge= C xy= ⎛----⎞ ⎝in·⎠ ( Y–X)V. Eq. 10The time interval (in seconds) in which during which Cxy mustbe charged is equal to the separation of the two points timesthe propagation delay in seconds per unit length:T = ( Y–X)⎛----L⎞⎛----C⎞⎝in·⎠⎝in·⎠. Eq. 117
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