Synthesis with Process Construct – Part 1

VHDLModeling Behaviorfrom Synthesis Perspective-Part A -EL 310Erkay SavaşSabancı University1

Motivation• Synthesis of VHDL models with processconstruct.• Processes provide powerful modeling abstractionfor simulation purposes.– modeling complex digital system behavior that cannotbe captured with only CSA statements.• Increasing the level of modeling abstractionmakes hardware inference process harder.– More than one hardware implementation is possible– Inference process has more work to do. Relationshipbetween the language constructs and the real systemsis no longer explicit.– Simple coding guidelines in order to ease the synthesiscompiler’s task.2

Synthesis with Processes• Process construct models have similarities tohigh-level programming languages– sequential style of high-level programming languagesmay lead to excessive logic and often long signalpaths.• Good rule of thumb:– Avoid long processes– promote concurrency within models through the useof multiple processes and CSA statements.– After all, processes are concurrent to otherprocesses and to CSA statements.3

Recall• Combinational logic– The value of an output signal is defined for everycombination of values of input signals– “Previous” values do not have to be remembered.– Make sure that every time a process is executed,each output should be assigned a value.• Sequential logic– The values of an output signal may depend on“previous” values stored in the circuit– if-then-else constructs leads to a latch elementif else branch does not assign a value to one of theoutput signals– Next issue: will edge-sensitive flip-flop or latch beinferred?– wait until (falling_edge(clk));4

One Old Examplelibrary IEEE;use IEEE.std_logic_1164.all;entity sig_var isport(x,y,z: in std_logic;res1, res2: out std_logic);end entity sig_var;architecture behavioral of sig_var issignal sig_s1, sig_s2: std_logic;beginproc1:process(x,y,z) is –- process 1 using variablesvariable var_s1, var_s2:std_logic;beginvar_s1 := x and y;var_s2 := var_s1 xor z;res1

Simulation Results6

Example: The Synthesized Logicres1xyres2z• Two processes result in identical logic for res1 andres2.• Both circuit are combinational• combinational logic is a natural result of using“variables” that are assigned immediately with valuesevaluated at the RHS of assignment statements.7

Synplify Pro RTL Viewres1 = res2 = z + (xy)’8

Example: The Synthesized Logic• Recall that– the values of sig_s1 and sig_s2 used when theprocess proc2 is executed are the ones when theprocess is invoked,– Not the values are newly evaluated within theprocedure– This would cause inference of storage elements.• However, compilers generally optimize thissequence to produce combinational logic.– Thus, signals and variables behave identically withrespect to the synthesis in this case.– Dependency in the sequential execution of signalswill increase the critical path.9

Sensitivity List Mismatch• The signal sig_s1 is not in the sensitivity list.– Therefore, an event on it (caused by anotherprocess perhaps) will not lead to the execution ofprocess proc2.– However, an event on sig_s1 will cause the recomputationof the output values in the synthesizedcircuit.• Simulation semantics may not match thebehavior of the synthesized circuit.10

Data Dependency• Independent of whether variables and signalsare used, process statements introduce a datadependency between the process statements• s1

Synthesis of Conditional Statements• If-Then-Else and If-Then-Elsif statements– All Boolean valued expressions are evaluatedsequentially until the first true expression isencountered.library IEEE;use IEEE.std_logic_1164.all;entity inf_latch isport(sel,x,y,z: in std_logic;w: out std_logic);end entity inf_latch;architecture behavioral of inf_latch isvariable s1, s2:std_logic;beginprocess(x,y,z,sel) isbeginif (sel = ‘1’) thens1 := x and z;s2 := s1 xor y;w

Alternative to Avoid Latches• Assign a default value to the signal prior tothe if statementlibrary IEEE;use IEEE.std_logic_1164.all;entity inf_latch isport(sel,x,y,z: in std_logic;w: out std_logic);end entity inf_latch;architecture behavioral of inf_latch isvariable s1, s2:std_logic;beginprocess(x,y,z,sel) isbeginw

Avoid Latches by Default Valueselxzys1s2if sel = ‘0’ the w gets ‘0’w15

Efficiency• Avoiding unnecessary latches is one aspect ofeffective design for combinational circuit synthesis• Efficiency in terms of speed and/or size is the other.library IEEE;use IEEE.std_logic_1164.all;entity inference isport(sel,x,y,z: in std_logic;w: out std_logic);end entity inference;architecture behavioral of inference isvariable s1, s2:std_logic;beginprocess(x,y,z,sel) isbeginif (sel = ‘1’) thenw

Example: Efficiencylogic forthen partxy2-to-1 MUXlogic forelse partwzsel• The general principle:• combinational logic is generated for each branch of anif-then-else construct.• A multiplexor is generated to select the outcome17

More Efficient Design - 1• a small rearrangement will simplify the designlibrary IEEE;use IEEE.std_logic_1164.all;entity inference isport(sel,x,y,z: in std_logic;w: out std_logic);end entity inference;architecture behavioral of inference isbeginprocess(x,y,z,sel) isvariable right: std_logic;beginif (sel = ‘1’) thenright := y;elseright := z;end if;w

More Efficient Design - 2xwyselz• Coding styles help us to control how much hardware isgenerated.• Golden rule: move complex or hardware intensiveoperations that are replicated in then and elsebranches out of the if-then-else statement.19

Multiple Levels of Nestinglibrary IEEE;use IEEE.std_logic_1164.all;entity nested isport(sel1, sel2, sel3, x,y,z: in std_logic;res: out std_logic);end entity nested;architecture behavioral of nested isbeginprocess(x, y, z, sel1, sel2, sel3) isbeginif (sel1 = ‘1’) thenres

Example: Multiple Levels of Nestingsel30 if sel1 = sel2 = sel3 = 0xyxysel1zy ⊕ zELressel1’ sel2xyx + ysel1sel2(x+ y) sel1’ sel2’• Priority logic is implemented.• What is the highest priority?21

Nested If Statementslibrary IEEE;use IEEE.std_logic_1164.all;entity nested_ifs isport(sel0, sel1, x,y,z: in std_logic;res: out std_logic);end entity nested_ifs;architecture behavioral of nested_ifs isbeginprocess(x, y, z, sel0, sel1) isbeginif (sel0 = '0') thenif (sel1 = '1') thenres

Nested If Statements• Latch is inferred because of the outer if-then-elsestatement23

Nested If Statementslibrary IEEE;use IEEE.std_logic_1164.all;entity nested_ifs isport(sel0, sel1, x,y,z: in std_logic;res: out std_logic);end entity nested_ifs;architecture behavioral of nested_ifs isbeginprocess(x, y, z, sel0, sel1) isbeginif (sel0 = '0') thenif (sel1 = '1') thenres

Nested If StatementsRemove the inner if-then-else from the outer onein order to infer combinational logic25

Don’t Cares in Conditional Expressionslibrary IEEE;use IEEE.std_logic_1164.all;entity sig_var isport(sel: in std_logic_vector(1 downto 0);x,y,z: in std_logic;w: out std_logic);end entity sig_var;architecture behavioral of sig_var isbeginprocess(x, y, z) isbeginif (sel = ‘-0’) thenw

Don’t Cares in Conditional ExpressionsSynthesis compiler generates a logic in which then branchis never taken27

Case Statement• Case statement is similar to if-then-elseconstructs– but identifies mutually exclusive blocks of code.– Only one branch of a case statement can be true– and collectively all branches cover all possible valuesof select expression.–The others clause helps cover all possible valuesof select expression– Selecting one of the several possible alternativessuggests that a multiplexor is inferred.– Select expression provides the control signals formultiplexor.28

Case Statement: Examplelibrary IEEE;use IEEE.std_logic_1164.all;entity case_ex isport(sel: in integer range 0 to 3;x,y,z: in std_logic;res: out std_logic);end entity case_ex;architecture behavioral of case_ex isbeginprocess(x, y, z, sel) isbegincase sel iswhen 0 => res res res res

Case Statement: Examplex and ywhen sel=0y xor zwhen sel=1zx nand zwhen sel=2resxysel(0)sel(1)(x nor y)(x nor y) when sel=3sel: in integer range 0 to 3; is mapped to a two-bit signal30

Latch Inference from Case Statementlibrary IEEE;use IEEE.std_logic_1164.all;entity case_ex isport(sel: in integer range 0 to 3;x,y,z: in std_logic;res: out std_logic);end entity case_ex;architecture behavioral of case_ex isbeginprocess(x, y, z, sel) isbegincase sel iswhen 0 => res res res null; -- in this case the value of res-- remains unalteredend case;end process;end architecture;31

Latch Inference from Case Statementsel[1:0]1 when sel = 0x and yz xor yx zyx nand zlatchdon’t enable thelatch when sel≠0,1,21 when sel(0) = 11 when sel(1) = 132

Avoiding Latch Using Default Valueentity case_ex isport(sel: in integer range 0 to 3;x,y,z: in std_logic;res: out std_logic);end entity case_ex;architecture behavioral of case_ex isbeginprocess(x, y, z, sel) isbeginres res res res null;end case;end process;end architecture;Any case statement has an equivalent if-then-elsif form.Question: what is the difference between the two?33

Using don’t cares in Case Statementsentity case_ex isport(sel: in integer range 0 to 3;x,y,z: in std_logic;res: out std_logic);end entity case_ex;architecture behavioral of case_ex isbeginprocess(x, y, z, sel) isbegincase sel iswhen 0 => res res res res res

Using don’t cares in Case Statementscircuit output res is not defined for sel= 335

• For-LoopLoop Statements– Most common construct for loops supported bysynthesis compilers– At compile-time, it is possible to know when theloops ends; the logic is inferred accordingly.– With while-loops, when the loop ends may be datadependent.– Therefore, a state machine controller issynthesized to cycle datapath a data-dependentnumber of times.– For-loops, on the other hand, is easy to synthesize.since the number of iterations is known.36

For Loops• Example:– for N in 3 downto 1 loopshift_reg(N)

Loop Unrolling: Examplelibrary IEEE;use IEEE.std_logic_1164.all;entity iteration isport(clk, reset, data: in std_logic;res: out std_logic_vector(3 downto 0));end entity iteration;architecture behavioral of iteration issignal shift_reg: std_logic_vector(3 downto 0);beginprocess(clk, reset, data) isbeginif(rising_edge(clk)) thenif(reset = ‘1’) then res

Loop Unrolling: Example• Latch inference– Because of if(rising_edge(clk)) then with no else, astorage element will be inferred.– Bu due to the call to function rising_edge() a flip-flopinstead of a latch is inferred.clkDRQresDRQresDRQresdataDQDQDQDQDE E E E RQresreset39

While Loopentity iteration isport(clk, reset, data: in std_logic;res: out std_logic_vector(3 downto 0))end entity iteration;architecture behavioral of iteration issignal shift_reg: std_logic_vector(3 downto 0);beginprocess(clk, reset, data) isvariable N: integer;beginif(rising_edge(clk)) thenif(reset = '1') then res 0 loopshift_reg(N)

sum := 1; j := 0;L2: loop;j := j+21;sum := sum *10;exit when sum > 100;end loop L2;Exit Statement–The exit statement can be used only inside a loop.– It causes execution to jump out of the innermost loop or the loopwhose label is specified.– exit [loop-label][when condition];sum := 1; j := 0;L3: loop;j := j+21;sum := sum *10;if sum > 100 thenexit L3;end if;end loop L3;41

Next Statement• A sequential statement that can be used only inside aloop.• Syntax: next [loop-label][when condition];• It results in skipping the remaining statements in thecurrent iteration of the loop;• execution resumes with the first statement in thenext iteration of this loop, if one exists.for j in 10 downto 5 loopif sum < total_sum thensum := sum + 2;elsif sum = total_sum thennext;elsenull;end if;k := k + 1;end loop;42

Next Statement• The next statement can also cause an innerloop to be exited.L4: for k in 10 downto 1 loop-- statements section 1L5: loop-- statements section 2next L4 when WR_DONE = ‘1’;-- statements section 3end loop L5;-- statements section 4end loop L4;• When WR_DONE = ‘1’ becomes true, statementssection 3 and 4 are skipped, and execution jumps to thebeginning of the next iteration of loop L4.• Notice that loop L5 is terminated by next statement.43

Loops• Some synthesis compilers forces the type ofthe loop index to integers or only a subsets ofarray types.• The dependencies across iterations of a loopwill lead to long signal paths.• Example:– reg(0)

Loops: Examplelibrary IEEE;use IEEE.std_logic_1164.all;entity iteration isport(data: in std_logic_vector(3 downto 0);res: out std_logic_vector(3 downto 0));end entity iteration;architecture behavioral of iteration issignal reg: std_logic_vector(3 downto 0);beginforl: process(data) isbeginreg(0)

Loops: Example46

Sensitivity List in Synthesis• Process is executed when there is an event onany signal in the sensitivity list.– When a signal is not in the sensitivity list, an eventon this signal does not cause the execution of theprocess.– However, when the VHDL code is synthesized in toa logic circuit, a change on any signal will lead to there-calculation of the other signals that depends onthis signal.– Therefore, simulation results after synthesis maynot match exactly to those before the synthesis.– Lesson: Include all signals of process in thesensitivity list when performing simulations.47

Variables• Variables are language objects that is useful indescribing the behavior of the circuit.– They are typically used to transfer values betweenstatements in a process– Compiler may collapse variable assignmentstatements and eliminate some of them.– When it is not possible to do so, then a variable issynthesized to a wire connecting gates.48

Inferring Latches...L1: if(s1 = ‘1’) then...L2: if(s2 = ‘1’) thenAout

Buffer and Inout Entity Modes• A signal can serve as both a driver and as anoutput signal– Aout

Inference Using Signals vs. Variableslibrary IEEE;use IEEE.std_logic_1164.all;entity sigvar isport(sel: in std_logic; x, y, z: in std_logic; v: out std_logic);end entity sigvar;architecture behavioral of sigvar issignal sig_s1: std_logic;beginprocess(x, y, z, sel) isvariable var_s1: std_logic;beginL1: if(sel = '1') thensig_s1

Inference Using Signals vs. VariablesSynthesis using Synopsys52

Inference Using Signals vs. VariablesL2var_s1sig_s1Synthesis using Synplify Pro53

Latch Inference for Variableslibrary IEEE;use IEEE.std_logic_1164.all;entity sigvar isport(clk, x, y: in std_logic;res: out std_logic);end entity sigvar;architecture behavioral of sigvar isbeginprocessvariable var_s1, var_s2: std_logic;beginwait until(rising_edge(clk));var_s1 := x nand var_s2;var_s2 := var_s1 xor y;res

• Signal res:Latch Inference for Variables– wait until(rising_edge(clk)); statement causes aflip-flop.– When there is no rising_edge of the clock, thesignal res should retain its value.• Variable var_s2:–variablevar_s2 is used before it is defined.– Variables retain their values across processinvocations.– Therefore, a flip-flop is inferred when a variable isused before it is defined.55

Latch Inference for Variables56

Latch and Flip-Flop Inference• if, case, wait, conditional and selected signalassignment statements can be used to inferlatches.– For example, “if (sel = ‘1’) then“ will lead to theinference of a latch.• if(rising_edge(clk)) then is used to inferan edge-triggered flip-flop.– if(clk’event and clk = ‘1’) then may notdetect a transition from ‘0’ to ‘1’.– The attribute clk’last_value may be useful in detecting0-to-1 transition.– However, it cannot be used in synthesis.– Use functions rising_edge() or falling_edge().– The Xilinx XC4000 series FPGAs support both edgetriggeredand level-sensitive devices.57

Flip-Flops with Asynchronous Resetlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;entity counter_async isport(clk, reset: in std_logic; res: out unsigned(3 downto 0));end entity counter_async;architecture behavioral of counter_async isbeginprocess(clk, reset) isvariable var_count: unsigned(3 downto 0);beginif(reset='1') then res

Flip-Flops with Asynchronous ResetsAsynchronous clear and set signal can be synthesized onlyif they exist in the target library.59

Flip-Flops with Synchronous Resetslibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;entity counter_async isport(clk, reset: in std_logic; res: out unsigned(3 downto 0));end entity counter_async;architecture behavioral of counter_async isbeginprocess(clk, reset) isvariable var_count: unsigned(3 downto 0);beginif (rising_edge(clk)) thenif(reset='1') thenres

Flip-Flops with Synchronous Resets61

Example in the Textbooklibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;entity counter_async isport(clk, reset: in std_logic; res: out unsigned(3 downto 0));end entity counter_async;architecture behavioral of counter_async isbeginprocess(clk, reset) isvariable var_count: unsigned(3 downto 0);beginif (rising_edge(clk)) thenif(reset='1') thenres

Example in the TextbookWhat is the reason for this difference?63