Advanced Features in RadSafe technology - Microelectronics - ESA

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PLL (phase locked loop) or DLL(delay locked loop) for clockmultiplication and de-skewing. The useof all-digital delay locked loop(ADDLL), with expanded tuningrange, and low jitter, enables usefulinternal clock frequency of >400MHz.Since the control data is stored indigital flip-flops, the operation of theseDLLs can start and stop at any time,with no latency for re-locking.High performance processorsrequires advanced and high capacityexternal memories. For interfacingwith DDR2 memories, and completeDDR2 interface is under development.The use of multi-IO buffers will enabledual use of the buffers, for otherapplications as well.Transferring high data rate withlimited number of signals and packagepins requires the use of SerDes. TheRadSafe TM SerDes is currently underdevelopment, which exceeds 2.5Gbps,is compatible with several standardinterfacing protocols, includingSpaceFiber. It is immune to allradiation effects. To enable the use ofhigh inductance packages, it includesconfigurable equalizers.The DDR2 PHY requires SSTL18bi-directional and differential unidirectionalbuffers, powered byisolated 1.8V supply. These buffersincludes switchable on die termination(ODT) with adjustable impedance of50/75/150Ω. The reference voltage forthe resistive termination, VTT, isdriven by external pin, typicallyconnected to 1.2V. This ODTtechnique consumes much less DCpower than the conventional technique,where the termination is implementedby resistors to VDD and GND (Figure1). Same ODT can be used for SSTL18and LVDS, enabling wider range ofimpedances, that enables powerreduction in some applications.(a)Advanced I/O cellsThe I/O library is powered by 2.5Vsupply. It provides ~30% fasterresponse due to smaller voltage swingand faster devices. The standard buffercells are tolerant to 3.3V signals, andcan interface any 3.3V device withTTL signal levels. In addition, thesecells are compatible with cold spare.LVDS buffers, with cold spare andfail safe capabilities had beendeveloped. These buffers enables>400MHz speed (800Mbps @DDR) atextreme temperatures. The outputcurrent is referenced externally,enabling tuning the drive strength foroptimal speed and power performance.(b)Figure 1: Conventional (a) andRadSafe TM (b) termination methodsTo enable configuring the use of thesame pins for either LVDS, poweredby 2.5V, or SSTL18, powered by 1.8Vsupply, in either directions, wedeveloped a fast multi-IO cell,presented in Figure 2.Several applications, such as fastmulti-IO cells, require isolated powerdomains. A complementary librarycells and methodology enables thatcapability, while supporting high ESDimmunity and low resistance of supplytraces.2
doutpdinpdinndoutnsenbobuflvdsoobufienblvdsoensenbienb-lvdsi+-lvdsi+lvdsienlvdsienFigure 2: Schematic of multi-IOcell in RadSafe TM libraryAll digital DLLsThe need for clock multiplicationand de-skewing is achieved by DLLcore. The tuning range of inputfrequency is 25÷125MHz, while theoutput can be configured to1X/2X/4X/bypass of reference input.The resolution is typically
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Advanced Features in RadSafe technology - Microelectronics - ESA

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