Thesis - Department of Electronic & Computer Engineering
Thesis - Department of Electronic & Computer Engineering
Thesis - Department of Electronic & Computer Engineering
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19.2Response Time V.S. Network Size N1918.8Response Time (ms)18.618.418.2180 10 20 30 40 50 60 70 80 90 100NFig. 2.4 Response time changes with network size N2.4 Related WorksLazzaro’s circuit [8] was the first hardware model <strong>of</strong> a winner-take-all network,which consists <strong>of</strong> only O(N) <strong>of</strong> interconnect. Each cell suppresses the outputs <strong>of</strong> allother cells through a global nonlinear inhibition. Since then, many improvements andvariations <strong>of</strong> this network with addition <strong>of</strong> positive feedback and lateral connectionshave been described.2.4.1 J. LazzaroIn Lazzaro’s design, a global nonlinear inhibition is computed by a single wire.Each cell contributes to this global inhibition, and each cell receives the same global16