Thesis - Department of Electronic & Computer Engineering

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queue a limited number of events, or discard aging events, have also been investigated[16].To illustrate this arbitered communication scheme, here we give one of the fullyarbitered implementations proposed by Boahen in [14].A full four-phase handshake is performed over a pair of wires between sender andreceiver, as shown in Fig. 3.3, which guarantees synchronization between chips. Thedata lines communicate the address of the sender to the receiver. A data-buffer is usedto queue unacknowledged events. Thus simultaneous events are serialized onto thesingle communication bus.SraraRdatadataCommunication modeldataraSignals and timingFig. 3.3 The arbitered communication scheme22
The sender initiates the sequence by driving its data onto the bus and taking r high.The receiver acknowledges by taking a high, after latching the data. This makesqueueing and pipelining straightforward: You make a neuron wait or stall a pipelinestage simply by refusing to acknowledge it.Pipelining is a well known approach to reduce the time of arbitration by breakingthe communication cycle up into a sequence of smaller steps that execute concurrently.As shown in Fig. 3.4, concurrency allows several address-events to be in various stagesof transmission at the same time, reducing the cycle time to the length of the longeststep.Sending neuronArbiter Encoder DecoderReceiving neuronTimeSetResetFig. 3.4 Pipelined communication channelCommunication cycle involving four-phase handshakes between sending neuron,arbiter, address encoder, address decoder, and the receiving neuron. White and blackboxes indicate the duration of the set and reset halves. In the pipelined channel, we donot wait for the next stage to acknowledge us before we acknowledge the previous23
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Page 41 and 42: The computer simulation results for
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whereV ˙ i () t=max( v i ()0 t , )
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θ t s Nf f wp ct(%) p cl(%) p cw(%
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10. “WTA networks with lateral ex
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Thesis - Department of Electronic & Computer Engineering

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