Techniques for in-band phase noise suppression in re-circulating ...

Techniques for In-band Phase Noise Suppression in Re-circulating DLLsAbstractThis paper presents a re-circulating delay-locked loop @LL)with various innovations to improve in-band phase noisesuppression. The voltage-controlled oscillator @’CO) andbias circuitry incorporate circuit-level techniques that reducel/f noise through switched biasing. The phase realignmenttheory presented in [I] is applied to optimize the VCO so asto maximize the phase noise suppression achieved byperiodically switching in a clean reference pulse, and it isfurther applied to optimize the loop filter. Theoreticalpredictions are verified through a 100 MHz prototype ICfabricated in a 0.18 p~ CMOS process.IntroductionFrequency synthesizers are critical blocks in communicationsystems. Ring oscillator VCOs are widely used in lowperformancefrequency synthesizer applications such asclock multiplication for digital systems because of theirsimplicity, wide tuning range, and ease of integration.However, they are less commonly used in communicationapplications wherein low phase noise is required, becausethey tend to introduce excessive close-in phase noise. In aconventional phase-locked loop (PLL) frequency synthesizer,the loop bandwidth is usually constrained to less than5% of the reference frequency to maintain stability acrossprocess and temperature extremes, so the PLL only provideslimited attenuation of the VCO phase noise.To overcome this barrier, a clean reference pulse can beinjected periodically into the VCO so as to reset the phaseerror and thereby suppress the noise memoty caused by thejitter accumulation effect in the VCO. The result is signifi-cant attenuation of the in-band phase noise. This noisereduction technique, referred to as phase realignment in theremainder of the paper, can be implemented in various ways.In a DLL based clock multiplier the delay of a voltagecontrolleddelay Line (VCDL) is locked to the referenceperiod [2]. Multiple delayed versions of the reference clockfrom the VCDL are then combined to produce the final clocksignal. Since the delayed reference is discarded at the end ofthe VCDL, phase realignment is performed naturally, bydesign. Another type of DLL, referred to as a re-circulatingDLL in the remainder of the paper, is implemented using aring VCO with the phase realignment performed by periodicallyopening the ring to discard the noisy VCO edge andreplace it with a clean reference edge [3]. Alternatively, in arealigned PLL [I], the phase realignment is performed bydirectly coupling a strongly buffered version of a cleanreference source into one of the inverters in the VCO. Thestrong buffer overpowers the VCO inverter so that the VCOphase is “dragged” toward the correct position.As demonstrated in [I], in both the re-circulating DLL andthe realigned PLL, parasitic coupling among the delay cellsSheng Ye”*, Lars Jansson2 and Ian Galton’1University of Califomia, San Diego, CA, USA2Silicon wave Inc., San Diego, CA, USAin the VCO tends to degrade the phase realignment and leadsto incomplete noise memory suppression. Therefore thechoice of VCO topology is critical in effectively implementingthe phase realignment technique.On the device level, llfnoise tends to severely degrade thein-band phase noise performance of the VCO. In analogy tothe phase realignment technique, llfnoise can be suppressedby periodically switching the associated transistors on andoff so as to suppress the long term noise correlation [4] [5].This paper presents a re-circulating DLL with a novel ringVCO topology. The VCO is optimized for the phaserealignment technique and also exploits switched biasing tosuppress llfnoise. The phase realignment theory from [I] isapplied to provide design guidelines and optimize the loopparameters. The fabricated IC can be configured as aconventional PLL and a re-circulating DLL. Measurementresults are presented that closely support the theoreticalfindings.Theoretical ModelA theoretical model is presented in [I] that characterizes thephase noise performance of both DLLs and realigned PLLs.It is based on physical observations that the phase of theVCO is shifted almost instantaneously when the phaserealignment occurs and that the phase shift is nearly linearwith respect to the instantaneous phase difference betweenthe VCO and the reference. The ratio between the phase shiftand the phase difference just before realignment is definedas p and referred to as the realigning factor. The value of pranges from 0 to 1 and is a measure of how completely thephase error is suppressed. The attenuation of VCO phasenoise increases as p increases. Therefore a large p isdesirable when a noisy VCO is used.Conventional frequency analysis on the DLL mainly focuseson the stability and settling of the loop [6],[7]. On the otherhand, quantitative analysis of conventional DLLs is usuallydone in the time domain [SI, [9], because DLLs are usedmainly in digital applications where jitter performance is ofinterest. Although jitter is a popular figure of merit, it isdifficult to separate the contribution to the jitter fromindividual noise sources in the circuit using the publishedanalyses. To optimize the loop filter parameters in a recirculatingDLL, the theory in [I] is applied here withoutmodification except that both first and second-order loopfilters are considered.As demonstrated below, the results indicate that when theVCO noise is dominant and a clean reference source is used,a second-order filter offers no benefit over a first-order filter,and increasing the loop filter bandwidth actually improvesthe attenuation of in-band VCO phase noise. Moreover,13-2-10-7803-7842-3/03Al7.00 0 2003 IEEE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE 297

to expect similar noise attenuation is achieved inside thedelay cell. This result confirms that the switched biasingtechnique is feasible up to at least 100 MHz. With both noisereduction schemes enabled, a peak spot phase noisereduction of 21.5 dB is observed compared to the conventionalPLL. Fig. 6 shows the measured phase noise when thesynthesizer is configured as a re-circulating DLL with a I"-order loop filter. The results support the assertions madeabove based on the theory presented in [I ] that a nide-bandI"-order loop filter yelds the best results.In the theoretical calculations. the VCO stand-alone phasenoise is required. This was obtained by measunng the phasenoise of the system with and without switched biasing andwith a very nmow bandwidth so that the phase noise isdominated by the VCO. Because the in-band phase noisewas domnated by the VCO. it was difficult to measure theinput and reference noise transfer function? from the phasenoise. In order to characterize the two transfer functions, asinusoid was ac coupled into the loop filter and the referenceclock pin, respectively. This injected signal, which is shapedby the noise transfer function, is upconverted to the synthesizeroutput in the form of spurious tones around the VCOcenter frequency. The power of the spurs were then measuredusing a spectrum analyzer. Sweeping the frequency ofthe injected signal provided a sampled version of the noisetransfer function.Due to the parasitic capacitance and inductance from thePCB board, it was difficult to measure the absolute value ofthe transfer functions. Alternatively. since the input noisetransfer function of a conventional PLL IS well known, it wasused as a reference and the measured results for the recirculatingDLL wth 20d and I" order loop filters werenormalized with respect to the convrntional PLL. Fig. 7shows the input phase noise transfer functions of th:conventional PLL, and re-circulating DLL with 2"d and Iloop filters. As shown in the figure, for the same total loopfilter capacitance, the DLL with a 1' order loop filterprovides more attenuation to input noise rhan that with a 2"'order loop filter. Fig. 8 shows the reference noise transferfunction of the conventional PLL, re-circulating DLL with22 pF loop filter and DLL with 2.2 nF loop filter. Asexpected, the loop filter bandwidth does nor significantlyaffect the attenuation of reference noise.References2000.6. T. Lee, J. Bulzacchelli, "A 155-MHz Clock Recovery Delay- and Phase-Locked Lmp", IEEE Jaumol of Solid Slote Circuits, vol. 27, No. 12,pp. 1736-1746, Dec. 1992.7. J. Maneatis, "Low-Jiner pmeess-independent DLL and PLL based onself-biased techniques," IEEE Jountal of Solid State Circuits, vol. 31,pp. 1723-1732, Nov. 1996.8. B. Kim, T. Weigandt, P. Gray, "PLUDLL System Noise Analysii forLow-jilter Clock Synthesizer Design", IEEE lntemotionol Symposiumon Circuits ondSysrem, Vol. 4, pp 31-34, Jun. 19949. R. van de BFek, E. Mumperink, C. Vaucher, B. Nauta, "LowlitterClock Multiplication: A Comparison Between PLLs and DLLS", IEEETransaclion on Circuils and System -11: Analog und Digitd SignalProcessing, Vol. 49, No. 8, pp 555-566, Aug. 2002.IO. P. Chen, S. Liu, "A Cyclic CMOS Time-to-Digitrl Converter WithDeep Sub-nanasccond Resolution", IEEE Cwrom lnregrored CircuitsConference, pp 605-608, May 1999.~~11. A. Hajimiri, S. Limotyrakis, T. Lee, "Jitter and Phase Noise in RingOscillators", IEEE Joumol of Solid Stote Circuits, vol. 34, No. 6 pp.790-804, Jun. 1999.TechnologyChip SizePackageReference FrequencyVCO FrequencyTuning RangePower ConsumptionTABLE IPdomance and Specification SummaryI.8V,O.I8pCMOS(I poly,6metal)2.2" x 2.2 mm32 Pin QFN4MHz (derived from a 32 MHz crystal)IOOMHzIMHz- 160MHz8.6mW (core)Figun I: Simplified block diagram ofthe proposed synthesim.I. S Ye. L. Janrson, 1. Galton. "A MultpIc-Crystal lnrcrfacc PLL wthVCO Rcalignmmt to Rcducc Phase Noire", IEEE Journal of Soird SmeCwcuiri. Vol. 37, No 12. pp 1795-1803. Dec. 2002.2. G. Chien, P. Gray, "A 900-Mtlz Local Oscillator Using a DLLbasedFrequency Multiplier Technique for PCS Applications", IEEE JoumdofSoiidStale Circuils, Vol. 35, No. 12, .. PP. 1996-1999, Da. 2000.3. R. Farjad-rad, et al., "A 0.2-2GHe l2mW Multiplying DLL for Low-Jiner Clock Synthesis in Highly-Integrated Data CommunicationChips", ISSCC Digest of Rchnievl Papers. pp. 76-77, Feb., 2002.4 I. Bloom, Y. Hemirovrky. ''Im Noix Reduction by lnlcrfcnng with IhcSelf Conchion of the Physical Noisy Proccrr", Elccvlcal and EleevunicsEnginens m Ismcl. 1991. heedmgr, 17th Convmr~on of, 5.7Mar. 19915. E Klumpmnk S. Gierkmk. A \an do Wcl, B. "a,"RedumpMOSFET I f Nom and Powcr Consumption by "Swuhed Biarmg"".IEEE Joumal ofSolrd lure CWNILF. Vol. IS. No. 7, pp 994-1001, Jul.Figure 2 VCO bias (a) Simplest implementation. @)One swightfonuardrealization of the switched biasing. (c) Operation details.13-2-3 299

"mI-.".marwyenryrmm cadrr (noFigure 6 Measured DLL phase noise showing the effect of Imp filter wideloop bandwidth resulll in more VCO noise attenuation.I ',.Z,Figure 3: (a) Pmposed bias generation. (b) Operation detailsT.ff.a,",v"v,"-n*n,wFigure 7: Measured input noise mnsfer function in PLL, resimulatingDLL with 2" and 1' order loop filter.Figure 4 (a) Delay cell with conventional latch. (b) Proposed delay cellwith impmvedp and a special latch for Ilfnoise attenuation.MeUurdph.rrmllr n rdrulndcm.ff.a,r."n/".""",WFigure 8: Measured reference noise transfer function in B DLL..*.".,"" *-'I'~-3ion c,-68np.-C,-8.2@ PL'BW=2WUIII,,wr~trwumqrml CH#Figure 5: Measured phase noise ofconventional PLL and re-circulatingDLL with a 2" odcr loop filter.Figure 9 Die photograph300 13-2-4