ATmega32A Datasheet - Sunrom Technologies

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<strong>ATmega32A</strong>The next code examples show assembly and C functions for reading the EEPROM. The examplesassume that interrupts are controlled so that no interrupts will occur during execution ofthese functions.Assembly Code ExampleEEPROM_read:; Wait for completion of previous writesbic EECR,EEWErjmp EEPROM_read; Set up address (r18:r17) in address registerout EEARH, r18out EEARL, r17; Start eeprom read by writing EEREsbi EECR,EERE; Read data from data registerin r16,EEDRretC Code Exampleunsigned char EEPROM_read(unsigned int uiAddress){/* Wait for completion of previous write */while(EECR & (1
<strong>ATmega32A</strong>8. System Clock and Clock Options8.1 Clock Systems and their DistributionFigure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocksneed not be active at a given time. In order to reduce power consumption, the clocks to modulesnot being used can be halted by using different sleep modes, as described in ““Power Managementand Sleep Modes” on page 33. The clock systems are detailed Figure 8-1.Figure 8-1.Clock DistributionAsynchronousTimer/CounterGeneral I/OModulesADC CPU Core RAMFlash andEEPROMclk ADCSource Clockclk I/OAVR ClockControl Unitclk CPUclk ASYclk FLASHReset LogicWatchdog TimerWatchdog ClockClockMultiplexerWatchdogOscillatorTimer/CounterOscillatorExternal RCOscillatorExternal ClockCrystalOscillatorLow-frequencyCrystal OscillatorCalibrated RCOscillator8.1.1 CPU Clock – clk CPUThe CPU clock is routed to parts of the system concerned with operation of the AVR core.Examples of such modules are the General Purpose Register File, the Status Register and thedata memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performinggeneral operations and calculations.8.1.2 I/O Clock – clk I/OThe I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.The I/O clock is also used by the External Interrupt module, but note that some external interruptsare detected by asynchronous logic, allowing such interrupts to be detected even if the I/Oclock is halted. Also note that address recognition in the TWI module is carried out asynchronouslywhen clk I/O is halted, enabling TWI address reception in all sleep modes.8155C–AVR–02/1125
Page 3 and 4: ATmega32A2. OverviewThe Atmel ® AV
Page 5: ATmega32Ametrical drive characteris
Page 9 and 10: ATmega32A6.3.1 SREG - AVR Status Re
Page 11 and 12: ATmega32A6.4.1 The X-register, Y-re
Page 13 and 14: ATmega32AFigure 6-5.Single Cycle AL
Page 15: ATmega32AA return from an interrupt
Page 18 and 19: ATmega32AFigure 7-2.Data Memory Map
Page 20 and 21: ATmega32AEEPROM data corruption can
Page 22 and 23: ATmega32ASupport - Read-While-Write
Page 26 and 27: ATmega32A8.1.3 Flash Clock - clk FL
Page 28 and 29: ATmega32AThe CKSEL0 Fuse together w
Page 30 and 31: ATmega32A8.7 Calibrated Internal RC
Page 32 and 33: ATmega32A8.10 Register Description8
Page 34 and 35: ATmega32Aface, Timer/Counters, Watc
Page 36 and 37: ATmega32A9.8.4 Internal Voltage Ref
Page 38 and 39: ATmega32A10. System Control and Res
Page 40 and 41: ATmega32AFigure 10-3.MCU Start-up,
Page 42 and 43: ATmega32AADC is used. To reduce pow
Page 44 and 45: ATmega32AThe WDP2, WDP1, and WDP0 b
Page 46 and 47: ATmega32Athe case if the Reset Vect
Page 48 and 49: ATmega32A$382D out SPL,r16$382E sei
Page 50 and 51: ATmega32A12. I/O Ports12.1 Overview
Page 52 and 53: ATmega32AIf PORTxn is written logic
Page 54 and 55: ATmega32AThe following code example
Page 56 and 57: ATmega32AFigure 12-5. Alternate Por
Page 58 and 59: ATmega32ATable 12-3.Table 12-4 and
Page 60 and 61: ATmega32A• MOSI - Port B, Bit 5MO
Page 62 and 63: ATmega32A12.3.3 Alternate Functions
Page 64 and 65: ATmega32ATable 12-11. Overriding Si
Page 66 and 67: ATmega32A12.4 Register Description1
Page 68 and 69: ATmega32A12.4.13 PIND - Port D Inpu
Page 70 and 71: ATmega32Alow level interrupt is sel
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ATmega32ASignal description (intern
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ATmega32Athe OCR0 value, the compar
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ATmega32AFigure 14-5.CTC Mode, Timi
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ATmega32AThe PWM resolution for the
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ATmega32AFigure 14-9. Timer/Counter
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ATmega32ATable 14-2. Waveform Gener
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ATmega32AThe Output Compare Registe
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ATmega32AFigure 15-1.T1/T0 Pin Samp
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ATmega32A16. 16-bit Timer/Counter11
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ATmega32Aput Compare Units” on pa
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ATmega32Athe main code and the inte
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ATmega32A16.5 Counter UnitThe main
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ATmega32AThe ICR1 Register can only
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ATmega32ARegister to either TOP or
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ATmega32AA change of the COM1x1:0 b
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ATmega32AThe PWM resolution for the
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ATmega32AUsing the ICR1 Register fo
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ATmega32ATable 16-3 shows the COM1x
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ATmega32A• Bit 7 - ICNC1: Input C
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ATmega32AThe Input Capture is updat
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ATmega32A17. 8-bit Timer/Counter2 w
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ATmega32AFigure 17-2.DATA BUSCounte
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ATmega32AThe setup of the OC2 shoul
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ATmega32AFigure 17-5.CTC Mode, Timi
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ATmega32A17.7.4 Phase Correct PWM M
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ATmega32AFigure 17-9. Timer/Counter
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ATmega32A• If Timer/Counter2 is u
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ATmega32AA FOC2 strobe will not gen
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ATmega32A17.11.2 TCNT2 - Timer/Coun
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ATmega32A17.11.7 SFIOR - Special Fu
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ATmega32Acommunication cycle when p
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ATmega32AAssembly Code Example (1)S
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ATmega32A18.3 SS Pin Functionality1
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ATmega32A18.3.4 SPSR - SPI Status R
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ATmega32A19. USART19.1 Features19.2
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ATmega32A19.2.1 AVR USART vs. AVR U
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ATmega32ATable 19-1.Operating ModeA
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ATmega32AThe frame format used by t
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ATmega32AThe following code example
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ATmega32AThe Transmit Complete (TXC
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ATmega32AAssembly Code Example (1)U
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ATmega32AThe PE bit is set if the n
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ATmega32AFigure 19-7.Stop Bit Sampl
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ATmega32AIf the receiver is set up
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ATmega32AThe following code example
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ATmega32A• Bit 0 - MPCM: Multi-pr
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ATmega32ATable 19-6.USBS Bit Settin
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ATmega32ATable 19-9.BaudRate(bps)Ex
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ATmega32ATable 19-11.BaudRate(bps)E
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ATmega32A20. Two-wire Serial Interf
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ATmega32Acondition is issued betwee
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ATmega32AFigure 20-6.Typical Data T
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ATmega32AFigure 20-9.Overview of th
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ATmega32A20.6 Using the TWIThe AVR
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ATmega32AAssembly code example C ex
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ATmega32ATable 20-2.Status Code(TWS
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ATmega32AFigure 20-12. Formats and
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ATmega32AThe upper seven bits are t
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ATmega32AFigure 20-16. Formats and
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ATmega32A4. The transfer must be fi
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ATmega32A20.9.2 TWCR - TWI Control
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ATmega32A20.9.5 TWAR - TWI (Slave)
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ATmega32A21.3 Register Description2
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ATmega32A22. Analog to Digital Conv
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ATmega32AIf differential channels a
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ATmega32Ain ADCSRA. The prescaler k
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ATmega32ATable 22-1.ConditionADC Co
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ATmega32AIf the user has a fixed vo
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ATmega32AFigure 22-9.ADC Power Conn
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INLATmega32AFigure 22-12. Integral
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ATmega32ATable 22-2.Correlation bet
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ATmega32ATable 22-4.MUX4:011010 ADC
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ATmega32A22.9.4 SFIOR - Special Fun
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ATmega32A• TMS: Test Mode Select.
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ATmega32AThe TMS input must be held
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ATmega32A23.8 Using the JTAG Progra
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ATmega32A24.3.1 Bypass RegisterThe
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ATmega32AThe active states are:•
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ATmega32AFigure 24-4. General Port
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ATmega32AFigure 24-7.Boundary-scan
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ATmega32ATable 24-4.SignalNameBound
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ATmega32ATable 24-5.SignalNameBound
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ATmega32ATable 24-6.Algorithm for U
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ATmega32ATable 24-7. ATmega32A Boun
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ATmega32ATable 24-7. ATmega32A Boun
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ATmega32A25. Boot Loader Support -
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ATmega32AFigure 25-1.Read-While-Wri
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ATmega32Amemory by SPM instruction.
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ATmega32ANotes: 1. The different va
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ATmega32A25.8.8 EEPROM Write Preven
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ATmega32Asbiw loophi:looplo, 2brne
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ATmega32A25.9 Register Description2
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ATmega32A26. Memory Programming26.1
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ATmega32ATable 26-4.Fuse Low ByteFu
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ATmega32ATable 26-7.Signal Name inP
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ATmega32Achanged. A Chip Erase must
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ATmega32AFigure 26-3. Programming t
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ATmega32A3. Set BS1 to “0” and
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ATmega32A26.7.14 Parallel Programmi
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ATmega32A26.9 SPI Serial Programmin
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ATmega32Awithout chip erasing the d
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ATmega32A26.9.4 SPI Serial Programm
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ATmega32A• Update-DR: The program
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ATmega32AFigure 26-14. Programming
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ATmega32AFigure 26-15. JTAG Program
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ATmega32AFigure 26-17. Virtual Flas
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ATmega32A26.10.18 Reading the Flash
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ATmega32A27. Electrical Characteris
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ATmega32A27.3 Speed GradesFigure 27
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ATmega32Aantees that a Brown-out Re
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ATmega32ATable 27-3. SPI Timing Par
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ATmega32ATable 27-5. ADC Characteri
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ATmega32A28. Typical Characteristic
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ATmega32AFigure 28-4.Active Supply
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ATmega32AFigure 28-8.Idle Supply Cu
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ATmega32AFigure 28-12. Idle Supply
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ATmega32A28.5 Standby Supply Curren
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ATmega32AFigure 28-20. Reset Pull-u
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ATmega32AFigure 28-24. I/O Pin Sink
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ATmega32AFigure 28-28. Reset Input
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ATmega32AFigure 28-32. BOD Threshol
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ATmega32AFigure 28-36. Calibrated 8
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ATmega32AFigure 28-48. ADC Current
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ATmega32A28.12 Current Consumption
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ATmega32A29. Register SummaryAddres
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ATmega32A30. Instruction Set Summar
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ATmega32AMnemonics Operands Descrip
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ATmega32A32. Packaging Information3
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ATmega32A32.3 44M1DMarked Pin# 1 ID
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ATmega32A34. Datasheet Revision His
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ATmega32A8.9 Timer/Counter Oscillat
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ATmega32A18.2 Overview ............
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ATmega32A26 Memory Programming ....
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Atmel Corporation2325 Orchard Parkw
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ATmega32A Datasheet - Sunrom Technologies

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