ATmega32A Datasheet - Sunrom Technologies

ATmega32AADC is used. To reduce power consumption in Power-down mode, the user can avoid the threeconditions above to ensure that the reference is turned off before entering Power-down mode.10.4 Watchdog TimerThe Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This isthe typical value at V CC = 5V. See characterization data for typical values at other V CC levels. Bycontrolling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted asshown in Table 10-1 on page 44. The WDR – Watchdog Reset – instruction resets the WatchdogTimer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.Eight different clock cycle periods can be selected to determine the reset period. If the resetperiod expires without another Watchdog Reset, the ATmega32A resets and executes from theReset Vector. For timing details on the Watchdog Reset, refer to page 41.To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followedwhen the Watchdog is disabled. Refer to the description of the Watchdog Timer ControlRegister for details.Figure 10-7.Watchdog TimerWATCHDOGOSCILLATOR10.5 Register Description10.5.1 MCUCSR – MCU Control and Status RegisterThe MCU Control and Status Register provides information on which reset source caused anMCU Reset.Bit 7 6 5 4 3 2 1 0JTD ISC2 – JTRF WDRF BORF EXTRF PORF MCUCSRRead/Write R/W R/W R R/W R/W R/W R/W R/WInitial Value 0 0 0 See Bit Description• Bit 4 – JTRF: JTAG Reset FlagThis bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected bythe JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logiczero to the flag.• Bit 3 – WDRF: Watchdog Reset FlagThis bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing alogic zero to the flag.8155C–AVR–02/1142