Defect oriented testing in advanced CMOS

Defect Oriented TestingVictor ChampacNational Institute for Astrophysics,Optics and Electronics-Mexicochampac@inaoep.mx

National Institute for Astrophysics,Optics and ElectronicsNational Council for Science and TechnologyCONACY-MexicoLocated in Puebla, MexicoOriented to research and post-graduate programs

Design and test group,research areas Defect modeling Development of new test strategies Signal integrity: modeling and verification Noise tolerant circuit design Process tolerant circuit design

Outline Introduction Interconnection opens defects modelling Detectability of interconnection opens A test framework for interconnection opens Conclusions

Motivation of the Work• Opens can appear due to the high number ofvias/contacts.• New technologies as cupper makes opens more likelyto occur.• Some opens are difficult to detect.• Special testing conditions are required to test opens.• Opens are responsable of test scapes.

Testing schemeTestvectorsCircuit undertestobservationcomparisonAccept/rejectAutomatic test equipmentreference

Quality levelAccepted chipsDefect-freechipsManufacturedpartsTestingDefectivechipsRejectedchips

Open Defects

Interconnection opens

Defect Modelling

Experimental measurementsIDDVDSVM

Experimental measurements1:CV = 3.8fF __ C 23.8fFGNDV=2 : C 3.8fF __ C 3.8fFDDV=GNDV=DD3:C = 23.8fF __ CGNDVDDV=3.8fF

Topology dependenceViVci..VcnVifFault00[V DD -|V TP |, V DD ]SA-101[V DD -|V TP |, V DD ]SA-110[0, V TN ]SA-011[0, V TN ]SA-0 Full controllability Partial controllability Low controllability

Partial controllabilityOne of the best test conditions can not be generatedV i V c = 00, 01, 11 okV i V c = 10not ok

Low controllabilityThe most favorable vector conditions can not be generatedV i V c = 00, 11 okV i V c =01, 10 not ok

Test framework forinterconnection opens

GEVEOPFASOPCoverageok?Test setvectors

Problem Definition000Input0SA-0couplinglines 0For favouring detection with a stuck-at 0 vector(Vif < VTN), the coupling signals should be at 1 logic

Problem Definition111Input1SA-1couplinglines 1For favouring detection with a stuck-at 1 vector(Vif >VDD-|VTP|), the coupling signals should be at 1 logic

CircuitDescription(Verilog)Input FilesRelation ofcouplingsEquivalence ofNodesOPVEGOPVEGStep 1Ordering and format of netlistIdentify couplings to VDD,GND and between nodesStep 2CouplingFactorIdentification and Selection ofcritical couplings betweennodes victim and aggressorsStep 3Obtain favorable testpatterns considering couplingsignals

Candidated lines A line is selected as critical when the ratio of thecoupled capacitance to the to total capacitance ishigher than a certain coupling factor.CcCT> Coupling Factor

OPVEG MetricsGenerated Vectors: They are those vectors for which atest vector was generated at least for one constraint(SA-0 or SA-1 ).Vectors 100% Ok: They are those vectors thatobtained the proper logic level for all the coupledsignals.

ResultsCouplingFactor20 %60 %100 %CriticalFaults3208832GeneratedVectors2987327Total Faults = 364CompactedVectors2267127Vectors100 % OK2296724C432OPVEGEffectiveness82.8 %79.9 %79.7 %CouplingFactor20 %60 %100 %CriticalFaults41815848GeneratedVectors38813738Total Faults = 486CompactedVectors2407223Vectors100 % OK31112937C499OPVEGEffectiveness85.5 %83.2 %78.1 %CouplingFactor20 %60 %100 %CriticalFaults42810420GeneratedVectors4219517Total Faults = 578CompactedVectors3268217Vectors100 % OK3869217C1908OPVEGEffectiveness92.5 %89.9 %85.0 %CouplingFactor20 %60 %100 %CriticalFaults1454408206GeneratedVectors1318373197Total Faults = 2204CompactedVectors1067310155Vectors100 % OK1130355187C2670OPVEGEffectiveness85.2 %89.6 %93.3 %

C432CouplingFactor20 %100 %Time ofselection ofNodes (m:s)00:4100:46CPUUsage47 %42 %Time ofATPGStuck-at-0 (m:s)15:4200:36CPUUsage93 %94 %Time ofATPGStuck-at-1 (m:s)10:5100:30CPUUsage95 %94 %ResultsC499CouplingFactorTime ofselection ofNodes (m:s)CPUUsageTime ofATPGStuck-at-0 (m:s)CPUUsageTime ofATPGStuck-at-1 (m:s)CPUUsage20 %100 %01:4101:2541 %50 %22:3200:5195 %89 %16:5100:4589 %89 %C1908CouplingFactor20 %100 %Time ofselection ofNodes (m:s)03:1203:00CPUUsage41 %43 %Time ofATPGStuck-at-0 (m:s)11:2800:19CPUUsage93 %86 %Time ofATPGStuck-at-1 (m:s)11:1400:20CPUUsage94 %91 %C2670CouplingFactor20 %100 %Time ofselection ofNodes (m:s)43:4052:48CPUUsage48 %34 %Time ofATPGStuck-at-0 (m:s)49:1704:22CPUUsage94 %94 %Time ofATPGStuck-at-1 (m:s)46:0404:08CPUUsage94 %93 %

Effectiveness usingconventional ATPG

Identification of criticalcasesNon observable CaseThis case appears when it is not possible to propagate the fault-effectfor favourable test at the coupling lines.Non Controllable CaseThis case appears when it is not possible simultaneously to sensitizethe fault and to have favourable conditions at the coupling signals.

Non observable caseX10X20EbC0XEC0g0/1C0XEC0X11X12EbC1X21X22EbC2XEC1gXEC2gSA0C20/1.XEC1XEC2PCgatePC1 / 0..X18X28EbC8XEC8g0 / 1XEC8

Non controllable caseX15XEB[0:4]B5E5Eb5EbB5EbB5g1 0 10SA0XEB5XEB5gXEB[6:8]1PBgatePBC0X25

DFT techniques• Increases separation between lines• Place critical coupling lines at different metal levels• Insert grounded lines

ConclusionsInterconnection opens have been modelled and analyzedA test framework for interconnection opens has beendeveloped.GEVEOP attempts to generate the most favourable testvector conditions by applying proper logic levels at thecoupled signalsThe number of considered critical open defective lines can beminimized by selecting only those lines with significantcoupling.FASOP is under development, it evaluates the defect coverageof interconnection opens