Reduction of Dishing in Polysilicon CMP for MEMS Application by ...

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 DresdenVDE VERLAG GMBH · Berlin-OffenbachReduction of Dishing in Polysilicon CMP for MEMS Application byUsing protective Layer and High SelectivityWoonki Shin 1 , Sungmin Park 2 , Hyoungjae Kim 3 , Kihyun Park 1 , Sukbae Joo 1 ,and Haedo Jeong 1,#1 Department of Mechanical and Precision Engineering, Pusan National UniversityBusan 609-735, Korea2 Dept. of Mechanical Engineering, University of California at Berkeley, CA, USA3 Busan R&D Center, Korea Institute of Industrial Technology, Busan 609-735, Korea# E-MAIL: hdjeong@pusan.ac.krThe aim of this paper is to develop the planarization process to make flat surface inpatterned areas for multilevel MEMS devices using CMP process. With creating planarsurface in each layer, the accuracy and flexibility of following steps such aslithography, etching and/or deposition process can be drastically enhanced. For thispurpose, the two step CMP process has been developed. The 30nm thick protectiveoxide layer was deposited to protect recessed areas. The wafer with protective layer isthen polished with low selectivity slurry to partially remove protruded area whilesuppressing the removal rate of the recessed area. After the first step CMP process,high selectivity slurry was used to minimize the dishing amount and variation inpattern structures. Experimental results show that the dishing amount was less than30nm at the largest pattern of 1250um wide and had no variation in whole patterns,which means local and global planarization. This result suggests that the developedtwo step CMP process can be successfully applicable to fabricate the multilevelMEMS device.Keywords: MEMS, Selectivity, Protective layer, Two step CMP1. IntroductionNow, polysilicon is an important material because of its broad applications for thin filmtransistors (TFT), liquid-crystal displays (LCD), large-scale integrated circuits (LSI), andmicro-electro mechanical system (MEMS) structures, etc [1]. Advanced MEMS devicesrequire their complicated mechanical, optical or electrical functions and are to be fabricatedby more sophisticated processes. Especially, three dimensional MEMS structure is one of thesolutions to realize multi-function by multilevel processing. However, the multilevelprocessing is possible on the flat planar surface in each layer. Moreover, MEMS has both ofmechanical and electrical parts, resulting in high step heights which is an obstacle to applywith a precise lithography process [2, 3]. To satisfy these requirements, CMP (ChemicalMechanical Planarization) is currently recognized as the most important process to realizeclear 3-D structures with high design flexibility among micromachining processes.However, the CMP technology, which has been used in ULSI process, is limited to applyto MEMS structures, due to their wide patterns of um to mm order and thick film layer ofseveral um. From the intrinsic behaviour of CMP process, wide and thick patterns makedishing phenomenon easily occur, which affects the device performance and throughput [4].So, CMP process engineers tried to solve the dishing problem by the formation of stop layeror using the fixed abrasive pad with high rigidity, however could not get an exact solutionwhich remains selectivity issues of slurry and defects on the pattern surface [5,6].

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 DresdenVDE VERLAG GMBH · Berlin-OffenbachThis paper focuses on the realization of local and global planarization of polysiliconMEMS structures by reducing the dishing amount and its variation. The basic processmechanism is two step polishing with different selectivity slurries on the protective orsacrificial oxide layer.Table 1 Specifications of the used slurry in the experimentSlurry (Silica based) Sample A Sample B Sample CAbrasive type Fumed Colloidal ColloidalAbrasive size 175nm 70nm 12nmpH 10.8 12 10.9Concentration 13wt% 28wt% 30wt%Application SiO2 Single crystal Si Poly Si2. Experimental ConditionsThis paper focused on the prevention of dishing problem generated in polysilicon patterns,which has been widely used in MEMS structures. Prior to investigating of dishing reduction,three different types of slurry were used with varying abrasive types, concentrations and pHsof slurry in order to find out the selectivity between polysilicon and oxide(SiO 2 ) (Table 1).Especially, thin layer (

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 DresdenVDE VERLAG GMBH · Berlin-Offenbachslurry with different selectivity on G&P POLI-500 polisher with endpoint detection system.Fig. 1(a) shows the photo-mask of the test patterned wafer, which has various pattern sizesof polysilicon based on MEMS structure scales. Also, Fig. 1(b) and Fig. 1(c) show the opticalimages of “A” region and “B” region, respectively. The thickness profile of patterned waferwas measured by using non-contact surface profiler, and the measuring ranges are “A1-A2”and “B1-B2” as shown in Fig. 1(b) and (c), respectively.3. Results and DiscussionsFrom the basic experimental results, the selectivity of slurry A, B and C was found to be70:1~3:1, 235:1~30:1 and 120:1~135:1, respectively. In case of slurry B, its selectivity has awide control range and strongly depends on the change in SiO2 MRR. It hardly removes theoxide layer. The change in MRR seems to be originated from the imbalance between thechemical and mechanical effects.Based on preliminary results, the polysilicon patterns with 100-1250um wide had beendirectly polished with oxide slurry at abrasive concentration of 13% (slurry A). The resultshowed not only a large dishing amount, but also increasing dishing amount according topattern width (Fig. 2(a)). This experiment reveals that conventional CMP of polysilicon cannot planarize wide patterns for MEMS structures. To reduce the dishing amount, authors havedeveloped two step CMP process (Fig. 2(b)) with the combination of deposition of oxideprotective layer and using high selectivity CMP process. To realize this, thin protective layerof SiO2 (30nm) was deposited on top of polysilicon layer and the two step CMP wasimplemented by oxide CMP with slurry A followed by high selectivity CMP with slurry B.At the first step with low selectivity slurry A, the top area of protective layer was removed toexpose polysilicon layer while remaining the protective layer in the trench. After removingthe protective layer, second step with high selectivity slurry was continued down to thebottom of trench areas. Due to its high selectivity (235:1), the CMP process stoppedspontaneously at the bottom of the trench, which prevents dishing in recessed areas.Direct CMP ProcessTwo Step CMP Process1) Poly-Si Deposition1) Protective Layer Deposition (30nm)2) Direct Poly-Si CMP2) First Step Oxide CMPSiO2Poly-Si3) Second Step Poly CMPSubstrate4) BOE Strip of Oxide(a) conventional one step process(b) the developed two step processFig.2 Reduction of dishing by using the two step CMP by the change of slurry selectivity

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 DresdenVDE VERLAG GMBH · Berlin-Offenbach(a) before CMP (b) one step process (c) two step processFig. 3 Comparison of dishing by one and two step processesThe comparison test of dishing amount by one step and two step processes was performed.Fig. 3 shows the information of surface profiles of 300um wide pattern trench which weremeasured by non-contact optical microscope. Fig.3(a) shows a profile before CMP, and (b)shows the result of conventional one step CMP with large dishing amount of 197nm, andfinally (c) has an ideal result without dishing, by the developed two step CMP process, whichverifies a successful trial that the thin layer of oxide protects poly-Si from high selectivityslurry.As for the uniformity of dishing amount, the one step process makes the dishing amountincrease according to pattern width. On the other hand, the two step process shows uniformprofiles without dishing independent on the pattern width. Fig. 4 shows the surface profilesafter one step and two step CMP according to pattern of small (a) and large size (b). We canfind the conventional one step CMP overcomes the requirement of MEMS structure up to300nm at the largest pattern width (1250um). However, the developed two step processenables an ideal uniformity of dishing amount, independent on the width of the patterntrenches, maintaining constantly under 30nm.(a) small patterns(b) large patternsFig. 4 Pattern dependency of dishing amount by one step and two step CMPTherefore, the result shows the reduction performance of dishing amount with less 30nm ofdishing even in 1250um trenched area (Fig. 5). Moreover, the two step process seems to be anexact solution to reduce the dishing amount, regardless of the change of pattern width. Basedon polysilicon CMP results, we believe that a variety of pattern size can be successfully

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 DresdenVDE VERLAG GMBH · Berlin-Offenbachplanarized by using developed two step process which also could be used to increaseflexibility in designing sophisticated MEMS devices.Dishing amount (nm)4003503002502001501005001 step 2 step100 150 210 300 625 1250Pattern width (um)Fig. 5 Comparison of dishing performance according to pattern width4. ConclusionAs a MEMS device is getting sophisticated, advanced process has been developed to meetthe requirement of each process steps. One of the emerging needs for complicated MEMSdevice is to make multilevel MEMS structures to include more functions in smaller space. Torealize this requirement, planar surface is mandatory to stack multiple layers and the flatfoundation gives a lot of design flexibility for making high performance devices.To make planar surface, the two step CMP process has been developed by using low andhigh selectivity slurry combined with protective layer. The highest removal rate selectivitybetween polysilicon and oxide was 235:1 and the lowest selectivity was 3:1 depending ontypes of slurry. With two step approach, the achieved dishing amount is suppressed to lessthan 30nm at 1250um trench. This result suggests that the developed CMP process can beapplicable for manufacturing of multilevel MEMS devices with a variety of pattern size.References[1] A. Tanikawa and T. Tatsumi, J. Electrochem. Soc., Vol. 141, p.2848 (1994)[2] Levrecht von Trotha, George Moersch and Gerfried Zwicker, Advanced MEMSfabrication using CMP, Semiconductor International, (8/1/2004)[3] Jeffry J. Sniegowski, Chemical-mechanical polishing: enhancing the manufacturabilityof MEMS, Proc. SPIE Vol. 2879, p. 104-115 (1996)[4] Beomyoung Park, et all, A Study on the Reduction of Dishing and Erosion Defects inTungsten CMP, J. of KSPE , Vol. 22, No. 2, p. 38-45 (2005)[5] Simon J. Fang, Vladimir A. Ukraintsev, Control of Polysilicon Topography in a HighSelectivity CMP Process, J. Electrochem. Soc., Vol. 146, No. 3, p.1158-1162 (1999)[6] Hoyum Kim, Hoyongjae Kim and Haedo Jeong, Development of an AbrasiveEmbedded Pad for Dishing Reduction and Uniformity Enhancement, J. of KPS, Vol. 37,NO. 6, p. 945 (2000)