microcontroller data book oki - Index of

OKIMICROCONTROLLERDATA BOOKISSUE DATE : DEC 1986

PREFACEA high technology company with an aggresive approach to innovation, OKI has beensupplying single-chip microcontrollers since 1975. OKI's single-chip microcontrollersfind wide application in various types of electronic equipment in the consumer and theindustrial fields. Our products have been enjoying a good reputation for their highquality and high performance. The most outstanding feature employed in all of OKI'smicrocontrollers is CMOS technology which ensures low power operation.OKI will continue to enhance the its microcontroller series and program developmentsystems to cater to cutomers' requirements.OKI makes no warranty for the use of its products and assumes noresponsibility for any errors which may appear in this document nordoes it make a commitment to update the information containedherein.OKI.retains the right to make changes to these specifications atany time, without notice.

CONTENTS1. PROGRAM DEVELOPMENT SYSTEM . ................................................. .2. LINE-UP AND TYPICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73. CODE ENTRY .......................................................................... 151. USABLE MEDIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 172. SINGLE CHIP MICROCONTROllER DEVELOPMENT STAGES. . . . . . . . . . . . . . . . . . . . . . .. 184. PACKAGING........................................................................... 195. RELIABILITY INFORMATION .. ..................................................... , . . . 33"6. DATA SHEET .............. "........................................................... 43• OlMS-40 SERIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45MSM5840 . ... ............. ...... ......... ... ..... ........ ........... .... .......... 47MSM5842 . ..... ...... ..... ...... .......... ....... ........ ......... ................ 58MSM58421 ........................................................................ 66MSM58422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76MSM5847 ............................................•............................ 84• OlMS-50/60 SERIES .............................................................. 89MSM5052 ...."..................................................................... 91MSM5054 ............. .......................... ....... .............. ......... .... 97MSM5055 ......................................................................... 104MSM5056 .................................................................."...... 111MSM6051 .................................................................."...... 118MSM6351 ......................................................................... 126MSM6052 ......................................................................... 129MSM6352 ......................................................................... 139• OlMS-64 SERIES . ................... ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 143MSM6404 ...........................................................".............. 145MSM6404VS ...................................................................... 157MSM6408 ..............................................................".......... 159MSM6411 ......................................................................... 170MSM6422 ......................................................................... 181MSM6431 ......................................................................... 189MSM6442 ......................................................................... 201MSC6458 ......................................................................... 206MSC6458VS ........................................................................ 216iii

• OLMS-65 SERIES ................................................................... 217MSM6502/6512 .................................................................... 219• 8 BIT SERIES (OKI ORIGINAL) ....................................................... 229MSM62580 ......................................................................... 231MSM66301 ......................................................................... 240• 8 BIT SERIES (INTEL COMPATIBLE) ................................................. 259MSM80C35/48, MSM80C39/49, MSM80C40/50 .................................... 261MSM80C31 F/MSM80C51 F ......................................................... 286MSM80C51 FVS .................................................................... 311MSM80C154/MSM83C154 ......................................................... 312MSM85C154VS .................................................................... 3467. PROGRAM DEVELOPMENT SUPPORT SySTEMS .... .................................... 347EASE40 ................................................................................ 349EASE6400 ............................................................................. 358EASE6502 ............................................................................. 368EASE80C49 ........................................................................... 378MAC51 ............................................................................... 398iv

PROGRAM DEVELOPMENTSYSTEMS

PROGRAM DEVELOPMENT SYSTEMS FOROKI MICROCONTROLLERSOLMS-40 SERIEStarget chipdevelopment tool standard software adaptor module field debuggingpackage name (included in package) (if necessary) toolMSM5840 EASE 40 DB400 debugger(SERIAL INTERFACE) ASM40 cross assembler -MSM5842(BUS INTERFACE)MSM58421 MPB421 MPB202MSM58422MSM5847MPB422dedicated hardware·simul.ator -[Note]1. The standard software DB400 and ASM40 are avalable on CP/M-80 for most of personal computers, or ISIS-II forINTEL MOS.CP/M is a registered trade mark of Digital Research, and ISIS-II, MDS of Intel.LOW POWER SERIEStarget chipdevelopment tool package namestandard softwareMSM5052MSM5056MSM5054MSM5055MSM6051EASE5052/56EASE5054/55(EASE6051)EASEhostmonitorAMS50cross assemblerASM6351MSM6351MSM6353(EASE6351/6353)ASM6351ASM6353MSM6052EASE6052, (EASE6352/6052)ASM50MSM6352(EASE6352/6052)ASM6352[Note]1. The standard software is avilable under following operating system.CP /M-80 for most of personal computersMSDOS for OKI if800, NEC PC9801 etc.PCDOS for IBM PC-XT, AT, IBM 55503

---------------. PROGRAM DEVELOPMENT SYSTEMS •8 BIT SERIES (OKI original)otarget chipdevelopment toolpackage namestandard software{included in package}optional softwareMSM66301EASE66301'ASM66301EASESee Note 1.MSM62580EASE62580'ASM62580EASE• under development[Note]1. Optional Software for MSM66301c-compiler (VMS for uVAX-II)relocatable assembler (VMS)object linker and librarian (VMS)cc66 debuger (VMS)symbolic debugger (VMS)• under development5

LINE-UP AND TYPICALCHARACTERISTICS

~---• OLM8-40 SERIESPOWERCLOCK ROM RAM INPUT I/OTYPE NO. PROCESS SUPPLY OUTPUT PORTFREQUENCY (BIT) (BIT) PORT PORTVOLTAGETIMER INTER· INSTRUC. MACHINESTACKCOUNTER RUPT TION CYCLEPOWER CONSUMPTIONACTIVE STAND-BYPACKAGEREMARKSMSM5840 CMOS 5V 4.2MHz 2048 x 8 128)(4 6 16 88 Bit R/W 2 4 98 7.61'S1.6mA -420lP/44FLA TMSM5842 CMOS 5V 4.2MHz 768)(8 32)(4 5 8 88 Bit - 1 52 7.6JlS1.5mA -28DIP/32FLA TMSM58421 CMOS 5V 4.2MHz 1536)(8 4Ox4 635LCD Seg.SLeD Seg. or LOGIC812 Bit - 1 52 7.6"S2.OmA -60FLATMSM58422 CMOS 5V 4.2MHz 1536)(8 4Ox4 57 x 5FLTSeg.5Discreate812 Bit - 1 52 7.6"S2.OmA -60FLATMSM6847 CMOS 3V 32kHz 1536x8 96)(4 - 24 x 3LeD Seg. 713 Bit - 2 43 610"S-----------_._-50,.A -44FLAT/CHIPco• OLMS-50/60 SERIESPOWERCLOCK ROM RAM INPUT I/OTYPE NO. PROCESS SUPPLY OUTPUT PORTFREQUENCY (BIT) (BIT) PORT PORTVOLTAGEMSM5052 CMOS 1.5V 32kHz 1280x 1 62)(4 8MSM5054 CMOS 1.5V/3V 32kHz 1024x 14 62)(4 6MSM5055 CMOS 1.5V/3V 32kHz 1792x14 96)(4 8MSM6068 CMOS 1.5V 32kHz 1792 xl 90)(4 4MSM6051 CMOS 1.5V/3V 32kHz 2560x 14 120)(4 9MSM6351 CMOS 1.5V/3V 32kHz 4096)(15 1024)(4 -26 x 2LCD Seg.5 LOGIC44)( 2LCD Seg.4 lOGIC -60 x 2LCD Seg.4 LOGIC-38 x 2LCD Seg.4 LOGIC63 x 3leC Seg.4 LOGIC-59 x 3lec Seg. or58 x 4LCD Seg.MSM6052 CMOS 3V 3.5~MHz 2048 x 14 640x4 12 12 4MSM6352 CMOS 3V 3.58MHz 2048 x 14 640x4 12 12 4--20TIMER INTER· INSTRUC. MACHINESTACKCOUNTER RUPT TION CYCLE- - - 42 122pS- - - 40 122pS- - - 42 122"S- - - 42 1221'S- 1 2 ,59 91.5pS- 3 7 65 61.0,,54 Bit 1 5 52 17.9".54 Bit 1 5 52 17.9".5POWER CONSUMPTIONACTIVE STAND-BY3pA -3pA -3pA -3,.A -3pA -3pA -1.2mA 0.2pA1.2mA 0.2pAPACKAGECHIPCHIPCHIPCHIPCHIPCHIP/l00FLAT28DIP/40DIP28DIP/40DIPREMARKSBuilt-in temperaturedetectorConnection withsolar cell availableUnderdevelopmentBuilt-in DTMFBuilt-in DTMFunderdevelopment=•CzmIC'tI• ZC~'tIn• r-():z:::u•()-Im::uiii-Inen•

...o• OLMs-&4 SERIESTYPE NO. PROCESSPOWERCLOCK ROM RAM INPUT 1/0SUPPLYOUTPUT PORTFREQUENCV (BIT) (BIT) PORTPORTVOLTAGEMSM6404 CMOS SV 4.2MHz 4000 x 8 256>

• 8 Bit SERIES (INTEL compatible)POWERTYPE NO. PROCESS SUPPLYVOLTAGECLOCK' ROM RAM INPUT 110OUTPUT PORTFREQUENCY (BIT) (BIT) PORTPORTTIMER INTER- INSTRUC- MACHINESTACKCOUNTER RUPTTION - CYCLEPOWER CONSUMPTIONACTIVESTAND-BYPACKAGEREMARKSMSMBOC35 CMOS 5V l1MHz - 64 x 8 - - 248 Bit R/W 2 8 111 1.36,,5lOrnA 1.A 40DIP/44FLATMSM80C39 CMOS 5V l1MHz - 128>< 8 - - 248 Bit R/W 2 8 111 1.36,,5lOrnA '.A 400lP{44FLATMSM80C40 CMOS 5V 6MHz - 256x 8 - 248 BitR/W 2 8 111 2.5"SlOrnA 1".4 40DIP/44FLATMSM80C31F CMOS 5V 16MHz - 128)( 8 3216 Bit R/Wx2 5 64 111 0.7S"S20mA I.A 40DIP/44FLATMSMBOC154 CMOS 5V 16MHz - 256x 8 3216 Bit RIWx3 6 128 111 0.751'520mA I,A 40DIPMSM80C48 CMOS 5V 1,MHz 1024 x B 64)( 8 24-MSM80C49 CMOS 5V '1MHz 2048 x 8 128)( 8 24MSM80C50 CMOS 5V 6MHz 4096 x 8 256x 8 24MSM80C51F CMOS 5V 16MHz 4096 x 8 128,.. 8 32MSM83C1S4 CMOS 5V 12MHz 16384x8 256 >C 8 32• 8 BIT SERIES (OKI original)POWERTYPE NO. PROCESS SUPPLYVOLTAGE-----,-----CLOCK ROM RAM INPUT 110OUTPUT PORTFREQUENCY (BIT) (BIT) PORTPORTMSM62580 CMOS 5V 4.9MHz 3072 x 8 128)( 8 1MSM66301 CMOS 5V 10MHz 16384 x 8 512" 8 8 40i8 Bit AIW 2 8 111 1.36,,58 Bit R/W 2 8 111 1.361{S8 Bit R/W 2 8 111 2.5"S16 Bit R/Wx 2 5 64 111 0.7S"S16 Bit RiWx3 6 128 111 I.S....TIMER INTER- INSTRUC- MACHINESTACKCOUNTER RUPTTION CYCLE- 32 95 860n516 Bit x4 17 256 99 400nSlOrnA I,A 40DIP/44FLATlOrnA I.A 40DIP/44FlATlOrnA 1".4 40DIP/44FLAT20mA I.A 40DIP/44FLAT20mA I.A 40DIPPOWER CONSUMPTIONACTIVESTAND-BYPACKAGE4rnA 10p.A T.B.O64 Shrink DIP!- - 68 PLCCI64 FLATREMARKSFan Ie cardsunder deVelop- .mentUnder developmen!- AIOC Bch. 1 Obit• USART-PWM• Chapter register=•r"ZmIC'V:J>ZtJ~'Vo:J>r"(')::z:::J>2J:J>(')-Im2Jiii-IoU)•

• LINE-UP AND TYPICAL CHARACTERISTICS .-------------LOW POWERIHIGH SPEEDOlMS-65 SERIESTYPE NO.ROM(BYTE IRAM(NIBBLES)POWERCONSUMP­TIONLCD SEGMENTMSM6502MSM65122000 x 82000 x 812B12B70p.A10B10BOlMS-64 SERIESTYPE NO.ROM RAM MACHINE(BYTE) (NIBBLES) CYCLE1/0 PORTM$M64044000 x B 256 1"(4MHz)36MSM640B8000 x 8 256 1"(4MHz)36OlMS-SO/60 SERIESMSM6411MSM6422MSM6431MSM6442MSC64581024)(8 32 1"(4MHz)2048)( 8 643,A(4MHz)1024)(8 48 1",(4MHz)2048)( a 12B 1",(4MHz)8000 x 8 512 1",(4MHz)1219141733TYPE NO.ROM(BYTE IRAM(NIBBLES)POWERCONSUMP­TIONREMARKMSM50521280x 1462Orl chip Temperature DelectlonCirCUlI 52 Set LCD OfillerMSM50541020x 146288 Seg. LCD DriverMSM50551792)( 1496120 Seg. LCD DriverMSM50561792)(1490Connection with solarcell available76 Seg. LCD DriverMSM60512560)(14120189 Seg. LCD DriverMSM63514096)( 151024232 Seg. LCD DriverMSM60522048)( 146401.2mABuilt-in DTMFMSM63522048)( 146401.2mABuilt-in DTMFOlMS-40 SERIESTYPE NO.ROM RAM MACHINE(BYTE) (NIBBLES) CYCLEMSM5840 2048)( 8 12B 8",(4MHz)MSM5842 768x 2 32 8"(4MHz)MSM58421 1536 x 8 46 8",(4MHz)MSM58422 1536x8 46 8}.!-5(4MHz)MSM5847 1536x8 96 600l's(32kHz)----_ ..11:1~1:1:114BITREMARKI/O port; 401/0 port; 2135 Seg. LCD Driver35 Seg. FLT Driver72 Seg. LCD Driver12

-------------. LINE-UP AND TYPICAL CHARACTERISTICS.I HIGH PERFORMANCE IIICOMPATIBLE WITH INTEL'S8 BIT MICROCONTROLLERTYPE NOROM RAM MACHINE(BYTE) (BYTE) CYCLEMSM80C48 1024 64MSM80C49 2048 128MSM80C50 4096 2561.36/15(11 MHz)1.36/,5(11 MHz)2.5/ls(6 MHz)MSM80C51F 4096 128 0.75"s(16 MHzlMSM83C154 16384 256MSM80C35 64MSM80C39 28MSM80C40 2561/,5(12MHzl1.36/15(11 MHz)1.36/15(11 MHz)2.5p.s(6 MHzlMSM80C31F 128 O.75"s(16 MHz IMSM80C154 2561/18(12MHz)8 BIT13

CODE ENTRY

-------------------------------------------eCODEENTRYeCODE ENTRYThe program code ENTERING method is outlined below.1. USABLE MEDIA(1) 2 pieces of same type EPROMs containing identical DATAEPROM specification2716273227C3227C32A276427C642712827256o(2) 1 copy of object machine code list17

• CODE ENTRY. -----------------------2. SINGLE CHIP MICROCONTROLLER DEVELOPMENT STAGESUSER 1• Program with OKI development tool.DifUSER 2800 TOOL• Prepare 2 pcs of EPROM and programming listI IEPROMOKI 3I IOKI4OKI5I IPrintout• Print out identical EPROM da~t:a.~~~~~~r;JZI11-1• Engineering SampleActual production sample of your microcontrollerchip prepared for final approval. ,~ ······~~y\toVED '.~ (j, .f,9.:~ ~.~~I sY. . ......... .~ ..• Volume production of single chip microcontrollers.18

PACKAGING

PACKAGINGPACKAGE/PIN COUNTDIP FLAT PLCCMSM5840 42PIN 44PIN -MSM5842 28PIN 32 PIN -MSM58421 - 60 PIN -MSM58422 - 60PIN -MSM5847 - 44PIN -MSM5052 - 56PIN -MSM5054 - 56PIN -MSM5055 - 80PIN -MSM5056* - - -MSM6051 * - - -MSM6351 - 100PIN -MSM6052 28/40 PIN 44PIN -MSM6352 28/40 PIN 44PIN -MSM6404 42PIN 44PIN 44PINMSM6404VS 42 PIN PIGGY BACK - -MSM6408 42PIN 44PIN 44PINMSM64ll l6PIN - -MSM6422 24PIN 24PIN -MSM6431 24PIN 24PIN -MSM6442 - 80 PIN -MSC6458 64 PIN SHRINK 64PIN 68PINMSC6458VS 64 PIN SHRINK - -PIGGYBACKNOTE: * means DIE SALES.21

• PACKAGING .-------------------------PACKAGE/PIN COUNTDIP FLAT PLCCMSM6502 - 56 PIN(S) -MSM6512 - 56PIN(S) -MSM62580 T.B.D. T.B:D T.B.D.MSM66301 64 PIN SHRINK 64PIN 68PINMSM80C35 40PIN 44PIN 44PINMSM80C39 40PIN 44PIN 44PINMSM80C40 40PIN 44PIN 44PINMSM80C31 40PIN 44PIN 44PINMSM80C48 40PIN 44PIN 44PINMSM80C49 40PIN 44 PIN 44PINMSM80C50 40PIN 44PIN 44PINMSM80C31 F 40PIN 44PIN 44PINMSM80C51 FVS 40 PIN PIGGY BACK - -MSM80C51 F 40PIN 44PIN 44PINMSM80C154 40PIN 44PIN 44PINMSM83C154 40PIN 44PIN 44PINMSM85C154VS 40 PIN PIGGY BACK - -22

------------------------'. PACKAGING·• 16 PIN PLASTIC DIP(Unit: mm)7.62±0300°_15°2.54±025 SEATING PLANE• 18 PIN PLASTIC DIP(Unit:mm)2.54±o.250"-15°SEATING PLANE23

• PACKAGING .----------------------------------------------~--• 24 PIN PLASTIC DIP(Unit:mm)II15.24±0.302.54:;1:0.250°-15'• 28 PIN PLASTIC DIPSEATING PLANE24

• 40 PIN PLASTIC DIP• 42 PIN PLASTIC DIP• PACKAGING •52.8 MAX(Unit: mm)15.24 ±03 0SEATING PLANE52.8 MAX (Unitmm)..>

•. • PACKAGING .I----------~-------------• 64 PIN SHRINK DIP58.0 MAX (Unit:mm)DIINDEX MARK19.05±O.300'>...15'SEATING PLANE26

-----------------------. PACKAGING •• 24 PIN PLASTIC FLAT16.0 ±O.3"IIn0.35±O; I1--o~;;+I +10"> 0r---:N(Unit:mm)CDINDEX MARK@• 32 PIN PLASTIC FLAT(Unit:mm)2.2±O.20.1-0.3INDEX MARK27

• PACKAGING ... ------------------------• 44 PIN PLASTIC FLAT14.S±O.41.5±0.2D· _10·(Unit:mm)oINDEX MARK• 56 PIN PLASTIC FLAT14.5±O.4(Unit:mm)INDEX MARK28

------------------------. PACKAGING.• 60 PIN PLASTIC FLAT24.0±04(Unit:mm)19.0±031.0±O.1CDINDEX MARK• 80 PIN PLASTIC FLAT(Unitmm)25.0±O'20.0 ±O.3O.S±O.I2.1 ±O.20-10"INDEX MARK29

• PACKAGING .--------------------------------------------------• 44 PIN PLASTIC PLCCINDEX MARK(. max: mm)unrt=-­min:mm1.27 T~P~116 . 0014.99 I• 68 PIN PLASTIC PLCC~ .2.oINDEX MARK;;;;5270~~\u:w 24.332@) .~ ~4.130~ unlt=--­. max:mm)min:mmf ~ 0 '0 ®~.C::§;0:~ ~~-wwwO~®~I. . 23.62 1·22.61 •30

------------------e. PACKAGING.• 40 PIN PIGGY BACK(Unit:mm)• 42 PIN PIGGY BACK(Unit:mm)33.02f------- 2.54z _ x~

ePACKAGINGe--------------------------------------------• 64 PIN SHRINK PIGGY BACK1"-[' -----~- 58.00(Unit:mm)X

RELIABILITY INFORMATION

RELIABILITY INFORMATION1. INTRODUCTIONSemiconductor devices playa leading role in theexplosive progress of semiconductor technology.They use some of the most advanced design andmanufacturing technology developed to date.With greater integration, diversity and reliability,their applications have expanded enormously.Their use in large scale computers, controlequipment, calculators, electronic games and inmany other fields has increased ata fast rate.A failure in electronic banking or telephoneswitching equipment, for example, could have farreaching effects and can cause incalculablelosses. So, the demand, for stable high qualitymemory devices is strong.We, at Oki are fully aware of this demand. So wehave adopted a comprehensive quality assurancesystem based on the concept of consistencyin dE;!velopment, manufacturing and sales.With the increasing demand for improvement infunction, capability arid reliability, we will expandour efforts in the future. Our quality assurancesystem and the underlying concepts are outlinedbriefy below.2. QUALITY ASSURANCE SYSTEMAND UNDERLYING CONCEPTSThe quality assurance system employed by Oki canbe divided into four major stages: device planning,developmental prototype, production prototype, andmass production. This system is outlined in the followingblock diagram (Fig. 1).1) Device planning stageTo manufacture devices that ineet market demandsand satisfy customer needs, we carefully considerfunctional and failure rate requirements, utilizationform, environment and other conditions. Once wedetermine the proper type, material and structure,we check the design and manufacturing techniques,and the line processing capacity. Then we preparethe development planning and time schedule.2) Developmental prototype stageWe determine circuits, pattern design, processsettings, assembly techniques and structural requirementsduring this stage. At the same time,we carry out actual prototype reliability testing.Since device quality is largely determined duringthe designing stage, Oki pays careful attentionto quality confirmation during this stage.This is how we do it:(1) After completion of circuit design (or patterndeSign), personnel from the design, processtechnology, production technology, installationtechnology and reliability departmentsget together for a thorough review to ensuredesign quality and to antiCipate problemsthat may occur during mass production.Past experience and knOW-how guide thesediscussions.(2) Since many semiconductor memories involvenew concepts and employ high levelmanufacturing technology, the TEG evaluationtest is often used during this stage.Note: TEG (Test Element Group) refers tothe device group designed for stabilityevaluation of MOS' transistors,diodes, reSistors, capacitors andother circuit component elementused in LSI memories.(3) Prototypes are subjected to repeated reliabilityand other special evaluation tests. Inaddition, the stability and capacity of themanufacturing process are checked.3) Production prototype stageDuring this stage, various tests check the reliabilityand other special features of the productionprototype at the mass production factory level.After confirming the quality of a device, we preparethe various standards required for massproduction, and then start production. Althoughreliability and other special tests performed onthe production prototype are much the same asthose performed on the developmental prototype,the personnel, facilities and production sitediffer for the two prototypes, necessitatingrepeated confirmation tests.4) Mass productionDuring the mass production stage, carefulmanagement of purchased materials, parts andfacilities used during the manufacturing process,measuring equipment, manufacturing conditionsand environment is necessary to ensure devicequality first stipulated during the deSigningstages. The manufacturing process (including inspectionof the completed device) is followed bya lot guarantee inspection to check that thespecified quality is maintained under conditionsidentical to those under which a customer wouldactually use the device. This lot guarantee inspectionis performed in three' different forms asshown below.(1) Group A tests: appearance, labels, dimensionsand electrical characteristicsinspection(2) Group B tests: check of durability underthermal and mechanical environmentalstresses, andoperating life characteristics(3) Group C tests: performed periodically tocheck operational life, etc.,on a long term basis.Note: Like the reliability tests, the group B testsconform to the following standards.MIL-STD-883B, JIS C 7022, EIAJ-IC-12135

IwOJ"TI....cQloc..;:;:

---------------'-----. RELIABILITY INFORMATION.• Acceptance InspectionProductionProcessWafer Process&Assembly'-----.----'I• Production Process Quality ControlLot ControlEquipment ConditionsIn·Process InspectionThermal ScreeningSe.1 Test• Electrical Test• Regular Check of MeasuringEquipment,-----''----.,. Group A Test• Group B Test'-----,r----' • Group C Test• Early Removal of Defective DevicesFigure 2 Manufacturing ProcessDevices which pass these lot guarantee inspectionsare stored in a warehouse awaiting shipmentto customers. Standards are also set up forhandling, storage and transportation during thisperiod, thereby ensuring quality prior to delivery.Figure 2 shows the manufacturing flow of thecompleted device.5) At Oki, all devices are subjected to thoroughquality checks. If, by chance, a failure doesoccur after delivery to the customer, defectivedevices are processed and the problem rectifiedimmediately to minimize the inconvenience tothe customer in accordance with the followingflowchart.Failure reportdeliveryRequest fortechnicalimprovementr - Rep;t~;;---IIQualityAssuranceDepartmentresults ofinvestigation& improvementReport onresults ofI investigationL _ ~ ~~r~v.:~e~tRequest formanufacturingimprovementFigure 3Failure report process37

• RELIABILITY INFORMATION • -----------,---------~Use Quality-••ServiceFailure Analysis• Customer I "formation Analysis~ tQuality Assurance&Quality Control• Quality and Reliability InformationQuality EvaluationDefective Analysis• Reliability Engineering• Quality Management and EducationTarget Quality• Operation Standard• Technical Standard• Quality Standard• Design Review• Prototype ReviewDesign Quality3. EXAMPLE OF RELIABILITY TESTRESULTSWe have outlined the quality assurance systemand the underlying concepts employed by Oki.Now, we will give a few examples of the reliabilitytests performed during the developmental andproduction prototype stages. All reliability testsperformed by Oki conform to the following standards.MIL-STO-883B, JIS C 7022, EIAJ-IC-121Since these reliability tests must determine performanceunder actual working conditions in ashort period of time, they are performed undersevere test conditions. For example, the 125°Chigh temperature continuous operation test performedfor 1000 hours is equivalent to testingdevice life from 2 to 300 years of use at Ta =40°C.By repeating these accelerated reliability tests,device quality is checked and defects analyzed.The resulting information is extremely useful inimproving the manufacturing processes. Someof the more common defects in LSI elements andtheir analysis are described on next page.38

------------------. RELIABILITY INFORMATION.'~M!CROCONTROLLER LIFE TEST RESULTSPart name MSM80C31 151- MSM80C35/39/48/49- MSM83C154-XXRS XXRS XXRSFunction 8 BIT ONE CHIP 8 BIT ONE CHIP 8 BIT ONE CHIP ReferredMICROCONTROLLER MICROCONTROLLER MICROCONTROLLER standardTest Test Sample Test Failures Sample Test Failures Sample Test Failuresitem condition size hours size hours size hours(pcs) (pes) (pcs)Operating Ta=125°C 88 2000 0 88 2000 0 88 2000 0 MILlifetest Vcc=6V (H) (H) (H) STD-883CMETHOD1005Temperature Ta=85°C 100 2000 0 100 2000 0 100 2000 ( 0humidity test RH=85% (H) (H) (H)Vcc=6VTemperature -55°C.,tRT.,t150°C 100 500 0 100 300 0 100 500 0 MIL-STDeyclingtest (30 min) t (30 min) (ey) (ey) (cy) 883C(5 min)METHOD1010Pressure Ta=121°C 50 200 0 50 200 0 50 200 0cooker test RH=100%(H) (H) (H)2 atmPart nameI~Test Test Sample Test Failures Sample Test, FailuresMSM6404-XXJSMSM80C31JSFunction 4 BIT ONE CHIP 8 BIT ONE CHIP ReferredMICROCONTROLLER MICROCONTROLLER standarditem condition size hours size hours(pes)(pes)Operating Ta=125°C 88 2000 0 88 2000 0 MILlifetest Vcc=6V (H) (H) STD-883CMETHOD1005Temperature Ta=85°C 100 2000 0 100 2000 0humidity test RH=85%(H)(H)Vcc=6VTemperature -55°C.,tRT.,t150oC 100 500 0 100 500 0 MILcyclingtest (30 min) t (30 min) (cy) (ey) STD-883C(5 min) MEJTHOD1010Pressure Ta=121°C - 50 200 0 50 200 0cooker test RH=100%(H)(H)2 atm39

......,..----------...,....-------. RELIABILITY INFORMATION.MICROCONTROLLER ENVIRONMENTAL TEST RESULTS~PartnameMSM80C31 151- MSM80C35/39/48149- MSM83Cl54-XXRS XXRS XXRSFunction 8 BIT ONE CHIP 8 BIT ONE CHIP 8 BIT ONE CHIP ReferredMICROCONTROLLER MIOROCONTROLLER MICROCONTROLLER standardTest Test Sample Failures Sample Failures Sample Failuresitem condition size (pes) size (pes) size (pes)SolderingHeat Test260·C,10 SEC22 0 22 0 22, 0 MIL-STD-883CMETHOD2003°Temperature -5S·C"'RT"'lS0·C 2222 0 22 0 MIL-Cycling Test (30min) (Smin) {30m in) STO-863C\20 cycles METHOD1010°Thermal 100·C"'0·C 2222 0 22 0 MIL-Shock (Smin) (Smin) STO-883CTest 10 cycles METHOD1011Tensile SOO g 10 SEC MIL-LeadIntegrity1111 0 11 0 STD883CBending 2S0 g 90· BEND °METHOD3 TIMES 2004Solderability 230·C S SEC 22 0 ~ 0 22 0 MILST0883CMETHOD2003,~Part1;;.... '"name MSM6404 MSM80C31JSXXJSFunction 4 BIT ONE CHIP 8 BIT ONE CHIP ReferredMICROCONTROLLER MICROCONTROLLER standardTest Test - Sample Failures Sample Failuresitem condition size (pes) size (pcs)PRE-Bake,Bake1125·C, 6 hrs)"iii Soldering Vapor Phase Reflow1215t: 2°C.90+ lO.-Osee)E Heat Test2 times'" Ec:.. ~22 0 22 0c: Temperature -SS·C"'RT""SO·C MILwCycling Test (3Omin) (Smin) (3Omin) ST0-883C"iii20 cyclesMETHODE1010'"..s:....Thermal l00·C",O·c MIL-Shock (Smin) (5min) ,ST0-883CTest 10 cycles" METHOD1011~., '"Solderability 2Bake (12S·C, 24hrs) 22 0 22 0.... Immerse _into Flux:;; Immerse into Solder(215±2°C 10:!: 1sec)540

------------------. RELIABILITY INFORMATION •4. SEMICONDUCTOR MEMORYFAILURESThe life-span characteristics of semiconductorelements in general (not only semiconductor Iedevices) is described by the curve shown in thediagram below. Although semiconductormemory failures are similar to those of ordinaryintegrated circuits, the degree of integration(miniaturization), manufacturing complexity andother circuit element factors influence their incidence.J!! .,II:.2 ".0;u.Semiconductor Element Failure Rate CurveInitial SHIPPINGWear-outfailure + Random failurefailure ---.... 0-=\\\\\, ,"m

• RELIABILlTVINFORMATION .------------------5) Aluminum CorrosionAluminum corrosion is due to electrolytic reactionscaused by the presence of water andminute impurities. When aluminum dissolves,lines break. This problem is unique to the plasticcapsules now used widely to reduce costs. Okihas carefully studied the possible cause andeffect relationship between structure and manufacturingconditions on the one hand, and thegeneration of aluminum corrosion on the other.Refinements incorporated in Oki LSls permit superiorendurance to even the most severe highhumidity conditions.6) Alpha-Particle Soft FailureThis problem occurs when devices are highlyminiaturized, such as in 1 megabit RAMs. The inversionof memory cell data by alpha-particlegenerated by radio-active elements like uraniumand thorium (present in minute quantities, measuredin ppb) in the ceramic package materi.alcauses defects. Since failure is only temporaryand normal operation restored quickly, this isreferred to as a "soft" failure. At Oki we haveeliminated the problem by coating the chip surfaceof 1 megabit RAMs with a resin which effectivelyscreens out these alpha-particles.7) De.gradation in Performance CharacteristicsDue to Hot ElectronsWith increased ·miniaturization of circuit elements,internal electric field strength in the channelsincreases since the applied voltage remainsthe same at 5V. As a result, electrons flowing inthe channels, as shown in the accompanying diagram,tend to enter into the oxide film near thedrain, leading to degradation of performance. Althoughprevious low-temperature operation testshave indicated an increase of this failure, wehave confirmed by our low-temperature accelerationtests, including checks on test elementgroups, that no such problem exists in Oki LSls.Drain~VD+VG IG~ :SourceHot electronsDrainSubstrate sil iconPackage ceramicCharacteristic deterioration causedby hot electrons----::.,.",.:-:-."''TCC7"":"::C':7f-cc::--7""'77"''c::-c-~ S i I icon ox i de-=-:"'='-'-",--+J."-'-'"rI-'-""'""~'-'+=-'--'- Iii m+--~L.. ,,-particleIOnization alongthe ,,-particle pathSu bstrate sil iconWith further progress in the miniaturization of circuitcomponents, failures related to pin holeoxide film destruction and photolithography haveincreased. To eliminate these defects duringmanufacturing,Oki has been continually improvingits production processes based on reliabilitytests and information gained from the field. Andwe subject all devices to high-temperature burninscreening for 48 to 96 hours to ensure evengreater reliability.42

DATA SHEETS

OLMS-40 SERIES

OKI &emlconductorMSM5840CMOS 4-BIT SINGLE CHIP MICROCONTROLLERGENERAL DESCRIPTIONThe OKI MSM5840 microcontroller is a low-power, high-performance single chip device implementedin complementary metal oxide semiconductor technology. Integrated within this one chip are16K bits of mask program ROM, 512 bits of data RAM,30 Input/Output lines, a programmabletimer/counter, and oscillator. Program memory is byte wide and data-paths are organized in 4 bit nibbles.RAM and I/O lines are bit addressable. Up to 4K of external ROM interfaces to the 8 bit bidirectionalbus. 98 instructions include binary, BCD, logical operations; bit set, reset, test, 8 bit I/O; relativejumps; multifunctional instructions (increment, modify, skip); 8 bit wide table output; subroutine calland return. 94% of instructions are single byte, single cycle operations.FEATURES• Low Power Consumption - 8mW Typical• 100% Static Logic - 50J,LW Standby, Typical• 2K x 8 Internal ROM• Up to 4K x 8 External ROM• 128 x 4 I nternal RAM• 30 I/O Lines Incl. 8 Bit Data Bus• Programmable 8 Bit Timer/Counter• Self-contained Oscillator• 981nstructions• Expandable Memory and I/O• 2 Interrupt Levels• 4 Stack Levels• Operating Temperature-40° to +85°C• 3V to 6V Operating VDD• Battery Powered or Battery Backup• TTL Compatible (with pullups)• 7.6p.s Cycle Time @4.2MHz (VDD 5V± 10%)FUNCTIONAL BLOCK DIAGRAMDATA RAM(16 x8)( 41--o5V---OGND:.L. RESET.....,,

.MSM5840.--------------------------------------------~-----PIN CONFIGURATION (Top View)42 PIN PLASTIC DIP (RS)44 Pin Plastic Flat PackageAoA,A,A,SYNC B,"-MODEB,uz0> ~ 0~~"'i.l1 "' "' "' Ii.~ ~ > ~ ~ ~!NT PH:"0RESETPHoMODEosc,G, OSCo PG;WR G, PG,ROGoPGoKoPFoK,PK,PF;K,K,PK,PF,0, E, PK, PF'J0,0,0,GND"0a -6 0 0 uz z I~ g' w~ ~ ~ ~~ ~ ~"PGoPIN DESCRIPTIONDesignation Pin No, FunctionGND 21 CircuitGND potentialVDD 42 Main power source (+5V)OSCo 10 Crystal OSC input, external ,clock inputOSC, 9 Crystal OSC input, external clock output (not TTL compatible)PA,PB 1 t04 Pseudo-bidirectional ports for 4-bit parallel I/O. Used as a pair for 8-bit I/O. Used38 to 41 to output 8 LSBs of address in external ROM mode, Used to read externalinstruction during IF.PD,PE, 17t020 Output ports for 4-bit parallel output and bit set/reset. Specified by internalPE,PG 23t034 port pointer, Bit position specified by set/reset instruction, PD also used forinstruction address MSBs in external ROM mode during IF,PK 13 to 16 4-bit parallel or bit test input port (u nlatched)",PH 36 and 37 2-bit input port with latched memory (negative level sensitive)RESET 7 RESET has_priority over every other signal. (see MSM5840 user's manual forinitialization sequence)MODE 8 Used to enable external ROM mode during RESET and also to enable STOP modeduring execution (for stepping program)INT 6 Negative edge sensitive external interrupt signal associated with EI and DIinstructions. Vectors to location 200H.CIN 35 Negative edge sensitive external input for counter associated with ECT and DCTinstructions, Vectors to location 1 OOH. (same as timer)SYNC 5 General purpose synchronizing signal output at the beginning of each machinecycle, Used for address strobe during external ROM mode.RD 12 Read strobe pulseoccuring when port A or B is read (1 A, 1 B, 1 AB)WR 11 ' Write strobe pulse occurring when port A or B is written (OA, OB, OAB, OBS, OTD)IF 22 Read strobe pulse occurring during an instruction fetch from external ROM.48

--------------------------. MSM5840 •FUNCTIONAL DESCRIPTIONProgram ROMThe MSM5840 will address up to 4K bytes ofprogram ROM and can have 2K bytes of internalmasked ROM, or all ROM may be located externally.External EPROM may be used for programdevelopment with conversion to internal ROM occurringafter program debug and system checkoutand verification. All instructions are bytewide. Only three of the 98 instructions requiretwo bytes of program code. The instructions arerouted to a programmed logic array which generatesthe necessary internal control Signals.Data RAMData is organized in 4 bit nibbles. Internaldata RAM consists of 128 nibbles, 8 nibbles ofwhich are dedicated registers accessible directlyunder program control. These are the generalpurpose registers, W, X, Y and Z, and the 4 save(exchange) registers, CH, A, L, and AX. All otherDATA RAM must be addressed indirectlythrough the DP (data po,nter) registers, a sevenbit pointer (directly accessible by numerous instructions)consisting of 4 bit DPL register and a3 bit DPH register. Any nibble of internal dataRAM can be accessed through the DP registers.Some instructions automatically change the contentsof the DP registers allowing efficient arrayprocessing.Input/Output PortsPA, PB - These two ports are pseudobidirectionalports which can be used as simpleI/O lines or used as either a 4-bit or 8-bit parallelbus. An instruction fetches the external ROMdata through these ports by outputting the 8 loworder bits of address during SYNC followed byan IF (instruction fetch) cycle. In addition,synchronized data transfers are possiblethroLl9il these ports with the I/O pin signals RDand WR associated with certain input/output instructionsdedicated to these ports. In short, PAand PB can be used as a multiplexed address/instruction/data bus.PD, PE, PF, PG - These four output ports areaddressed indirectly through the TWO BIT portpOinter whose contents are changed throughcertain instructions. These ports are bit(set/reset) addressable. PD is also used for thehigh order bits of address during an external instructionfetch. PF and PG are open drain outputsand PG is set high by a hardware RESET.PK is an input port without memory, addressableeither as a nibble or bit level input.PH is a two-bit input port with memory, whichcan be tested and reset under program control.External InterruptThe TNT pin can be tested under programcontrol Dr enabled to cause a vectored interruptto location 200H. It is negative edge sensitive.Timer/CounterThe timer/counter is an 8-bit counter whoseinput is selected under program control to beeither an external Signal (CIN) or an internalsquare wave of 1/128 the frequency of the OSCoinput (2 MHz/128 = 15.625 kHz). Thetimer/counter can be enabled or disabled underprogram control as can be associated internal interruptwhich vectors to location 100H and hashigher priority than the external interrupt.StackThe stack is an LIFO queue for storing returnfrom-interruptand return-from-subroutine addressinformation. It is eleven bits wide and 4levels deep.Program Counter (PC)The program counter is 11 bits wide andloaded under program control.AccumulatorThe accumulator register is the data pathfocal point of the CPU. Approximately one-half ofthe instructions involve the accumulator. Its contentsare t~e source and destination for manyALU operations and port operations. CASE statements(computed GOTOs) are possible by usingthe Jump with Accumulator (JA) instruction.FlagsThe MSM5840 is endowed with the followingset of flags.Z - zero flagF- all ones0- all zerosC - carryT - timerCT - counterTM - timer flagINT - interruptINTE - interruptenableHo - Ho memoryXIndicates that the resultof the previous operationwas zeroIndicates a carry from theDPL registerIndicates a borrow fromthe DPL registerIndicates a carry from theprevious operationIndicates that the timer/counter is specified as atimerIndicates that the timer/counter is specified as acounterIndicates an overflow ofthe timer/counter registerLatching memory flag forthe external interruptIndicates that interruptshave been enabledIndicates that an inputhas been detected on theHo inputsame as Ho except H 1inputo indicates internal ROM,1 indicates externalROM. If all external ROM,o indicates first bank of2K.49

• MSM5840 .'-------------'--------------INSTRUCTION SET:;;Q)(3Instruction CodeMnemonic Description Byte Cycle7 6 5 4 3 2 1 0CLA Clear Accumulator 0 0 0 1 0 0 0 0 1 1CLL ClearDPL 0 0 1 0 0 0 0 0 1 1CLH ClearDPH 0 1 1 0 0 0 0 0 1 1LAI Load Accumulatorwith Immediate 0 0 0 1 Is 12 11 10 1 1LLI Load DPL with Immediate 0 0 1 0 13 i2 11 10 1 1LHI Load DPH with Immediate 0 1 1 0 '0 12 11 10 1 1L Load Accumulator with M~mory 1 0 0 1 0 1 0 0 1 1LM Load Accumulator with Memory then Modify DPH 1 0 0 1 0 1 11 10 1 1LAL Load Accumulator with DPL 0 1 0 1 0 1 0 1 1 1LLA Load DPL with Accumulator 0 1 0 1 0 1 0 0 1 1LAW Load Accumulator with W Register 1 0 0 0 0 1 0 0 1 1-g LAX Load Accumulatorwith X Register 1 0 0 0 0 1 0 1 1 1Q)a: LAY Load Accumulator with Y Register 1 0 0 0 0 1 1 0 1 1~ LAZ Load Accumulator with Z Register 1 0 0 0 0 1 1 1 1 1.9(f),j SI Store Accumulator to Memory then Increment DPL 1 0 0 1 0 0 0 0 1 121 SMI, Store Accumulator to Memory then Modify DPH ...J1 0 0 1 0 0 11 10 1 1and Increment DPLQ)Cl

----------------------------------------------------eMSM5840eINSTRUCTION SET (CONT.)Instruction CodeMnemonic Description Byte Cycle7 6 5 4 3 2 1 0DCA Decrement Accumulator - Skip if Not All Ones 0 0 0 0 1 1 1 1 1 1"E DCL Decrement DPL "' 0 1Q)0 1 0 1 1 0 1 1EDCM Decrement Memory 0 1 0 1 1~1 0 0 1 1uQ)DCW Decrement W Register Skip if All Ones 1 0 0 0 1 1 0 0 1 1e"E DCX Decrement X Register 1 0 0 0 1 1 0 1 1 1Q)E DCY Decrement Y Register 1 0 0 0 1 1 1 0 1 1~u.E DCZ Decrement Z Register ~ 1 0 0 0 1 1 1 1 1 1DCH Decrement DPH - Skip if All Ones and C = Zero 0 1 0 1 1 1 1 1 1 1CAO Complement Accumulator of One 0 1 0 1 0 0 0 0 1 1"iii AND And Accumulator with Memory 0 1 0 0 0 1 0 0 1 1u"0> OR Or Accumulatorwith Memory0 1 0 0 0 1 0 1 1 10...JEOR Exclusive or Accumulator with Memory 0 1 0 0 0 1 1 0 1 1RAL Rotate Accumulator Left through Carry 0 1 0 0 0 1 1 1 1 1AC Add Memory to Accumulator with Carry 0 1 0 0 1 1 0 0 1 1ACS Add Memory to Accumulator with Carry, Skip 0 1 0 0 1 1 0 1 1 1if CarryAS Add Memory to Accumulator, Skip if Carry 0 1 0 0 1 1 1 0 1 1u AIS Add Immediate to Accumulator, Skip if Carry 0 0 0 0 13 12~" 10 1 1E DAS Decimal adjust Accumulator in Subtraction 0 1 0 1 1 0 1 0 1 1£;~ CM Compare Accumulatorwith Memory, Skip if Equal 0 1 0 1 1 1 1 0 1 . 1AWS Add W Register to Accumulator, Skip if Carry 1 0 0 1 1 1 0 0 1 iAXS Add X Register to Accumulator, Skip if Carry 1 0 0 1 1 1 0 1 1 1AYS And Y Register to Accumulator, Skip if Carry 1 0 0 1 1 1 1 0 1 1AZS Add Z Register to Accumulator, Skip if Carry 1 0 0 1 1 1 1 1 1 1SPB Set Port Bit 1 0 1 1 0 0 11 10 1 1RPB Reset Port Bit 1 0 1 1 0 1 11 10 1 15MB Set Memory Bit 1 0 1 1 1 0 11 10 1 1RMB Reset Memory Bit 1 0 1 1 1 1 11 10 1 1en TAB Test Accumulator Bit 1 0 1 0 0 0 11 10 1 1fE."-Q) TMB Test Memory Bit 1 0 1 0 0 1" 10 1 1gj TKB Test K Port Bit 1 0 1 0 1 0 11 10 1 1~Q) THB Test H Port Bit Skip if One 1 0 1 0 1 1 0 10 1 1C/)[ii TI Test Interrupt flag 1 0 1 0 1 1 1 1 1 1TTM Test Time flag 1 0 1 0 1 1 1 0 1 1TC Test Carry flag 0 1 0 0 0 0 1 0 1 1SC Set Carry flag 0 1 0 0 0 0 0 0 1 1RC Reset Carry flag 0 1 0 0 0 0 0 1 1 151

• MSM5840 •• ----------------------------------------------------INSTRUCTION SET (CONT.)I nstruction CodeMnemonic Description Byte Cycle7 6 5 4 3 2 1 0Q) J Jump 0 0 1 1 0 110 19 a 2 2:§ 17 I. I. I. 10 I. il 10:::le JC Jump in Current Page 1 1 I. I. 10 i2 i1 10 1 1.c:::l(j) JA Jump with Accumulator 0 1 0 0 0 0 1 1 1 1"-.

-------------------------. MSM5840 •ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Limits UnitSupply Voltage VDD Ta=25°C -0.3t07 VInput Voltage VI Ta=25°C -0.3toVDD VOperating Voltage PF PG Vo Ta=25°C -0.3 to 25 VStorage Temperature Tstg -55to+150 °CNote: Stresses above those listed under ABSOLUTE MAXIMUM RATI NGS may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device atthese or at any other condition abovethose indicated in the operational sections of this specification is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.OPERATING CONDITIONSParameterSymbolConditionsLimitsUnitSupply VoltageVDD@1 MHz@4.2MHz3t06V4.5 t05.5 VOperating TemperatureFan OutTopNMOSLoadTTL Load-40to+85 °C151D.C. CHARACTERISTICS(VDD = 5V± 10%, Ta = -20° to + 70 0 e)High Input VoltageLow Input VoltageParameterHigh Output Voltage (1)Low Output VoltageOSCo Input Leak CurrentRESET, MODE LeakCurrentInput Leak Current(2)PA, PB High Output CurrentHigh Output Current(l)Low Output CurrentPF, PG Output Breakdown VoltageInput CapacitanceOutput CapacitanceCurrent Consumption(3)Notes: (1) Except PA, PB (see graphs), (2) Except OSCo, RESIT, iiilCiDE(3) Typical Value of VDD is 5VSymbolConditionsVIH -VIL- -VOHVOLIIHIlLIIHIlLIIHIlL10HIOH10LBVOHCICoIDDIDD10=-40/LA10= 1.6mAVI =VDD/OVVI =VDD/OVVI =VDD/OVVOH=0.4VVOH=2.5VVOL =0.4VIO=10/LAf= 1 MHzTa=25°Cf=lMHzTa=25°CVI =VDD/OVVI =VDD/OVf=4.2MHzMin. Typ. Max. Unit3.6 V0.8 V4.2 V0.4 V25I--- /LA-251I----50/LA1I--- /LA-1-1 mA-0.25 mA1.6 mA20 V5 pF7 pF10 200 /LA1.6 4 mA53

\ • MSM5840 ... --------~---------------'----A.C. CHARACTERISTICS (INTERNAL ROM MODE)(VDD = 5V±1 0%, Ta = -:-40° to +85°C)Parameter Symbol Conditions Min.Typ.Max.UnitCycle Time tCY 7.6Sync Pulse Width tsw 0.95/LS/LSRD Pulse Width tRW 1.9/LSSync 1 toRO 1 tRD CL =50pF 112 tCY +0.5WR Pulse Width tww 0.95Sync 1 toWR 1 tWD CL =50pF 13/16 tCY +0.5/LS/LS/LSPort Input Setup Time tDSR 4/16tCYPort Input Hold Time tDHR 0WR 1 to New Data ValidtDDWPA,PBCL =50pF0.80.8/LS/LS/LSSync 1 to New Data ValidtDDSPD, PE, PF, PGCL =50pF13/16tCY+0.5/LSPHo, PH ,Input Pulse Width tHW (1 ) 500nSCIN Input Pulse Width tcw 250nSINT Input Pulse Width tlNTW (1 ) 500nSNote: (1) The processor logi c wi II ignore the followi ng events:1. An INTfalling edge occurring during TINH of a TI instruction .. 2. A PHoor PH ,low level occurring only during TINH of a THB instruction.TIMING CHARTSSYNC~FlOWRPA, PBPD,PEPF, PG--' I(11tRDtwo'Cy~IItRW--) INPUT DATA!----tDSR_PK DON'T CARE I INPUT DATA'ItDDSOLD DATAtcwftH~iI ·1+'WW8-I--tDHR·1[;--~ NEW OUTPUTDATADON'T CARE:1JINEW DATAitNT~I-tINTWIt-----\I1/2 tCY tlNHI17/16tCylNote: (1) All 'ONES' must be output before reading port A or B.II1/16tCY54

-------------------------'. MSM5840 •A.C. CHARACTERISTICS (EXTERNAL ROM MODE)(Voo = 5V±1 0%, Ta = -40° to +85°C)Parameter Symbol Conditions Min.CycleTime tcv 7.6Sync Pulse Width tsw 0.95IF Pulse Width tlW 1.425Sync TtolF! tiD CL=50pF 3/16 tcv + 1Address Low Delay tLAD CL=50pFAddress Low Hold tLAH 1/16tCVInstruction Setup 'tiS 1/16tCVInstruction HoldtlHData Recovery tOR CL=50pF 0Address High Delay tHAD CL =50pFAddress High Hold tHAH 0Typ. Max. Unit1-'51-'51-'51-'50.8 1-'51/16tCV+1 1-'51-'5'20 nS0.8 1-'50,5 1-'50,5 1-'5SYNC --IPA,PBPOtswtiD{tlW_-tLAD1--, ~tL~H.:I tlS_HHDATA ADDRESSLOWINSTR-tHADDATACVtORADDRESS HIGH1I ItHAHDATADATA~Cycle Dependent Timings 4MHz 2MHz1/16tcv 0.51-'5 11-'51/16tCV+1 1.51-'5 21-'53/16tcV+1 2.51-'5 41-'54/16!cV-1 11-'5 31-'51/2tC),+1 51-'5 91-'57/16tCV 3.51-'5 71-'513/16tcV+1 7.51-'5 141'51MHz500kHz21-'541-'531-'551-'571-'5131-'571-'5151-'5171-'5331-'5141-'5281-'5271'5 531'555

.MSM5840.'----------------~----------------------------------TYPICAL PERFORMANCE CURVESSupply Current vs Supply Voltage(Ta = 25°C, No Load)lpm ,-----.---,-~-,__--r--__,Supply Current vs Oscillator Frequency(Ta = 25°C, No Load)10m ,------,..----,__---.,.-__,~0El00j,l10j,l~CClm~---~---+_~~Voo =6VI5V100j,l~---T7~~~+_--__i10j,lL_~~_L_ ___.L.-___ ~10K lOOK 1M 10Mf (OSC) (Hz)0.1 j,I '---'-_-'-__.L.-_-'-__---'o 3 5Voo(V)7 10Oscillator Frequency vs Supply Voltage10(Ta,; 25°C, CL = 50pF)Oscillator Frequency vs Temperature10(CL = 50pF)8NJ:~ 6(jeng.....42I/jV8NJ:~ 6(jeng.....42..........r--..-oo 1 35VOO(V)710-50o 50Ta (OC)1005~

__________________________ e MSM5840 eiLow Current Out vs VoltageHigh Current Out vs Voltage(Ta = 25°C, Except PA, PS)-10r-.-----,-----r-----r-------,~r-~----+_--~----_r------~1 0 r--tH'---:;;;; ...... ~-+~ -6 t-~----+_--~----_r------~E:co5~~~--+_----r_--~------~3 5 7 103 57 10Va (V)Va (V)Fall Time vs Load(Ta = 25°C, PA, PB, PO, PE, RO, WR,IF, SYNC)1000800onc:-:J 600:c...I-400200o----~VOO =5V10 20 50 100 200 500 1000CL (pF)Rise Time vs Load1000800..s 600:c...Jt"400200(Ta = 25°C, PO, PE, RO, WR, iF, SYNC)-... V /////VOO=5Vo10 20 50 100 200 500. 1000CL (pF)57

I , ,OKI semiconductorMSM5842CMOS 4-BIT SINGLE CHIP MICROCONTROLLERGENERAL DESCRIPTIONThe OKI MSM5842 microcontroller is a low-power, high-performance single chip device implementedin complementary metal oxide semiconductor technology. Integrated with this one chip are6K bits of mask program ROM, 128 bits of data RAM, 21 Input/Output lines, an 8-bit binarytimer/counter, and oscillator. Program memory is byte wide and data paths are organized in 4 bit nibbles.RAM and I/O lines are bit addressable. 52 instructions include binary, BCD, operations; bit set,reset, test;8-bit I/O; relative jumps; multifunctional instructions (increment, modify, skip); 8-bit widetable output; subroutine call and return. 94% of instructions are Single byte, Single cycle operations.Available in plastic (RS) package.FEATURES• Low Power Consumption - 7mW Typical • 52 Instructions• 100% Static Logic - 1 OO/lW Standby • 1 Stack Level• 768 x 8 Internal ROM• -20° to +70°C Operating Temperature• 32 x 4 Internal RAM / • 3V to 6V Operating VDD• 21 I/O Lines Inci. 8 Bit Data Bus • Battery Powered or Battery Backup• 8 Bit Binary Timer/Counter• TTL Compatible (with pullups)• Self-contained Oscillator • 7.6"s Cycle Time @4.2MHzFUNCTIONAL BLOCK DIAGRAM32)(4 RAMFEDCBA9876DEC32103210 3'-PE-J '-po--.J '----PK---J58

PIN CONFIGURATION (Top View)• MSM5842 •28 PIN PLASTIC DIP (RS) 32 Pin Flat PackagevOOPA,PA,PA,PAoPE,PBoRESETPE,PB,OSC,PE, PB, OSC,PEo PB, SYNCPO, NC PHoPO, GNO NCPO,CINYODPKoNCPOoPK,PE,PBoPK,PK,PE,PB, PK, PK, PE,PB, PK, NC PEoPB,PKoPOoPO,PO,PO,GNOCIN0PIN DESCRIPTIONDesignation Pin No. FunctionGND 14 CircuitGND potentialVDD 2B Main power source (+5V)OSCo 4 Crystal OSC input, external clock inputOSC, 3 Crystal OSC input, external clock output (not TTL compatible)PA,PB 6to 13 QuaSi-bidirectional ports for 4 bit parallel I/O. Used as a pairforB bit I/O.PD,PE 20t027 Output ports for 4 bit parallel output and bit sel/reset. Specified by internal portpointer. Bit position specified by set/reset instruction.PK 16 to 19 4 bit parallel or bit test input port (unlatched)PH 1 1 bit input port with latched memory (negative level sensitive)RESET 5 RESET must be low for more than one machine cycle and has priority over everyother signal. (see MSM5B42 user's manual for initialization sequence)CIN 15 Negative edge sensitive external input for timer/counter.SYNC 2 General purpose synchronizing signal output at the beginning of each machinecycle.59

• MSM5842 .--~--------------------'"---FUNCTIONAL DESCRIPTIONProgram ROMThe MSM5842 will address up to 768 bytesof program ROM. All instructions are byte wide.Only three of the 52 instructions require twobytes of program code. The instructions arerouted to a programmed logic array which generatesthe necessary internal contral signals.Data RAMData is organized in 4 bit nibbles. Internaldata RAM consists of 32 nibbles and one nibblewhich is a dedicated general purpose register,W, accessible directly under program contraLDATA RAM must be addressed indirectlythrough the DP (data pointer) register, a five bitpointer (directly accessible by numerous instructions)consisting of a 4 bit DPL register and a 1bit DPH register. Any nibble of internal data RAMcan be accessed through the DP registers. Someinstructions, automatically change the contentsof the DP register allowing efficient array processing.Input/Output PortsPA, PB - These two ports are pseudobidirectionalports which can be used as simpleI/O lines or used as either a 4 bit or 8 bit parallelbus.PO, PE - These two output ports are addressedindirectly through the ONE BIT portpOinter whose contents are changed throughcertain instructions. These ports are bit (set!reset) addressable.PK is an input port without a Latch circuit, addressableas a nibble input.PH is a one bit input port with a Latch circuit,which can be tested and reset under programcontrol.Timer/CounterThe timer/counter is an 8-bit counter whoseinput is an external signal (CiN). The TM flag isset when the timer/counter generates a carry.StackThe stack is a single register for storingreturn-fram-subroutine address information. It isten bits wide.Program Counter (PC)The program counter is ten bits wide.AccumulatorThe accumulator register is the data pathfocal point of the CPU. Approximately one-half ofthe instructions involve the accumulator. Itscontents are the source and destination formany ALU operations and port operations. CASEstatements (computed GOTOs) are possible byusing the Jump with Accumulator (JA) instruction.FlagsThe MSM5842 is endowed with the followingset of flags.Z - zero flagC - carryTM - timer flagHo - Ho memoryIndicates that the resultof the previous operationwas zeroIndicates a carry from theprevious operationIndicates an overflow ofthe timer/counter registerIndicates that an inputhas been detected on theHo inputINSTRUCTION SETMnemonicCLAClear AccumulatorDescriptionCCL ClearDPLCLH ClearDPH~(I)LAI Load Accumulator with ImmediateQ LL.I Load DPL with Immediate"Ci LHI Load DPH with Immediate(I)a: '"L Load Accumulatorwith Memory~ LAL Load Accumulator with DPLc5 LLA Load DPL with Accumulator-g LAW Load Accumulatorwith W RegisterInstruction Code7 6 5 4 3 2 1 0ByteCycle0 0 0 1 0 0 0 0 1 10 0 1 0 0 0 0 0 1 10 1 1 0 0 0 0 0 1 10 0 0 1 Is 12" 10 1 10 0 1 0 Is 12 11 10 1 10 1 1 0 0 0 0 10 1 11 0 0 1 0 1 0 0 1 10 1 0 1 0 1 0 1 1 10 1 0 1 0 1 0 0 1 11 0 0 0 0 1 0 0 1 1.9 SI Store Accumulatorto Memory then Increment DPL 1 0 0 1 0 0 0 0 1 1LWA Load W Registerwittr Accumulator 1 0 0 0 0 0 0 0 1 1LPA Load Port POinter with Accumulator 0 1 0 1 1 0 0 0 1 1LTI Load Timer with All Zeros 0 1 1 0 1 0 0 0 1 160

--------------------~----------------------------.MSM5842.INSTRUCTION SET (CONT.)Instruction CodeMnemonic Descri ptlon Byte Cycle7 6 5 4 3 2 1 0Q)01c::os.&; X Exchange Accumulatorwith Memory 1 0 0 1 1 0 0 0 1 10>en JA Jump with Accumulator 0 1 0 0 0 0 1 1 1 1-...&; CAL Call Subroutine 0 ,0 1 1 1 0 I.• 2 20c:: 17 I. I. I. Ia I. 11 10~aJ RT Return from Subroutine 0 1 0 1 1 0 0 1 1 2OTD Output Table Data 0 1 1 1 0 0 0 1 1 2OA Output Accumulator to Port A 0 1 1 1 0 0 1 0 1 1OB Output Accumulator to Port B 0 1 1 1 0 0 1 1 1 1:;Q,OP Output Accumulator to Port P designated Port 0 1 1 1 0 1 0 0 1 1:;0 Pointer~ OPM Output Memory to Port P deSignated Port Pointer 0 1 1 1 0 1 1 0 1 1Q,.E IA Input Port A in Accumulator 0 1 1 1 1 0 1 0 1 1IB Input·Port B in Accumulator 0 1 1 1 1 0 1 1 1 1IK Input Port K in Accumulatgr 0 1 1 1 1 1 0 0 1 12'E NOP No Operation 0 0 0 0 0 0 0 0 1 10U61

eMSM5842 .e----------------------------------------------------ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Limits UnitSupply Voltage VDD Ta=25°C -0.3t07 VInput Voltage VI Ta=25°C -Q.3toVDD VStorage Temperature Tstg -55 to +150 °CNote: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at these or at any other condition abovethose indicated in the operational sections of this specification is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.OPERATING CONDITIONSParameterSymbolConditionsLimitsUnitSupply VoltageVDD1MHz4.2MHz3t064.5t05.5VVOperating TemperatureTop-40t085 °CFan OutMOSLoadTTL Load401,D.C. CHARACTERISTICS(Voo = 5V±1 0%, Ta = -40° to +85°C)High Input VoltageLow Input VoltageParameterHigh Output VOltage (1)Low Output VoltageOSCo Input Leak CurrentRESET Leak CurrentInput Leak Current(2)PA, PB High Output CurrentHigh Output Curreni( 1 )Low Output CurrentInput CapacitflnceOutput CapacitanceCurrent Consumption(3)Notes: (1) Except PA, PB (see graphs)(2) Except OSCo, RESET(3) Typical Value of VDD is 5VSymbolVIH -ConditionsVIL -VOHVOLIIHIlLIIHIlLIIHIlL10H10H10LCICoIDDIDD10=-4O!LA10= 1.6mAVI=VDD/OVVI =VDD/OVVI=VDDIOVVOH=0.4VVOH=2.5VVOL=0.45Vf= 1 MHzTa=25°Cf= 1 MHzTa=25°CVI=VDD/OVVI=VDD/OVf=4.2MHzMin. Typ. Max. Unit3.6 V0.8 V4.2 V-'0.250.45 V25f---- !LA-251- !LA-201- !LA-1-1 mAmA1.6 rnA5 pF7 pF20 200 !LA1.5 4 rnA62

--------------------------. MSM5842 •A.C. CHARACTERISTICS(VDD = 5V±1 0%, Ta = -40° to +85°C)Parameter Symbol Conditions Min. Typ.Cycle Time tCY OSC=;4MHz 7.6Sync Pulse Width tsw 0.95Port Input Invalid Time tDiVPort Input Valid Time tDV 2Sync T to New Data Valid tDDS PD, PE CL = 50pFPHo Input Pulse Width tHW (1 ) 250Ciiifinput Pulse Width tcw 250Max. UnitIo'SIo'S112 tCY +0.5 Io'S10'813/16 tCY + 0.5 Io'SnSnSNotes: (1) The processor logic may ignore the following event:A PHo low level occurring only during TINH of a THB instruction.(2) All 'ONES' must be output before reading port A or B.TIMING CHARTS_tSW.=iSYNC --J }tCYr--PA,PBNote 2INPUT DATAtOlVtDV-PK DON'T CARE INPUT DATANEW OUTPUT D ATADON'T CAREPD,PEtDDSOLD DATANEW DATAPH Of--tHW-IfCINtcw-y~-"\"-7 /16 tCY1/2 tCY tlNHII1/16 tc y63

eMSM5842 e----------------------------------------------------TYPICAL PERFORMANCE CURVESSupply Current vs Supply VoltageSupply Current vs Oscillator Frequency5Cl.910m1m100 1LlOlL(Ta = 25°C, No Load)I(OSC) = 8MHz4MHz~~~~~~q2MHzlMHz100KHzOHz10m1m5 100ILCl.9lOlL~(Ta = 25°C, CL = 15pF)IVOO=5'l/V1/L0.11L L-oL-o-L_....L._...I.._--'o 1 3 5 7 10VOo(V)10K lOOK 1 M 10MI(OSC)(Hz)Oscillator Frequency vs Supply VoltageOscillator Frequency vs Temperature(Ta = 25°C, CL = 50pF)14(CL =50pF)N:c66(/)0;::;121086/V~V12N 10:c:2G 8(/)o;::; 6......... ~=5VI'442203 5 7 10o-50100VOo(V)64

---------------------------. MSM5842 •Low Current Out vs Voltage20(Ta = 25°C)High Current Out vs Voltage-4(Ta = 25°C)1510/' I-- VDD=5V5oVo 1 3 5 7Vo(V)10«E-3Ir-......9 -2I'-..-1 VDD~15y(PA~VDD=5Vo o 3 5 7Vo(V)PD,PESYNC10Fall Time vs LoadRise Time vs Load(ijc:1000800I 600..J!:"400(Ta = 25°C, PA, PB, PD, PE, SYNC)-D=5V200V~ VI'o10 20 50 100 200 500 1000CL(pF)1000800Ciic:':J 600:r:!:"400200(Ta = 25°C, PD, PE, SYNC)-V VjVI/ VDD =5Vo10 20 50 1 00 200 500 1 000CL(pF)65

OKI semiconductorMSM58421CMOS 4-BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVERGENERAL DESCRIPTIONThe OKI MSM58421 is a low-power, high-performance 4-bit single-chip microcontroller implementedin complementary metal oxide semiconductor technology.Integrated within this one chip is a 5 digit 7-segment LCD driver and PLA which can change thecharacter font for the 7 segments freely under the control of the mask programmable data.Also integrated in this chip are mask ROM of 1536 x 8 bits for programming, data RAM of 40 x 4bits, 13 general-purpose input/output ports, 12-bit timer, and clock oscillator to facilitate easy applicationto equipment with an LCD display.FEATURES• Low Power Consumption CMOS 4-bitOne-Chip Microcomputer• 100% Static Logic• 1536 x 8 bits Mask ROM• 40 x 4 bits Data RAM• 1 Static Register• Built-in 1 2-bit Timer (with 32 Hz CommonOutput)• All Input Ports Contain Schmitt TriggerCircuits• 8-bit Interface Bus• 52 Instructions• 94% of the 52 Instructions are 1 Byte and1Machine Cycle• Integrated with 13 Input/Output Ports and 40Static LCD Driver Circuit• +5V Single Power Supply, 60-Pin Mold FlatPackage• 7 -Segment Character User ProgrammableFont (32 Words x 7 Segments)• Various Functions Changeable under MaskProgram ControlFUNCTIONAL BLOCK DIAGRAM54321 gfedcbagfedcba gfedcba:gfedcba'gtedcba C 3 21 0 PH 3 2 1 0 3 2 1 0 5 "'6 OVoo Gy 5 S NZ L- PK-J'---PB--J Nee 0Mc 1 0aN\'PlCD6J'-PLCD5-J'-PLCD4--"-PLCD3...J\"'PLCO:z-,J'-PLC01..J• Crystal Oscillator 4.194304 MHz, SYNC = 7.63 ,",sec LCD common signal 32 Hz66

-------------------------. MSM58421 •LOGIC SYMBOLPIN CONFIGURATION;J;;J;RESETRES-ET) PORT AJ PORT BPLCD5-c~i~ ~~ ± ~ ~~j~ ~ ~~.,0~! J0 0~ ~r~PLCDJ-eJ PLeD 1PLCD3-cPLCD3-dPORT HJ PLeD 2PLCD2-ePlCD2-dPLCD6-5PORT K [KoK,K,K;] PLeD 3J PLeD 4PLCDS-fPLCD2-cPLCD2-gPLCD1-ePLC01-dJ PLeD 5PLC01-bPLeD 1-9PLeD l-cJ PLeD 6PLCD5-QPHSYNCPlC06-!GNDCOMMON+5V-vDDOSCIovSYNC- SYNC SIGNAL OUTPUTCOMMON- - -- COMMON SIGNAL OUTPUTo>PIN DESCRIPTIONDesignationPin No.GND 33VDD 23OSCo 17OSC, 16PA,PB 19 to 2224 t027PK28t031PH 14RESET 18CircuitGND potentialMain power source (+5V)Crystal OSC input, external clock inputFunctionCrystal OSC input, external clock output (not TTL compatible)Pseudo-bidirectional ports for 4-bits parallel I/O. To input data from these ports, it isnecessary to write "1" to them beforehand. When nothing is applied to theirterminals, the content of output ports is written in them, sothey can also be used asregisters. In addition, it is possible to use them for make 8-bit parallel outputdepending on instructions.Input ports for4-bit parallel input with no latching function.Input port with latching function to be set by negative logical signal.That is, this terminal is set at the time when the negative logical signal is applied to itfrom the. outside.It is reset automatically after execution of the test instruction of this port.The RESET signal which input has priority over all of other signals and performs thefollowing functions:(1) Resets all bits of the program counter;(2) Resets the timer counter and timer flag;(3) Resets the port pointer;(4) Resets the accumulator;(5) Resets I/O ports PA and PB;(6) Resets the input port PH flag;(7) Initializes the output port PLCD for LCD;(8) Resets the machine cycle to M ,.Since the RESETterminal is pulled up to VDD by an internal resistor (approx. 800kO), it is possible to make power ON/reset by connecting itwith an externalcapacitor.67

eMSM58421 .e------------------------------------~----~-------PIN DESCRIPTION (CONT.)Designation Pin No. FunctionSYNC 15 General-purpose synchronizing signal output. The signal is output at the beginningof each machine cycle. Output constantly, this signal is used also as clock pulse toexternal units.The cycle of SYNC becomes 32 times that of the original oscillation (8,..,s when theclock pulse is 4 MHz).PLCD 1 to 13 PLCD 1 - 6 (Pins 1 - 13 and 34 - 60)1 -6 34 to 60 7 -bit and 5-bit parallel output ports, respectively. They are used to direct drive anLCD (static type). Specification of each port is done by the port pointer (PP) asshown in the table below:Content of PPb3 b2 b, boPort Specifiedx 0 0 0 PLCDlx 0 0 1 PLCD2x 0 1 0 PLCD3x 0 1 1 PLCD4x 1 0 0 PLCD5x 1 0 1 PLCD61 "'--4x 1 1 0 PLCD6 5 and BIx 1 1 1 --X: Don't careBI: 7 Segment DecoderPLA Blank InputThe data of bo, olthe internal4-bit bus is written to 5 of PLCD6, and that of b3 toBI.COMMON 32 COMMON (Pin 32)COMMON output terminal. This output signal is connected tothe common electrodeof static type LCD. The frequency of the COMMON signal output is given with thefollowing equation:f(COM) = f(OSC)/217Where the basic clock f(OSC) is 4.19304 MHz, f(COM) becomes 32 Hz (duty ratio:50%).MASK OPTION TABLEf(ose) ~4.194304MHzPortKO PortK2 PortK3 Com momTimerNo. 28pin 30pin 31 pin 32pin0 K, K2 K, 32Hz 12bit1 K, BUZZER COMMON 32Hz 12bit2 K, BUZZER K, 32Hz 12bit3 K, BUZZER K, 64Hz 11 bit4 K, K, K, 64Hz 11 bil5 Ko K, K, 128Hz 10bit6 K, BUZZER K, 128Hz 10bit7 K, K, K, 256Hz 9bit8 K, K2 K, 512Hz 8bit9 K, BUZZER K, 512Hz 8bit68f (BUZZER)~2048Hz

-------------------------. MSM58421 •ABSOLUTE MAXIMUM RATINGSParameter Symbol ConditionsPower Supply Voltage Voo . Ta=25°CInput Voltage VI Ta=25°CPower Dissipation Po Ta = 25°C per 1 packageStorage TemperatureTstgLimitsUnit-0.3 to 7 V-0.3toVOO V200 mW-55to+150 °COPERATING RANGEParameter Symbol ConditionsPower Supply Voltage VOO I(OSC) = 0 to 4.2 MHzOperating TemperatureTOpFan Out (excluding COM, SEC)N-MOSLoadTTL LoadLimitsUnit4t06V-40 to +S5 °C15-1D.C. CHARACTERISTICS(Voo = 5V±1 0%, Ta = -40 to +85°C)ParameterSymbolConditionsMin.Typ.Max.Unit"H" Input Voltage"L" Input VoltageVIHVIL3.6O.SVV"H" Output Voltage( 1 )VOH10=-SOf.LAVOO-0.1V"H" Output Voltage(2)VOH10=-2Of.LAVOO-0.1V"H" Output Voltage(3)"H" Output Voltage(4)"L" Output Voltage (1 )"L" Output Voltage(2)"L" Output Voltage(5)OSCo Input Leak CurrentInput Current(6)PA"H"PBOutput CurrentVOHVOHVOLVOLVOLIIH/IILIIH/IIL10H10=-4Of.LA10=-15f.LA10=SOf.LA10 = 20f.LA10=1.6mAVI =VOOIVI =OVVI =VOOIVI =OVVO=0.4V4.24.2VV0.1 V0.1 V0.4 V101-10 f.LA1/-20 f.LA-1 rnA"H" Output Current(3) 10H"L" Output Current(4) 10LInput CapacityCIOutput CapacityCoCurrent Consumption 100VO=2.5VVO=0.4V1=1 MHz, Ta=25°C1=1 MHz, Ta=25°C1.= 4.194304 MHz,at no load-0.251.6572rnArnApFpF5 rnANotes: (1) Applied to COMMON(2) Applied to SEGMENT(3) Applied to SYNC(4) Applied to PA, PB(5) Applied to SYNC, PA, and PB(6) Applied to RESET, PK, and PH69

• MSM58421 .---------------------------------------------------SWITCHING CHARACTERISTIC(Voo = 5V±1 0%, Ta = -40° to +85°C)ParameterSYNC Delay Time fromClock (OSCo)Clock (OSCo) PulseWidthCycle TimeSYNC Pulse WidthPAPB Data Valid TimePKPAPB Data Invalid TimePKData Delay TimePort H Set Pulse Width(?)COMMON Delay Timefrom SYNCSEGMENT Delay Timefrom COMMONSymbolt¢dIcpWHtcf>WLtCYtswtDVtDiVtDDStHWtSCdtCSdConditions Min. Typ. Max. UnitCL =50pF 800 ns115 ns(1 ) ,",s(2) ,",SCL =50pF (3) ,",SCL =50pF (4) ,",SCL =50pF 500 ns500 nsCL =50pF 2 ,",$CL =50pF1 ,",StCPWLCLOCK (OSCo)SYNC70

----------------,------------. MSM58421 •~--~~------_tCY~(l~)----------~SYNC(6)PA, PB,PK(4)t------tD IV-----+--IN VALIDINPUT MODE ---___ +-_____ -..JIN VALIDPA,PBOUTPUTMODEPHSYNC_____~ ___ _J)(~:!·:~~~~~~~~O~L_~_D_:_:_:5_~_-_-_-_-_-_-_-_-_-~~~~~~-N-E-W-D-A-T-A-tT..... T-\ : T"""STRUeT.O" CYCLE'~ .1. TINH16xl/f(OSC)15xl/f(OSC).I.[L1 xl /f(OSC)Notes: (1 )lCV = 32 x l/f(OSC)(2) tsw = 4 x l/f(OSC)(3) tDV = 8 x l/f(OSC)(4) tDIV = 16 x 1 If(OSC) + 0.5 "'s(5) tDDS = 26 x l/f(OSC) + 1 P.s(6) When data is input from PA or PB, set the contents of PA or PB to"1" prior to reading instruction.(7) At execution ofthe THB instruction, any input made during a period ofTlNH (15 x 1 If(OSC» shownin theabove figure may be neglected.SYNCtscdCOMMONtcsdtcsdSEGMENT ____________ ~ r------------~(WHEN THE DISPLAY -------------­CONTENT IS FIXED)71

• MSM58421 .'--------------------------DESCRIPTION OF TERMINALSGND (Pin 33)Circuit grounding potentialVDD (Pin 23)Main power supplyOSCo (Pin 11)Input of internal oscillation circuit at one sideof crystal resonator and ceramic vibrator.OSC 1 (Pin 16)Output of internal oscillation circuit at theother side of crystal resonator and ceramic vibrator(not TTL compatible)PA, PB (Pins 19 ......, 22 and 24 - 27)These are quasi-bidirectional ports for 4-bitparallel 110. To input data from these ports, it isnecessary to write "1" to them beforehand.When nothing is applied to their terminals, thecontent of output ports is written in them, so theycan also be used as registers. In addition, it ispossible to use them to make an 8-bit paralleloutput depending on instructions.PK (Pins 28 - 31)Input ports for 4-bit parallel input with nolatching function.PH (Pin 14)Input port with latching function to be set bynegative logical signal.This terminal is set at the time when the negativelogical signal is applied to it from the outside.It is reset automatically after execution of thetest instruction of this port.RESET (Pin 18)Reset must be active for greater than 1 machinecycle.The RESET signal, when input, has priorityover all of other Signals and performs the followingfunctions:(1) Resets all bits of the program counter;(2) Resets the timer counter and timer flag;(3) Resets the port pointer;(4) Resets the accumulator;(5) Resets I/O ports PA and PB;(6) Resets the input port PH flag;(7) Initializes the output port PLCD for LCD; and(8) Resets the machine cycle to M 1.Since the RESET terminal is pulled up to VDDby an internal resistor (approx. 800k!l), it ispossible to activate power ON/reset by connectingit to an external capacitor.SYNC (Pin 15)This is a general-purpose synchronizingsignal output. The signal is output at the beginningof each machine cycle. Output constantly,this Signal is used also as clock pulse to externalunits.The cycle of SYNC becomes 32 times that ofthe original oscillation (8ILs when the Clock pulseis4MHz).PLCD 1 -6 (Pins 1 -13and 34 -60)These are 7 -bit and 5-bit parallel outputports, respectively. They are used to directlydrive an LCD (static type). SpeCification of eachport is done by the port pointer (PP) as shown inthe table below;Content of PPb3 b2 b, box 0 0 0 PLCDlx 0 0 1 PLCD2x 0 1 0 PLCD3x 0 1 1 PLCD4x 1 0 0 PLCD5Port Specifiedx 1 0 1 PLCD6-4x 1 1 0 PLCD6 5 and BIx 1 1 1 -X: Don't CareBI: 7 Segment Decoder PLA Blank InputThe data of bo, of the internal 4-bit bus is written to5 of PLCD6, and that of b3 to BI.COMMON (Pin 32)This is a COMMON output terminal. Thisoutput signal is connected to the common electrodeof static type LCD. The frequency of theCOMMON signal output is given with the followingequation:f(COM) = f(OSC)/217Where the basic clock f(OSC) is 4.19304 MHz,f(COM) becomes 32 Hz (duty ratio: 50%).72

---_______________________ e MSM.58421 eINSTRUCTIONS LISTMnemonicDescriptionInstruction Code7 6 5 4 3 2 1 0Byte CycleCLA Clear Accumulator 0 0 0 1 0 0 0 0 1 1CLL ClearDPL 0 0 1 0 0 0 0 0 1 1CLH ClearDPH 0 1 1 0 0 0 0 0 1 1LAI Load Accumulator with Immediate 0 0 0 1 Is I, 11 10 1 1LLI Load DPL with Immediate 0 0 1 0 13 i2 11 10 1 1LHI Load DPH with Immediate 0 1 1 0 0 10 11 10 1 1L Load Accumulator with Memory 1 0 0 1 0 1 0 0 1 1LAL Load Accumulator with DPL 0 1 0 1 0 1 0 1 1 1LLA Load DPL with Accumulator 0 1 0 1 0 1 0 0 1 1LAW Load Accumulator with W Register 1 0 0 0 0 1 0 0 1 1SI Store Accumulator to Memory then Increment DPL 1 0 0 1 0 0 0 0 1 1LWA Load W Register with Accumulator 1 0 0 0 0 0 0 0 1 1LPA Load Port Pointer with Accumulator 0 1 0 1 1 0 0 0 1 1LTI Load Timerwith Immediate "0" (ClearTimer& TMF) 0 1 1 0 1 0 0 0 1 1X Exchange Accumulatorwith Memory 1 0 0 1 1 0 0 0 1 1INA Increment Accumulator 0 0 0 0 0 0 0 1 1 1INL Increment DPL 0 1 0 1 0 1 1 1 1 1INM Increment Memory 0 1 0 1 1 1 0 1 1 1INW Increment W Register 1 0 0 0 1 0 0 0 1 1DCA Decrement Accumulator 0 0 0 0 1 1 1 1 1 1DCL Decrement DPL 0 1 0 1 0 1 1 0 1 1DCM Decrement Memory 0 1 0 1 1 1 0 0 1 1CAO Complement Accumulator of One 0 1 0 1 0 0 0 0 1 1RAL Rotate Accumulator Left through Carry 0 1 0 0 0 1 1 1 1 1AC Add Memory to Accumulator with Carry 0 1 0 0 1 1 0 0 1 1AS Add Memory to Accumulator, Skip if Carry 0 1 0 0 1 1 1 0 1 1AIS Add Immediate to Accumulator, Skip if Carry 0 0 0 0 13 I, 11 10 1 1DAS Decimal adjust Accumulator in Subtraction 0 1 0 1 1 0 1 0 1 1CM Compare Accumulator with Memory 0 1 0 1 1 1 1 0 1 15MB Set Memory Bit 1 0 1 1 1 0 11 10 1 1RMB Reset Memory Bit 1 0 1 1 1 1 11 10 1 1TAB Test Accoumulator Bit 1 0 1 0 0 0 11 10 1 1TMB Test Memory Bit 1 0 1 0 0 1 11 10 1 1THB Test H Port Bit 1 0 1 0 1 1 0 0 1 1TTM TestTimeflag 1 0 1 0 1 1 1 0 1 1TC Test Carry flag 0 1 0 0 0 0 1 0 1 1SC Set Carry flag 0 1 0 0 0 0 0 0 1 1RC Reset Carry flag 0 1 0 0 0 0 0 1 1 1J Jump 0 0 1 1 0 110 19 e 2 217 I. 15 I. Is i2 11 10JC Jump in Current Page 1 1 15 I. Is I, 11 10 1 1JA Jump with Accumulator 0 1 0 0 0 0 1 1 1 1CAL Call Subroutine 0 0 1 1 1 1,0 19 e17 I. 15 I. Is I, 11 102 2RT Return from Subroutine 0 1 0 1 1 0 0 1 1 1OTD Output Table Data 0 1 1 1 0 0 0 1 1 15 2OA Output Accumulator to Port A 0 1 1 1 0 0 1 0 1 1OB Output Accumulator to Port B 0 1 1 1 0 0 1 1 1 1OP Output Accumulator to Port deSignated Port Pointer 0 1 1 1 0 1 0 0 1 1OPM Output Memory to Port P designated Port Pointer 0 1 1 1 0 1 1 0 1 1IA Input PortA in Accumulator 0 1 1 1 1 0 1 0 1 1IB Input Port B in Accumulator 0 1 1 1 1 0 1 1 1 1IK Input Port K in Accumulator 0 1 1 1 1 1 0 0 1 1NOP No Operation 0 0 0 0 0 0 0 0 1 173

________• MSM58421 .~------------------------------------------------TYPICAL PERFORMANCE CURVESOuJput Current (lOL) TYP(VOO = 5V, Ta = 25°C)20r--'--~----~~(C-O-M-M-rO-N-t-er-m~in-a~l)~Output Current (lOH) TYP-1 0 .----,------.-----.--~--r-------__;< 15~~-,~----_±~--_+--------_1E(PA, PB, SYNC terminal)::I:9E~ 10~_tI_+-_+----_+_----+_----__I...S- "o "5~~---+-----+----_+--------_1o~~ __ ~ ____ ~ ____(SEGMENT terminal)~~3 5 7 10Output voltage Vo (V)< -8.§::I:9 -sE~... -4Co... "0 "-20 0 5 7 10Output voltage Vo (V)tTHL - CL Characteristic TYPtTLH - CL Characteristic TYP..E...J1000800::I:soot-..~...S- ""~. 4000 200o- :rr10 20 50 100 200 500 1000Load capacity CL (pF)1000SOO0;E::I:...Jt- SOOO>.~.~ 400...S- ""0 200/j .... / V/VOO=51--o10 20 50 100 200 500 1000/Load capacity CL (pF)74

-------------------------------------------------4eMSM58421 ef(OSC) - VDD Characteristic TYPf(OSC) - Ta Characteristic TYP12'N:I:~ 10UenJ.I:..> 8u" cr! 6.J" cr!.J

OKI semiconductorMSM58422CMOS 4-BIT SINGLE CHIP MICROCONTROLLER WITH FLT DRIVERGENERAL DESCRIPTIONOKI's MSM58422 is a low-power, high-performance 4-bit single-chip microcontroller implementedin complementary metal oxide semiconductor technology.Integrated within the one chip is a mask ROM of 1536 x 8 bits, RAM of 40 x 4 bits, 10 input/outputports 11-bit timer-counter, clock oscillator, 4-bit parallel arithmetic circuit, 40 static FL T driversetc.MSM58422 has an instruction set which consists of 4-bit arithmetic instructions, Boolean (bit)manipulation instructions (bit-set, bit-reset, bit-test), data input/output instructions, and 8-bit codetranslation (Table data out) instructions.Also the pseudo-bilateral ports are used for connection to the buses of other 8-bit systems.FEATURES• Low Power Consumption CMOS 4-bitOne-Chip Microcomputer• 1 00% Static Logic• 1536 x 8 bits MASK ROM• 8-bit Interface Bus• 1 Stack Register• 52 Instructions• +5V Single Power Supply• 60-Pin Flat Package• Built-in 11-bit Timer• 94% of the 52 Instructions and 1 Byte and 1Machine Cycle• Integrated with 10 Input/Output Ports and 40Static FLT Driver Circuit• PK and PH Input contain S9hmidt TriggerCircuitsFUNCTIONAL BLOCK DIAGRAIVIFED C5 4 3 2 1 gledcbaPFl T6 PFTL5 PFl T 4 PFTl3 PFl T2 PFTL 1oB PK PH 3 2 1 0 SROO VGUZ PA PBZERYESSDNNSCC 00CE 1 0TOSC 4,194304 MHz. SYNC = 7.63 f.Lsec76

-----------------------. MSM58422 •PIN CONFIGURATIONLOGIC SYMBOL44 Pin Flat Package_.c.cca~~~~~~~~a. a. a. a.PFLT 5-c 1PFlT3-a 2PFLT3-bPFLT5-dPFLT2-fPFLT2-aPFLT5--ePFLT 2-bPFLT1-fPFLTS-f 1PFLT1-aPFLT1-bPFLT5-gPFLTPHPFLTSVNCPFLTOSC, 1PFLT 3-e45 PFLT 3-d4 PFLT 2-c9 PFLT2-gPFLT l-ePFLT1-dPFLT l-cPFLT1-g4 PFLTS-lX'ial (----:..0 OSCJcsc,SYNCTESTSYNCPORTH H,PORTKDIM (BUZZER64Hz5VDVDIM,DIM?BUZZER64HzVDD'0'PORTAB· , PORTSPFLTt a-9PFlT2a-gPFLT3a-gPFlT4a-gPFLT5a-gPFLT61-5ABSOLUTE MAXIMUM RATINGParameterSymbolConditionsLimitsUnitSupply VoltageVooTa =25°C-0.3 -7 VInput VoltageVITa =25°C-0.3 -VOO VOutput Voltage (FLT)VoTa =25°CVOO -30VPower OissipationPoTa = 25°C per 1 packageTa = 25°C per 1 FLT2008mWStorage Temperature Tstg --55 -+125 °COPERATING CONDITIONSParameter Symbol ConditionLimitsUnitSupply Voltage VOO HOSC) = 0 to 4.2 MHzOperating Temperature TOp -Output Voltage (FL T) Vo -4-6 V-40 -+85 °CVOO -26 VFan Out (excluding FL Ts)NMOSLoadTTL Load151-77

eMSM58422 e--------------------------------------------------DC CHARACTERISTICS(Voo = 5V±1 0%, Ta = -40 - +85°C)\ Parameter Symbol Conditions"H" Input VoltageVIH"L" Input VoltageVIL"H" Output Voltage (1) VOH 10=-15/LA"H" Output Voltage (2) VOH 10 =-40/LA"L" Output Voltage (3) VOL 10 = 1.6 mAOSCo Input Leak Current IIH/IIL VI =VOO/OVInput Current (4) IIH/IIL VI =VOO/OV"H" Output Current (1) 10H Vo =0..4 V"H" Output Current (5) 10H Vo =2.5 V"H" Output Current (6) 10H Vo =3V"L" Output Current (3) 10L VO=O.4VFLT Output Leak Current ILO VO=VOO-26VInput Capacity CI f = 1 MHz, Ta = 25°COutput Capacity Co f = 1 MHz, Ta = 25°CCurrent Consumption IOD f = 4.2 MHz at no loadMin. Typ. Max. Unit3.6 V0.8 V4.2 V4.2 V0.4 V101-10 /LA1/-20 /LA-1 mA-0.25 mA-1 mA1.6 mA-10 /LA5 pF7 pF2 5 mANotes: (1) Applied to PA, PB(2) Applied to SYNC, BUZZER, 64 Hz and PFTL(3) Applied to PA, PB, SYNC, BUZZER and 64Hz(4) Applied to PH, RESET, OIM and PK(5) Applied to SYNC and 64Hz(6) Applied to BUZZER and PFLT78

-------------------------. MSM58422 •SWITCHING CHARACTERISTICS(VDD = 5V±1 0%, Ta = -40 - +85°C)ParameterSYNC Delay Time fromClock (OSCe)Clock (OSCe) Pulse WidthCycle TimeSINC Pulse WidthPAPB Data Valid TimePKPAPB Data Invalid TimePKData Delay TimePort H Set Pulse Width (8)64Hz Delay Timefrom SYNCBUZZER Delay Timefrom SYNCSEGMENT Delay Timefrom SYNCSymboltdtWHtWLTCYtswtDVtDVtDDStHWtSFDtSBDtSSDConditions Min. Typ. Max. UnitCL =50pF 800 ns115 ns(1 ) /Ls(2) /LsCL =50pF (3) /LsCL =50pF (4) /LsCL =50pF (5) ns500 nsCL =50pF 2 /LsCL =50pF 2 /LsCL =50pF (8) 2 /LsNotes: (1) tCY = 32 x 1/f(OSC)(2) tsw = 4 x 1/f(OSC)(3) tDV = 8 x 1/f(OSC)(4) tDIV = 16 x 1 If(OSC) + 0.5 /Ls(5) tDDS = 26 x 1/f(OSC) + 1 /LsCLOCK (OSCo)SYNC79

• MSM58422 • -------------------------1---.,..-,. ____ tCy.:.;(1:.:.) _____ --ISYNC(S)PA,PB,PK(4)1---tDIV--oo+--IN VALID VALID IN VALIDINPUT MODE _____ -1 ______ -' '\. __ ...J '---------PA,PBOUTPUTMODEPH____ ~x 1-1------O-L::::~ -----'---'OD-r*...,_N_E_W_D_A_T_A_nNotes: (6) When data input from PA or PB, set the contents of PA or PB to "1" prior to reading instruction.(7) Alteration by the instructions relative to output ports PFL T (it is in the case that the outputsof open drain are pulled down to GND by a resistor below 20 kOl. .SYNC______ ~ THB 'NSTRUOT'ON CYCLE'~ .1. TINHlSxl/f(OSC) 15xl/f(OSC):1.:f"L1 xl/f(OSC)Notes: (8) At execution of the THB instruction, any input made during a period of TINH (15 x1 If(OSC) shown in the above figure may be neglected.80

-------------------------. MSM58422 •1024 pulses32 pulses 32 pulses--~ISBD64HzISFD~=-=------------ ----~--------------------------------------32 pulsesSYNElLfLJUUL _______ _L L SEGH L SEGL H SEGNotes: (9) The waveform shown above is in lighting up state, in the case that that open-drain outputof FLT driver is pulled down to GND by a resistor below 20 k!1.DIM 1 and DIM2 inputs must be in the state specified above.81

eMSM58422e------------------------------------------------DESCRIPTION OF TERMINALSGND (Pin 33)Circuit grounding potentialVDD (Pin 23)Main power supplyOSC 0 (Pin 17)Input of the internal oscillation circuit at oneside of the crystal resonator and ceramicvibrator. .OSC , (Pin 16)Output of the internal oscillation circuit at theother side of the crystal resonator and ceramicvibrator (not TTL compatible)PA, PB (Pins 19 - 22 and 24 - 27)These are quasi-bidirectional ports for a 4-bitparallel I/O. To input data from these ports, it isnecessary to write a "1" to them beforehand.When nothing is applied to their terminals, thecontent of the output ports is written into them,so they can also be used as registers. In addition,it is possible to use them to make an 8-bitparallel output depending on instructions.PK (Pin 31)1-bit input port with no latching function. ContainsSchmidt a Schmidt Trigger Circuit.PH (Pin 14)Input port with latching function to be set bynegative logical signal.This terminal is set at the time the negativelogical signal is applied to it from the outside. It isreset automatically after execution of the testinstruction at this port.RESET (Pin 18)Reset must be active for greater than 1machine cycle.The RESET signal input has priority over allof other signals and. performs the followingfunctions: .(1) Resets all bits of the program counter;(2) Resets the .latches of I/O ports PA, PB andoutput port PFL T6;(3) Resets the timer flag (TMF);(4) Resets the accumulator;(5) Resets the skip F/F circuit;(6) Resets the machine cycle to MI;(7) Resets the output port PFL T5-1 to the dataof 7 Seg PLA address 0;Since the RESET terminal is pulled up to VDDby an internal resistor (approx. 800 kfl), it ispossible to activate power ON/reset byconnecting it to an external capacitor.SYNC (Pin 15)This is a general-purpose synchronizingsignal output. The Signal is output at thebeginning of each machine cycle. Outputconstantly, this signal is used also as ;Q clockpulse to external units.One SYNC cycle is 32 times that of theoriginal oscillation (8 /1-s when the clock pulse is4 MHz).82PFL T 1 - 6 (Pins 1 - 13 and 34 - 60)These are 7 -bit and 5-bit parallel outputports, respectively. They are used to directlydrive an FL T (static type). Specification of eachport is accomplished by the port pOinter (PP),which is a 4-bit register and is set to thecontents of the accumulator by the LPAinstruction.Latching data of each port is output throughthe logical AND operation with the DIMA signal(later described) and via buffer circuits. (Whenthe data in the latch is 1, DIMA is output. When itis 0, the output is at high impedance.)ContentofPPb3 b2 b, box 0 0 0 PFLT1x 0 0 1 PFLT2x 0 1 0 PFLT3x 0 1 1 PFLT4x 1 0 0 PFLT5Port Specifiedx 1 0 1 PFLT6-1....,.4x 1 1 0 PFL T6-5, BI and BZx 1 1 1 -x : Don't careBI: 7 Segment Decoder PLA Blank InputBZ: Control Signal output forthe buzzer outputThe inputs with the latching function of portsPFLT1-5 are connected to the outputs of the 7segment decoder PLA and that of PFL T6 directlyto the internal buses.DIM1, DIM2 (Pins 28, 29)Input terminals for the dimmer control ofoutput ports PFL T1-6.DIM1 DIM2 DIMAo1o1o111/4 duty1/8 duty1/16 duty1BUZZER (Pin 30)This terminal outputs the value of the logicalAND operation between latching bit 2 of outputport PFLT6 and the timer output (aS).By externally connecting a resistor and atransistor, this BUZZER output terminal is usedto control an alarm, buzzer etc.64 Hz (Pin 32)This is an output terminal, whose frequencyis 1/65536 of the OSCO. For example, when thefrequency of oscillator is 4.194304 MHz, thefrequency of the 64 Hz signal output is given 64Hz.. This olltput pulse is used for adjusting thefrequency. Its duty is 50%.

-------------------------. MSM58422 •INSTRUCTIONS LISTMnemonicDescriptionInstruction Code7 6 5 4 3 2 1 0Byte CycleClA Clear Accumulator 0 0 0 1 0 0 0 0 1 1Cll ClearDPl 0 0 1 0 0 0 0 0 1 . 1ClH ClearDPH 0 1 1 0 0 0 0 0 1 1lAI load Accumulator with Immediate 0 0 0 1 b 12 I, 10 1 1lLi load DPl with Immediate 0 0 1 0 b i2 I, 10 1 1lHI load DPH with Immediate 0 1 1 0 0 10" 10 1 1l load Accumulator with Memory 1 0 0 1 0 1 0 0 1 1lAl load Accumulator with DPl 0 1 0 1 0 1 0 1 1 1llA load DPl with Accumulator 0 1 0 1 0 1 0 0 1 1lAW load Accumulator with W Register 1 0 0 0 0 1 0 0 1 1SI Store Accumulator to Memory then Increment DPl 1 0 0 1 0 0 0 0 1 1lWA load W Register with Accumulator 1 0 0 0 0 0 0 0 1 1lPA load Port POinter with Accumulator 0 1 0 1 1 0 0 0 1 1lTI load Timer with Immediate "0" (Clear Timer & TMF) 0 1 1 0 1 0 0 0 1 1X Exchange Accumulator with Memory 1 0 0 1 1 0 0 0 1 1INA Increment Accumulator 0 0 0 0 0 0 0 1 1 1INl Increment DPl 0 1 0 1 0 1 1 1 1 1INM Increment Memory 0 1 0 1 1 1 0 1 1 1INW IncrementW Register 1 0 0 0 1 0 0 0 1 1DCA Decrement Accumulator 0 0 0 0 1 1 1 1 1 1DCl Decrement DPl 0 1 0 1 0 1 1 0 1 1DCM Decrement Memory 0 1 0 1 1 1 0 0 1 1CAO Complement Accumulator 01 One 0 1 0 1 0 0 0 0 1 1RAl Rotate Accumulator left through Carry 0 1 0 0 0 1 1 1 1 1AC Add Memory to Accumulator with Carry 0 1 0 0 1 1 0 0 1 1AS Add Memory to Accumulator, Skip il Carry 0 1 0 0 1 1 1 0 1 1AIS Add Immediate to Accumulator, Skip if Carry 0 0 0 0 13 12 I, 10 1 1DAS Decimal adjust Accumulator in Subtraction 0 1 0 1 1 0 1 0 1 1CM Compare Accumulator with Memory 0 1 0 1 1 1 1 0 1 15MB Set Memory Bit 1 0 1 1 1 0" 10 1 1RMB Reset Memory Bit 1 0 1 1 1 1 I, 10 1 1TAB Test Accoumulator Bit 1 0 1 0 0 0" 10 1 1TMB Test Memory Bit 1 0 1 0 0 1 I, 10 1 1THB Test H Port Bit 1 0 1 0 1 1 0 0 1 1TTM TestTimellag 1 0 1 0 1 1 1 0 1 1TC Test Carry flag 0 1 0 0 0 0 1 0 1 1SC Set Carry flag 0 1 0 0 0 0 0 0 1 1RC Reset Carry flag j 0 1 0 0 0 0 0 1 1 1J Jump 0 0 1 1 0 1'0 I. • 2 217 I. Is I. b i2" 10JC Jump in Current Page 1 1 Is I. b i2 I, 10 1 1JA Jump with Accumulator 0 1 0 0 0 0 1 1 1 1CAL Cali Subroutine 0 0 1 1 1 110 I. • 2 217 I. Is I. b 12 I, 10RT Return from Subroutine 0 1 0 1 1 0 0 1 1 1OTD Output Table Data 0 1 1 1 0 0 0 1 1-15 2OA Output Accumulator to Port A 0 1 1 1 0 0 1 0 1 1OB Output Accumulatorto Port B 0 1 1 1 0 0 1 1 1 1OP Output Accumulator to Port deSignated Port Pointer 0 1 1 1 0 1 0 0 1 1OPM Output Memory to Port P designated Port Pointer 0 1 1 1 0 1 1 0 1 1IA Input Port A in Accumulator 0 1 1 1 1 0 1 0 1 1IB Input Port B in Accumulator 0 1 1 1 1 0 1 1 1 1IK Input Port K in Accumulator 0 1 1 1 1 1 0 0 1 , 1NOP No Operation 0 0 0 0 0 0 0 0 1 183

OKI semiconductorMSM5847CMOS 4 BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVERGENERAL DESCRIPTIONOKI's MSM5847 microcontroller is a low-power, high performance single-chip device implementedin complementary metal oxide semiconductor technology. Integrated onto single chip are 1536 x8 bits of mask program ROM, 96 x 4 bits of data RAM, 7 input/output lines, 1 output line, a timer, LCDDriver and oscillator. Program memory is byte wide and data paths are organized in 4 bit nibbles. RAMis bit addressable. 43 instructions include binary, logical operations; bit set, reset, test; multifunctionalinstruction (increment, skip); subroutine call and return. 95% of instructions are single byte, singlecycle operations.FEATURES• Low Power Consumption 50 ,,"A Typical• 1 .5K x 8 Internal ROM• 96 x 4 Internal RAM• 7 I/O lines, 1 output line including 8 bit databus• 1 3 bit Timer• Self-contained Oscillator'• 43 Instructions• 2 Stack Levels• -20° to +70°C Operating Temperature• 3 V Operating VDD• 61 O,,"s Cycle Time @32.768 kHz• 44 pin Flat Package• Chip FormFUNCTIONAL BLOCK. DIAGRAMDATA MEMORY (RAM)16x6x4bitPROGRAMMEMORY(MASKROM)WF ELCD DRIVERTiming1/3 dutyl/3 bias Control22201816141210987654321023211917 lS 13 11Segment321 34 B\........J Hz UCommon ZZER3 2 1 0'----iPA32 1 0'----IPBSROOVGYESSDNNSCCDDCE01T84

-----------------------------------------------------eMSM5847eLOGIC SYMBOLPIN CONFIGURATION44 Pin Flat Package/.;J; J;. 32.768kHzoseoosc,}ortARESET'RESETSEGMENTD}ortBJ SegmentDseg~ent232334 Hz 34 Hz OutputBUZZER Buzzer OutputSYNCSynchronizedSignal+3V VDO COMMON 1 Common 1COMMON 2 Common 2DV GNO COMMON3 Common 3PBoPB,PB,PB3SegmentOSegment 1Segment 2Segment 3Segment 4Segment 5Segment 6Segment 22Segment 21Segment 20Segment 19Segment18Segment17Segment16Segment 15Segment 14Segment 13Segment 12ABSOLUTE MAXIMUM RATINGParameterSymbolConditionsLimitsUnitSupply VoltageVDD-0.3 -7VInput VoltageVITa = 25DC-0.3 -VOOVOutput VoltageVo-0.3 -VOOVStorage TemperatureTstg--55 - +125°COPERATING CONDITIONSParameterSymbol ConditionLimitsSupply Voltage VOO HOSC) = 32.768 kHz 2.7 -3.3Operating Temperature TOp - -20 - +70UnitVDC85

e MSM5847e-------,..--------------------AC CHARACTERISTICS(VDD = 3V±1 0%, Ta = -20 - +70°C)ParameterSymbolConditionMin. TYIil· Max. UnitSYNC Delay Timefrom Clock (OSCo)tet>CL =50 pF- - 5 JLSClock (OSCo) Pulse Widthtet>WHtet>WL-15 - - JLsCycle TimeSYNC Pulse WidthtCYtsw--Note (1) - - JLsNote (2) - - JLsPA, PB Data Valid TimetDV-Note (3) - - JLsPA, PB Data Invalid TimeData Delay TimetDIVtDDSCL =50pF-- - Note (4) JLs- - Note (5) JLsNote: (1) tCY = 20 x 1lf (OSC)(2) tsw = 2 x 11f (OSC)(3) tDV = 4 x 11f (OSC)(4) tDIV = 8 x 11f (OSC) + 20 JLS(5) tDDS = 1 7 x 11f (OSC) + 40 JLS[f(OSC) =32.768kHZ]tCY =610JLstsw = 61JLstDV = 122JLstDIV = 264JLstDDS = 558.5JLstWHCLOCK(OSCo)SYNC_%tpDtCY"''----SYNCtswKtDIVtDVnPA,PBInput mode INVALID VALID INVALIDtDDSPA,PBOutput modeOLD DATANEW DATA86

-------------------------... MSM5847.DC CHARACTERISTICS(Voo =3V±10%, Ta =-20 - +70°C)Parameter Symbol ConditionMin. Typ. Max.Unit"H" Input Voltage VIH -"L" Input Voltage VIL -V,*1 Applicable toCommon, Segment Common 1-3Output Voltage V2 Segment 0-23"H" Output Voltage*2 *3 *4 VOH 10 = 1JLA"L" Output Voltage *2 VOL 10 = 1JLA"L" Output Voltage *3 *4 VOL 10=1 mAOSCo Input Current IIH/IIL VI=VOOIVI=OVRESET Input Current IIH/IIL VI=VOOIVI=OVVaV3VOO - --0.2- - 0.30 - 0.2113 VOO - 113 VOO-0.2 +0.22/3 VOO - 2/3 VOO-0.2 +0.2VOO - VOO-0.2VOO - --0.2- - 0.2- - 1.0- - 5/-5- - 1/-15VVVVVVVVVJLAJLACurrent Consumption 100VOO=3Vf = 32.768kHz,no load- 50 100JLANote: *1 Applicable to PAO-2, PBo-3, SYNC and 34 Hz*2 Applicable to PA3*3 Applicable to BUZZERLevel of Output Voltage for Common, Segment,.....-...,------------V3----V2-----V,L--~-----Vo87

eMSM5847e'--------------------------------------------------i,TYP. Output Current (lOH) vs OutputVoltage (VOH) for High-level StateTYP. Output Current (lOL) vs OutputVoltage (VOL) for Low-level State-2.0-·1.8-1.6-1.4-;;( -1.2..s::c -1.0o- -0.8-0.6-0.4-0.2ok34 Hz terminal'\SYNC terminal~I\C6M r\terminal \SEG'~\(Voo=3V, Ta=25°C)PA, PB terminalo 1 2 3 4 5 6 7 8 9 10VOH (V)-;;(..s..J.91098765432I__PA3 terminal(VOO=3V, Ta=25°C)1/A/ 10- BUZZER termi~alIJ34 Hz ttminal I J~. I I.- PAa - 2, PBa - 3, SYNC term ina~ ~ COM, SEG terminal I I I Io 1 2 3 4 5 6 ·7 8 9 10VOL (V)TYP. Output Current (11, 12l vsOutput Voltage (V 1, V 2) for Middle-level State252015~ 10 5..::: 0-5-10-15-20-25/IIV1/ /(Voo=3V, Ta=25°C)Iv,/I II COM, SEG terminal/ I/ /I ilIo 1 2 3 4 5 6 7 8 9 10V " V2 (V)S0.910m5m1m500/1100/150/110/15/1Supply Current (100) vsSupply Voltage (Voo)./(Ta=25°C, No Load)f(OSC)I./ o Hz./32.768 kHz100no 1 2 3 4 5 6 7 \8 9 10VOO (V)88

OlMS-SO/60 SERIES

OKI semiconductorMSM5052CMOS 4 BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITHTEMPERATURE DETECTION CIRCUIT AND LCD DRIVERGENERAL DESCRIPTIONThe OKI MSS5052 is a low-power and high-performance single-chip microcontroller employingcomplementary metal oxide semiconductor technology.'lntegrated onto a single chip are a 4 bit ALU,18K bits of mask programmable ROM, 248 bits of data RAM, crystal oscillator, voltage doubler, timer,LCD driver, input port, output port and CR oscillator for temperature detection.The MSM5052 is widely used in electronic products requiring low power operation, for example,thermometer and clinical thermometer with a time piece.FEATURES• Low Power Consumption 3 /LA Typical• 1280 x 14 Internal ROM• 62 x 4 Internal RAM• 4 x 2 Input Port• 5 Output Port• 4 x 4 Key Matrix Input (K1-K4, M1-M4)• 26 LCD Driver(112 Duty, 112 Bias, 52 Segment)• 42 Instructions• 1.5 V Operating Voltage• 32.768 kHz Crystal Oscillator• 122.1 I1-s Instruction Cycle• -20 to 75°C Operating Temperature• 61 pad dieFUNCTIONAL BLOCK DIAGRAMBoA3-AOLoK,IK4s,s,~======~~~:~~~~=Jll~~]~~~~~ DISPLAYINSTRUC·liONDECODERLATCHandDRIVERSEGMENTOUT1\SEGMENTOUT26COMlCOM2TH R' C IN!! I I ! I ! ! J I r91

• MSM5052 .----------------------------------------------~~~LOGIC SYMBOLCHIP PAD LAYOUTSECMENTOUTOSCILLATION [OSC3INPUT PORT [ LCD DRIVER~ OSC2'(S1~S4)SEGMENTOSClOUT26INPUT PORT [COM1(K1 ~K4) COM2JOUTPUT PORT [-(Ml-M4)MlOSCILLATIONM2-- CIRCUIT FORM3M4TEMPERATUREOUTPUT PORT LD DETECTIONRESET ACBUZZER OUTPUTVDDPOWER SOURCE [ _VSS1VSS2VCPVCM-J TESTVDDACVCPVCMSlS2S3S4CHIP SIZE 4.77 x 4.36 (mm)PIN DESCRIPTIONDesignationVDDCircuit ground potentialVSS l Power source (-l.S V)FunctionVSS 2 Power source for LCD driver (-3.0 V)This terminal is connected to VDD terminal through a 0.1 /-tF capacitor.VCP, VCMOSC1,OSC3Booster capacitor connection terminalsVCP terminal is connected to VCM terminal through a 0.1 /-tF capacitor.Input and output terminals of oscillator inverter,32.768 kHz crystal is connected to these terminals.Tl -TS Terminals to test internal logic, Tl - T3 and TS are pulled down to VSS 1•T4 is output. Test pins must be normally open.AC Terminal to clear internal logic pulled down to VSS 1•After power is turned on, the MSMSOS2 must be reset by this terminal.BDTH,R,C,'INBuzzer outputTerminal to CR oscillation circuit for temperature detection,fundamental resistor, thermistor, capacitor connection terminal.92

______________________________________________ --e. MSM5052.FUNCTIONAL DESCRIPTIONA block diagram of the MSM5052 is given onpage 91. Each block of logic will be brieflydiscussed. For more information, please refer tothe MSM5052 user's manual.Program ROMThe MSM5052 addresses up to 1.25 Kwords of internal mask programmable ROM.Each word consists 0.1 14 bits and allinstructions are one word. The instructions arerouted to a programmed logic array whichgenerates the signals necessary for control oflogic.Data RAMData is organized in 4-bit nibbles. Internaldata RAM consists of 62 nibbles.The RAM is addressed by page address andcolumn address. Normally page address isspecified with page register, but directaddressing is available in Page O.Column address is directly addressed byoperand of various instructions.. ALUThe ALU performs 4-bit parallel operation onRAM and ACC contents, or RAM contents andan immediate digit. It sets or resets the flags (Z,C) depending on the condition.P.rogram Counter (PC)The program counter is 11 bits wide andspecifies the address of the program ROM.The PC is incremented by one everyexecution of the instruction, and then specifiesthe next instruction to be executed. However, thecontents of the PC are rewritten by the executionof the Jump or Branch instruCtion.There is no boundary in the ROM, so a Jumpor Branch instruction can be put anywhere in theROM.Input Port (K1 - K4)The input port (K1 - K4) is a 4 bit parallelinput port. Each pin of the port is pulled down toVSS1 by an internal resistor, and the status ofthe port is fetched by an input instruction.Output Port (M1 - M4)The output port (M1 - M4) is a 4 bit paralleloutput port. This port consists of data latchesand buffers, and the contents of the data latchesare rewritten by an output instruction.Output Port (LD)The output port (LD) is single output port.This terminal is used for loading of M1 to M4data.Display FunctionThe MSM5052 is provided with a segmentoutput terminal which can directly drive a 1/2bias, 112 duty LCD and the common drive outputterminal COM1 and COM2.The segment drive circuit consists of thedisplay data latch, multiplexer and driver. If thedata is sent to the display data latch with adisplay instruction, the LCD drive waveform isoutput to the segment drive output terminal.Time BaseThe time base for the CPU is provided byconnecting a 32.768 kHz crystal to the OSC1and OSC3 pins. One machine cycle is 122.1 p.s.A hardware divider up to 1 Hz is providedenabling programs to implement a clock functionby counting signals between 16 and 1 Hz.Temperature Detection CircuitThe temperature detection circuit iscomposed of an external thermistor, afundamental resistor, a capacitor and a built-inCR oscillation circuit.Two types of temperature measurementcircuit, as shown below, are available,Input/Output PortInput Port (51 - 54)The input port (S1 - S4) is a 4 bit parallel RMSM5052input port. Each pin of the port is pulled down toThermometer(R. TH series)VSS1 by an internal resistor, and the status ofthe port is fetched by an input instruction. TH THRMSM5052ClinicalThermometer(R. TH parallel)93

• MSM5052 .--------------------------ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Limits UnitSupply Voltage 1 VOO-VSS, Ta =25°C -0.3 to +2.0 VSupply Voltage 2 VOO - VSS 2 Ta =25DC -0.3 to +4.0 VInput Voltage VIN, Ta =25DC VSS, -0.3 to +0.3 VStorage Temperature Tstg -55 to 125 °cOPERATING CONDITIONSParameter Symbol Limits UnitOperating Voltage VOO-VSS, 1.25 to 1.65 VOperating Temperature Topr -20to 75 DCoParameterDC CHARACTERISTICS(VOO =OV, VSS, = -1.55V, VSS2 = -3.OV, CI = 30kO, Ta = 25°C)LimitsSymbol Condition UnitMin. Typ. Max.Power supply current 1 100, Temperature sampling off - 3.0 - /LAPower supply current 2 1002 Temperature sampling on - 100 - /LAOscillation start Within 10 seconds 1.45 - - Vvoltage-VOSC VSS, terminalOutput current 1COMIOH, VOH, =-0.2V -4 - -10M, YOM, =VSS, ± 0.2V4/-4 - - /LAIOL, VOL, =-2.8V 4 - -Output current 2 IOH2 VOH2=-0.2V -0.4 - -SEGMENTIOL2 VOL2 =-2.8V 0.4 - -Output current 3 IOH3 VOH3 =-0.4 V -400 - -C.R.THIOL3 VOL3 = -1.15V 400 - -/LA/LAOutput current 4 IOH. VOH. =-0.4V -100 - "-M1-M. LOIOL. VOL. = -1.15V 10 - -/LAOutput current 5 IOH5 VOH5= -0.4V -50 - -500-SO/LAIOL5 VOL5 = -1.15V 4 - -Input current IIH, VIH, =OV 1 10 100S1-S4 K1-K4IlL, VIL, = -1.55V - - ..,..0.2/LAOscillator built-incapacitorCO- 25 - pF94

------------------------~----------------------~. MSM5052·MEASURING CIRCUITr---.:-.,....-!INC+-.JVI1\rl RR'--JW"v-ITHTHVCPVCMOSC3OSClC2ClX-talClC2,C3C4X-talR,TH20pFO.l,..F3000pF32.768 kHz10KOTYPICAL APPLICATIONLCDTHTHRR. INCOSClC2 0 (CO=25pF)32.768 kHz OSC3C3VCPMSM5052M,HI } Alarm outputM. 1---- LOM.LOBOVSS,VOOAC*1R, =33 kOR.= 20 kOTH 40BT-540KO ±1 0% at 25°CB=3550±2%C,=680pFC.=5 -35pFC3=0.1,..FC.=O.l,..F*1. Inner switch or pad on PCB*2. Bonding option12345--'-Thermomet~~19n"gesecondsam linThermomet~~ll 0-second sam lingW~~JP~t~~~ alarmrJI~J~r~~~e alarmClock95

eMSM5052 e----------------------------------------------------DESCRIPTION OF INSTRUCTIONSMnemonicInstruction Code131211109 8 7 6 5 4 3 2 1 0OperationADDACC,AP 0 0 0 0 0 P 0 1 0 0 A AP - (AP) + (ACC)ADD #D,AP 0 1 1 0 0 P D A AP-(AP) - DADCAP 0 0 0 0 0 P 0 1 0 1 A AP - Decimal adjust{(AP) + (ACC) + (C)lc: SUB ACC, AP 0 0 0 0 1 P 0 1 0 0 A AP - (AP) - (ACC)0~(])a.0():;SUB #D,AP 0 1 1 0 1 P D A AP - (AP) - DSBCAP 0 0 0 0 1 P 0 1 0 1 A AP - Decimal adjust{(AP) - (ACC) - (C)lE CMPACC,AP 0 0 0 0 1 P 1 1 1 0 A (AP) -. (ACC):5~ CMP #D,AP 0 1 0 1 1 P D A (AP) - DINCAP 0 1 1 0 0 P 0 0 0 1 A AP -(AP) + 1DECAP 0 1 1 0 1 P 0 0 0 1 A A

OKI semiconductorMSM5054CMOS 4 BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITHLCD DRIVERGENERAL DESCRIPTIONThe OKI MSM5054 is a low-power, high-performance single-chip microcontrolier employingcomplementary metal oxide semiconductor technology. Integrated onto a single chip are 4-bit of ALU,14K bits of mask programmable ROM, 248 bits of data RAM, crystal oscillator, voltage doubler, timer,LCD driver, input port and output port.The MSM5054 is widely used in electronic products requiring low power operation, for example,Clocks, Timers and Games.FEATURES• Low Power Consumption 3 ,."A Typical• 1 024 x 14 Internal ROM• 62 x 4 Internal RAM• 6 Input Port• 4 Output Port'• 4 x 4 Key Matrix Input (S,-S", M,-M4)• 44 LCD Driver .(1/2 Duty, 1/2 Bias, 88 Segment)• 40 Instructions• 1.5 V or 3 V Operating Voltage(Masking Option)• 32.768 kHz Crystal Oscillator• 122.1 P.s Instruction Cycle• -20 to 75°C Operating Temperature• 74 pad dieFUNCTIONAL BLOCK DIAGRAM80-----1A3-AOLOSEGMENTOUTlSSEGMENTOUT44COM,COM2INSTRUC·TIONDECODERI I I I I I111111197

·MSM5054·------------------~--------~----------------------LOGIC SYMBOLCHIP PAD LAYOUTCOM1OSCILLATION [ SEGME;NT N.COUT,VDDXTINPUT PORT [(51 ..... 54)INPUI~;~:2j [SEGMENTOUT44S,COM,M,S,COM,OUTPUT PORT [ M,VEE(M,-M4) M,BUZZERBD OUTPUTM4K,RESETACLD LAMP OUTPUT K,vooVSS 1 M,_rn [ VSS2 32HzSOURCE VEE T,VCP T,VCM T, lTESTM,T4T,M.COM2SEG1SEGMENT OUTPUTCHIP SIZE 4.68 x 4.23 (mm)PIN DESCRIPTIONDesignationVDDCircuit ground potentialVSS, Power source (-1 .S V)FunctionVSS 2 Power source for LCD driver (-3.0 V)This terminal is connected to VDD terminal through a 0.1 /LF capacitor.VEE Power source for internal logic (-1.S to -3.0 V)This terminal is connected to VDD terminal through a 0.1/LF capacitor.VCP, VCMXT,XTBooster capacitor connection terminalsVCP terminal is connected to VCM terminal through a 0.1 /LF capacitor.Input and output terminals of oscillator inverter,32.768 kHz crystal is connected to these terminals.T,-T5 Terminals to test internal logic, T, - T3 and T5 are pulled down to VSS,.T 4 is output. Test pins must be normally open.ACBDLDTerminal to clear internal logic pulled down to VSS,.After power is turned on, the MSMSOS4 must be reset by this terminal.Buzzer outputLamp output98

-----------------------------------------------------. MSM5054 •FUNCTIONAL DESCRIPTIONA block diagram of the M8M5054 is given onpage 97. Each block of logic will be brieflydiscussed. For more information, please refer tothe MSM5054 user's manual.Program ROMThe MSM5054 addresses up to 1 K word ofinternal mask programmable ROM. Each wordconsists of 14 bits, and all instructions are oneword. The instructions are routed to aprogrammed logic array which generates thesignals necessary for control of logic.Data RAMData is organized in 4-bit nibbles. Internaldata RAM consists of 62 nibbles.The. RAM is addressed by page address andcolumn address. Normally page address isspecified by the page register, but directaddreSSing is available in Page O.Column address is directly addressed by theoperand of various instructions.ALUThe ALU performs 4-bit parallel operation ofRAM and ACC contents, or RAM contents andan immediate digit. It sets or resets the flags (Z,C) depending on the condition.Program Counter (PC)The program counter is 10 bits_ wide andspecifies the address of the program ROM.The PC is incremented by one at everyexecution of the instruction, and then specifiesthe next instruction to be executed. However, thecontents of the PC are rewritten by the executionof the Jump or Branch instruction.There is no boundary in the ROM, so theJump or Branch instruction can be put anywherein the ROM.Input/Output PortInput Port (81 - 84)The input port (81 - S4) is a 4-bit parallelinput port. Each pin of the port is pulled down toVSS1 by an internal resistor, and the status ofthe port is fetched by the SWITCH instruction.Input Port (K1 - K4)The input port (K1 - K2) is a 2-bit parallelinput port. Each pin of the port is pulled down toVSS1 by an internal resistor, and the status ofthe port is fetched by the KSWITCH instruction.Output Port (M1 - M4)The output port (M1 - M4) is a 4-bit paralleloutput port. This port consists of data latchesand buffers, and the contents of the data latchesare rewritten by a matrix instruction.Display FunctionThe MSM5054 is provided with a segmentoutput terminal which can directly drive a 1/2bias, 112 duty LCD, and the common driveoutput terminal COM1 and COM2. The segmentdrive circuit consists of the display data latch,multiplexer and driver. If the data is sent to thedisplay data latch with a display instruction, theLCD drive waveform is output to the segmentdrive output terminal.Time BaseThe time base of the CPU is provided byconnecting a 32.768 kHz crystal to the XT andXT pins. One machine cycle is 122.1 '"S.A hardware divider of up to 1 Hz is provided,enabling programs to implement a clock functionby counting signals between 32 and 1 Hz.99

·MSM5054.------------------------------------------------~ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Limits UnitSupply Voltage 1 VOO -VSSl Ta = 25°C -0.3 to +2.0 VSupply Voltage 2 VOO-VSS2 Ta = 25°C -0.3 to +4.0 VSupply Voltage 3 VOO-VEE Ta = 25°C .-0.3 to +4.0 V,Input VoltageVINlTa=:25°C VSS 1-O.3 to +0.3 VStorage Temperature Tstg -55 to 125 °cOPERATING CONDITIONSParameter Symbol Limits UnitOperating Voltage VOO-VSSl 1.25 to 1.65 VOperating Temperature Topr -20 to 75 °cDC CHARACTERISTICS(VOO =OV, VSS 1' VEE = -1.55V, VSS2 = -3.0V, CI = 30kO, Ta = 25°C)LimitsParameter Symbol Condition UnitMin. Typ. Max.Power supply current 100-Oscillation startvoltageOutput current 1COM- 3.0 - /LA-VOSC . Within VSS 1 terminal5 seconds 1.45 - - VIOHl VOHl =-0.2V -4 - -IOMl VOMl =VSSl ± 0.2V 4/-4 - - /LAlOLl VOL1=-2.8V 4 - -Output current 2 IOH2 VOH2=-0.2V -0.4 - -SEGMENTIOL2 VOL2=-2.8V 0.4 - -Output current 3 IOH3 VOH3=-0.4V VSS 1= -1.25V -50 - -500SOVEE =-1.25VIOL3 VOL3= -0.8V VSS2=-2.4V 2.5 - 7.5Output current 4 IOH4 VOH4 = ,-0.55V VSS l = -1.25V -21 - -83LOVEE=-2.4VIOL4 VOL4 = -1.15V VSS2=-2.4V 1 - -Output current 5 IOH5 VOH5=-0.5V -100 - -Ml-M4IOL5 VOL5=-1.0V 1.5 - 7.5Input current 1 IIHl VIHl =OV 1 10 50Sl-S4IILl VILl = -1.55V - - -0.2Input current 2 IIH2 VIH2=OV 2.5 6 12Kl,K2IIL2 VIL2 = -1.55V - - -0.2Oscillator built-incapacitor CO - 20 - pF/LA/LA/LAJ.lA/LA/LA100

---------------------------------------------------.4. MSM5054 •MEASURING CIRCUITVCPVCMXl'XT '------"'r-CaXTAL0.1 j.tF30pF32.768kHzTYPICAL APPLICATIONLCDLampSEGMENTS COM 2LD 1-----[X-tal c::::::IXT(CD=20pF)MSM5054BD I----+--fVSS11-----T­VDDI----~ACVSS 2 VEE5 - 35pF0.1j.tF1.5V20mH101

• MSM5054 .----------------~---------DESCRIPTION OF INSTRUCTIONSInstruction CodeMnemonic131211109 8 7 6 5 4 3 2 1 0Operation,ADDACC,AP 0 0 0 0 0 P 0 1 0 0 A AP +- (AP) + (ACC)ADD#D,AP 0 1 1 0 0 P D A AP+-(AP) + DSUB ACC,AP 0 0 0 0 1 P 0 1 0 0 A AP +- (AP) - (ACC)c:.2 SUB#D,AP 0 1 1 0 1 P D A AP+-(AP) - D;;;...Q)a.0ADJUST N, AP 1 1 0 0 0 P N + 1 A AP +- N adjust {(AP)}0 CMP ACC, AP 0 0 0 0 1 P 1 1 1 0 A (AP) - (ACC)~E CMP#D,AP 0 1 0 1 1 P D A (AP)-D:5INCAP 0 1 1 0 0 P 0 0 0 1 A AP +- (AP) + 1~DECAP 0 1 1 0 1 P 0 0 0 1 A A+- (AP)-1XOR ACC, AP 0 0 0 0 0 P 0 1 1 1 A AP +- (AP)Ir(ACC)XOR#D,AP 0 1 1 1 1 P D A AP +- (AP)-'

________________________________________________ __e_ MSM5054-DESCRIPTION OF INSTRUCTIONS (CONT.)MnemonicInstruction Code131211109 8 7 6 5 4 3 2 1 0OperationJMPAdrs1 0 0 0 a 9 a 8 a 7 a 6 a 5 a4 a3 a2 a 1 ao PC --AdrsJMP@AP 0 0 0 0 0 P 1 1 0 1 A PC -- (PC) + (AP) + 1JMPIO@AP 0 0 0 0 1 P 1 1 0 1 A PC -- (PC) + (AP)/\ 7H } +1c. BEQ +nE:::I BZE +n...,BNE +nBNZ +n0 0 0 1 1 0 0 1 0 n4 n3 n2 n1 noPC -- (PC)+n+1: if Z=l0 0 0 1 1 0 1 1 0 n4 n3 n2 n1 no PC -- (PC)+n+1, if z=oBCS +n 0 0 0 1 1 0 0 0 0 n4 n3 n2 n1 no PC -- (PCl+n+1, if C=lBCC +n 0 0 0 1 1 0 1 0 0 n4 n3 n2 n 1 no PC -- (PC)+n+1, if C=OSWITCHAP 1 1 0 1 0 P 0 0 0 1 A AP --INPUT PORT (S1 - S4)KSWITCHAP 1 1 0 1 0 P 0 0 1 0 A AP --INPUT PORT (K 1 - K2)MATRIXAP 1 1 0 1 1 P 0 0 1 0 A OUTPUT PORT (M 1 - M4)"S --(AP)c."S MATRIXMn 0 0 0 1 0 0 0 0 1 o M4M3M2M1 OUTPUT PORT (M 1-M4)0:;:: -- Mn (n=l, 2, 3, 4).:::1c..E BUZZER freq., 0 0 0 1 0 0 1 1 0 0 b3 b2 b1 bo Freq -- freq, Mreg - soundsoundBuzzer startBSO 0 0 0 1 0 0 1 1 0 0 0 o 0 0 Buzzer stopLAMP ON/OFF 0 0 0 1 0 0 0 0 0 1 0 o b1 bo LD ON/OFFDSP digit, AP 0 0 1 0 0 P digit A Digit -- (AP), (ACC)>- FORMATAP 1 1 0 1 1 P 0 0 1 1 A FMT reg. -- (AP)a. '"1/1 FORMATN 0 0 0 1 0 0 0 0 1 1 N FMTreg.--N6DSPF digit, AP 0 0 1 1 0 P digit A Digit -- (AP) via tableHALT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 HaltINTENAB 0 0 0 1 0 0 1 0 1 1 1 0 0 032/16 0 0 0 1 0 0 0 1 0 0 0 0 1 0Enable timer1/1QjINTDSAB 0 0 0 1 0 0 1 0 1 1 0 1 0 0Disable timer.&: 32/16 0 0 0 1 0 0 0 1 0 0 0 0 0 1001:1 INTMODEAP 1 1 0 1 0 P 0 1 0 0 A AP --Interrupt mode"0 ...PAGEAO 1 1 0 1 1 0 0 1 0 1 A Preg --(AO)E0C) PAGEN 0 0 0 1 0 0 0 1 0 1 N Preg --N'::>D.. RATEAP 1 1 0 1, 0 P 1 0 0 1 A AP - DIVIDER (8 Hz-1 Hz)C)RSTRATE 0 0 0 1 0 0 1 0 0 0 1 0 0 0 DIVIDER (8 Hz-1 Hz) -- 0BACKUP 0 0 0 1 0 0 0 0 0 1 b3 b2 0 0 Backup ON/OFFON/OFFNOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation103

OKI semiconductorMSM5055CMOS 4 BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITHLCD DRIVERGENERAL DESCRIPTIONThe OKI MSM5055 is a low-power, high-performance single-chip microcontroller employingcomplementary metal oxide semiconductor technology. Integrated onto a single chip are 4 bits ofALU, 25K bits of mask programmable ROM, 384 bits of data RAM, crystal oscillator, voltage doubler,timer, LCD driver, input port, output port and interface circuit for voice LSI (MSM6212).The MSM5055 is widely used in electronic products requiring low power operation, for example,multi-functioned watches, voice synthesizer watches and games.FEATURES• Low Power Consumption 3,..A Typical• 1792 x 14 Internal ROM• 96 x 4 Internal RAM• 4 x 2 Input Port• 4 X 1 Output Port• 4 X 4 Key Matrix Input (K1-K4, M1-M4)• 60 LCD Driver(112 Duty, 112 Bias, 120 Segment)• 42 Instructions• 1.5 V or 3 V Operating Voltage(Masking Option)• 32.768 kHz Crystal Oscillator• 122.1,..S Instruction Cycle• -20 to 75°C Operating Temperature• 94 pad dieFUNCTIONAL BLOCK DIAGRAMBD ___ -+DATA RAM96 word x 4 bitLDM1IM4LOK1\K4SEGMENToun\SEGMENTOUT60COMlCOM2INsrRUC­TIONDECODE1792 word x 14 bitj j j I j iAC T1 T2 T3 T4 T5104

________________________________________________ -4. MSM5055 •LOGIC SYMBOLCHIP PAD LAYOUTOSCILLATION ( _________ NINPUT PORT [ ~~(81-84) - 83S4INPUT PORT [(K1-K41 -OUTPUT PORT [(M1-M41LOADRESETM'M2M3M4LOACSEGMENTDUnSEGMENTOUT6DCOM1COM2LCD DRIVERBO BUZZER OUTPUTLD LAMP OUTPUTXTOUT ~ 8D~8b-fULSEAC'J RESETPOWER SOURCE -~~g1 VSS2[ ~VEET i3'2 J TEST- VCP T4VGMTSL-__ ---lSEGM~NT OUTPUTCHIP SIZE 5.49 x 4.71 (mm)PIN DESCRIPTIONDesignationVDDCircuit ground potentialVSS, Power source (-1.S V)FunctionVSS 2 Power source for LCD driver (-3.0 V)This terminal is connected to VDD terminal through a 0.1 p,F capacitor.VEE Power source for internal logic (-1.S to -3.0 V)This terminal is connected to VDD terminal through a 0.1 p,F capacitor.VCP, VCMXT,XTBooster capacitor connection terminalsVCP terminal is connected to VCM terminal through a 0.1 p,F capacitor.Input and output terminals of oscillator inverter,32.768 kHz crystal is connected to these terminals.T1 -TS Terminals to test internal logic, T1 - T3 and TS are pulled down to VSS ,.T4 is output. Test pins must be normally open.AC Terminal to clear internal logic pulled down to VSS ,.After power is turned on, the MSMSOSS must be reset by this terminal.BDLDLOAC2XTOUTBuzzer outputLamp outputLoad data terminal of M1 to M4Reset terminal for external circuitClock output for external circuit105

• MSMSOSS·,--------------------------------------------------FUNCTIONAL DESCRIPTIONA block diagram of the MSM5055 is given onpage 104. Each block of logic will be brieflydiscussed. For more information, please refer tothe MSM5055 user's manual.Program ROMThe MSM5055 addresses up to 1 K word ofinternal mask programmable ROM. Each wordconsists of 14 bits, and all instructions are oneword. The instructions are routed toaprogrammed logic array which generates thesignals necessary for control of logic.Data RAMData is organized in 4-bit nibbles. Internaldata RAM consists of 62 nibbles.The RAM is addressed by page address andcolumn address. Normally page address isspecified by the page register, but directaddressing is available in Page o.Column address is directly addressed by theoperand of various instructions.ALUThe ALU performs 4-bit parallel operation ofRAM and ACC contents, or RAM contents andan immediate digit. It sets or resets the flags (Z,C) depending on the condition.Program Counter (PC)The program counter is 10 bits wide andspecifies the address of the program ROM.The PC is incremented by one at everyexecution of the instruction, and then specifiesthe next instruction to be executed. However, thecontents of the PC are rewritten by the executionof the Jump or Branch instruction.There is no boundary in the ROM, so theJump or Branch instruction can be put anywhereinthe ROM.Input/Output PortInput Port (81 - 84)The input port (S1 - S4) is a 4-bit parallelinput port. Each pin of the port is pulled down toVSS1 by an internal resistor, and the status ofthe port is fetched by the SWITCH instruction.Input Port (K 1 - K4)The input port (K1 - K2) is a 2-bit parallelinput port. Each pin of the port is pulled down toVSS1 by an internal resistor, and the status ofthe port is fetched by the KSWITCH instruction.Output Port (M1 - M4)The output port (M1 - M4) is a 4-bit paralleloutput port. This port consists of data latchesand buffers, and the contents of the data latchesare rewritten by a matrix instruction.Display FunctionThe MSM5055 is provided with a segmentoutput terminal which can directly drive a 1/2bias; 112 duty LCD, and the common driveoutput terminal COM1 and COM2. The segmentdrive circuit consists of the display data latch,multiplexer and driver. If the data is sent to thedisplay data latch with a display instruction, theLCD drive waveform is output to the segmentdrive output terminal.Time BaseThe time base of the CPU is provided byconnecting a 32.768 kHz crystal to the XT andXT pins. One machine cycle is 122.1 ILs.A hardware divider of up to 1 H;z is provided,enabling programs to implement a clock functionby counting signals between 32 and 1 Hz.106

--------------------------------~----~-------------. MSM5055 •ABSOLUTE MAXIMUM RATINGS. Parameter Symbol Conditions Limits UnitSupply Voltage 1 VDD -VSS, Ta = 25°C -0.3 to +2.0 VSupply Voltage 2 VDD - VSS2 Ta = 25°C -0.3 to +4.0 VSupply Voltage 3 VDD -VEE Ta = 25°C -0.3 to +4.0 VInput Voltage VIN, Ta = 25°C VSS, -0.3 to +0.3 VStorage Temperature Tstg -55 to 125 DCOPERATING CONDITIONSParameter Symbol Limits UnitOperating Voltage VDD-VSS, 1.25 to 1.65 VOperating Temperature Topr -20 t6 75 °cDC CHARACTERISTICS(VDD =OV, VSS" VEE = -1.55V, VSS2 = -3.0V, CI = 30kfl, Ta = 25DC)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Power supply current IDD - 3.0 - /LAOscillation start -VOSC Within 5 seconds 1.45 - - VvoltageVSS, terminalOutput current 1COMIOH, VOH, =-0.2V -4 - -10M, VOM, =VSS, ± 0.2V 4/-4 - - /LAIOl, VOL, =-2.8V 4 - -Output current 2 IOH2 VOH2 =-0.2V -0.4 - -SEGMENTIOl2 VOl2 =-2.8V 0.4 - -Output current 3 IOH3 VOH3 =-0.5V -10 - -AC2 lOAD, XTOUTIOl3 VOl3 = -1.05V 10 - -Output current 4 IOH. VOH.=-0.5V -100 - -M1-M4IOl. VOL. =-1.0V 1.5 - 12.7Output current 5 IOHs VOHs = -0.55V Vss,=-1.25V -21.6 - ':"83VEE =-2.4VlDtOls VOls=-1.15V VSS 2=-2.4V 1 - -Output current 5 IOHa VOHa =-O.4V VSS, =VEE -50 - -SD=-1.25VIOHa VOla =-0.8V VSS2=-2.4V - 5 .-Input current 1 IIH, VIH, =OV 1 10 50S,-S4Ill, Vll,=-1.55V - - -0.2Input current 2 IIH2 VIH2=OV 2.5 6 ~12K,-K.IIl2 VIl2 = -1.55V - - -0.2Oscillator built-incapacitorCD/LA/LA/LA/LA/LA/LA/LA- 20 - pF.107

e MSM5055ee--------------------------------------------------MEASURING CIRCUITVCPVCMXTXTC3XTALC1 .C2.C3 0.1 J.tFC4 30 pFX-tal 32.768 kHzTYPICAL APPLICATIONLCDLampSI-L COM 1S2 -L SIS3 -LS2S3S4 -L...S4XT(CD=20pF)SEGMENTSMSM5055COM2LDBDVSS 1VDDC1ACr5 - 35pF0.1,uF1.5V20mH108

________________________________________________ --e. MSM5055.DESCRIPTION OF INSTRUCTIONSMnemonicInstruction Code131211109 8 7 6 5 4 3 2 1 0OperationADD ACC,AP 0 0 0 0 0 P 0 1 0 0 A AP - (AP) + (ACC)ADD#D,AP 0 1 1 0 0 P D A AP-(AP) +DSUB ACC,AP 0 0 0 0 1 P 0 1 0 0 A AP - (AP) - (ACC)c:.2 SUB#D,AP 0 1 1 0 1 P D A AP-(AP) -Diiiloa.0t)ADJUSTN,AP 1 1 0 0 0 P N + 1 A AP - N adjust {(AP)}CMPACC,AP 0 0 0 0 1 P 1 1 1 0 A (AP) - (ACC)~ECMP#D,AP 0 1 0 1 1 P D A (AP) -D:;;INCAP 0 1 1 0 0 P 0 0 0 1 A AP-(AP) + 1~DECAP 0 1 1 0 1 P 0 0 0 1 A A-(AP) -1XOR ACC, AP 0 0 0 0 0 P 0 1 1 1 A AP -(AP) -V- (ACC)XOR#D,AP 0 1 1 1 1 P D A AP - (AP) -V- DBITACC,AP 0 0 0 0 0 P 1 1 1 0 A (AP) V (ACC)c: BIT#D,AP 0 1 0 1 0 P D A (AP)VD0~ BISACC,AP 0 0 0 0 0 P 0 1 1 0 A APV (ACC)lo· a.0 BIS#D,AP 0 1 0 0 0 P D A (AP)VD-iii BICACC,AP 0 0 0 0 1 P 0 1 1 0 A AP A (ACC)BIC#D,AP 0 1 0 0 1 P D A AP AD;: ASRAP 0 0 0 0 0 P 0 0 1 1 A C(C) O-(AP)::::J.s::(f)ASlAP 0 0 0 0 1 P 0 0 1 1 A (C)-(AP)-OClZ 0 0 0 0 0 0 1 0 1 0 0 0 0 0 z-oc:0 ClC 0 0 0 0 0 0 1 0 0 1 0 0 0 0 C-O~lo ClA 0 0 0 0 0 0 1 0 1 1 0 0 0 0 Z-O,C-Oa.0SEZ 0 0 0 0 1 0 1 0 1 0 0 0 0 0 Z-lClt1lu:: SEC0 0 0 0 1 0 1 0 0 1 0 0 0 0 C-1SEA 0 0 0 0 1 0 1 0 1 1 0 0 0 0 Z-l,C-lMOVACC,AP 1 1 1 1 0 P 0 0 0 0 A AP-(ACC)loU; MOVACC,AX 1 1 1 1 0 0 0 X A AX-(ACC)c:g MOV#D,AP 0 1 1 1 0 P D A AP-DS MOVAP,ACC 1 1 1 1 1 P 0 0 0 0 A ACC-(AP)t1l0MOVAX,ACC 1 1 1 1 1 0 0 X A ACC-(AX)JMP adrs1 0 o a,o a 9 as a7 a 6 a 5 a. a3 a 2 a, ao PC -adrsa.E::l...,JMP@AP 0 0 0 0 0 P 1 1 0 1 A PC - (PC) + (AP) + 1JMPIO@AP 0 0 0 0 1 P 1 1 0 1 A PC - (PC) + {(AP) A 7H} +1BEQ +n0 0 0 1 1 0 0 1 0 PC +- (PC)+n+1, ifZ=lBZEn. n3 n2 n, no+n109

., • .MS.M5055 .-----------------,....------'---DESCRIPTION OF INSTRUCTIONS (CONT.)MnemonicInstruction Code131211109 8 7 6 5 4 3 2 :1 0OperationBNE +n0 0 0 1 1 0 1 1 0 n4, PC +- (PC)+i1+1 , if Z=Oa. BNZn3+nn2 n1 noE::s BCS +n 0 0 1 1 0 0 0 0 n 4 n3 n2 n1 no PC - (PC)+n+1, if C=l...,0BCC +n 0 0 0 1 1 0 1 0 0 n 4 n3 n2 n1 no PC - (PC)+n+1, if C=OSWITCHAP 1 1 0 1 0 P 0 0 0 1 A)AP -INPUT PORT (S1 - S4)KSWITCHAP 1 1 0 1 0 P 0 0 1 0 A AP -INPUT PORT (K1 - K4)MATRIXAP 1 1 0 1 1 P 0 0 1 0 A OUTPUT PORT (M1 ....;, M4).... -(AP)::s.s- MATRIXMn 0 0 0 1 0 0 0 0 1 0 M4M3M2M1 OUTPUT PORT (M1 -M4)::s0- Mn (n=l, 2, 3, 4):;::.::sa.XTCPON/OFF 0 0 0 1 0 0 1 0 0 0 o 0 b1 bo XTOUT ON/OFF-= FREON 0 0 0 1 0 0 1 1 0 1 N Freq -NBUZZER sound 0 0 .0 1 0 0 1 1 0 0 b3 b2 1 0 Mreg - sound, Buzzer startBSO 0 0 0 1 CY 0 1 1 0 0 0 0 0 0 Buzzer stopLAMP ON/OFF 0 0 0 1 0 0 0 0 0 1 0 o b1 bo LDON/OFFDSP digit, AP 0 0 1 0 0 P digit A Digit (Low part) - (AP) , (ACC)DSPHdigit, AP 0 0 1 0 1 P digit A Digit (High part) ...;. (AP), (ACC)FORMAT AP 1 1 0 1 1 P 0 0 1 ·1 A FMT reg. - (AP):>.1\1a. FORMATN 0 0 0 1 0 0 0 b ,1 1 N FMTreg. -NrnCi DSPF digit, AP 0 0 1 1 0 P digit A Digit (Low part) - (AP)via tableDSPFH digit, AP 0 0 1 1 1 P digit A Digit (High part) - (AP)via tableHALT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 HaltINTENAB 0 0 0 1 0 0 1 0 1 1 1 0 0 032/16 0 0 0 1 0 0 0 1 0 0 0 0 1 0Enable ti~erINTDSAB 0 0 0 1 0 0 1 0 1 ' 1 0 1 0 0Disable timer32/160 0 0 1 0 0 0 1 0 0 0 0 0 1rn(jj.c ,INTMODEAP 1 1 0 1 0 P 0 1 0 0 A AP -Interrupt mode(5PAGEAO 1 1 0 1 1 -0, 0 1 0 1 A Preg -(AO)oiSe .PAGE N -. 0 0 0 1 0 0 0 1 0 1 N Preg +-NC0 ADRSAP 1 1 0 1 \ 1 P 0 1 1 0 A Areg -(AP),Q:::>a. ADRSN 0 9 0 '1 0 0 0 1 1 0 N Areg -NQRATEAP 1 1 0 1 0 P 1 0 0 1 A AP - DIVIDER (8 Hz-1 Hz)110RSTRATE 0 0 0 1 0 0 1 0 0 0 1 0 0 0 DIVIDER (8 Hz---1 Hz)-OBACKUP 0 0 0 1 0 0 0 0 0 1 b3 b2 0 0 Backup ON/OfFON/OFFNOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation;

OKI semiconductorMSM5056CMOS 4BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITHLCD DRIVERGENERAL DESCRIPTIONThe OKI MSM5056 is a low-power, high-performance single-chip microcontroller employingcomplementary metal oxide semiconductor technology. Integrated onto a single chip are a 4-bit ALU,25K bits of mask programmable ROM, 360 bits of data RAM, crystal oscillator, voltage doubler, timer,LCD driver, input port, output port and overcharge protection circuit for connection to a solar cell.The MSM5056 is widely used in electronic products requiring low power operation, for example,solar calculator watches and games.FEATURES• Low Power Consumption 3 !LA Typical • 42 Instructions• 1792 x 14 Internal ROM • /1 .5 V Operating Voltage• 90 x 4 Internal RAM(The solar.cell can be connected.)• 4 Input Port• 32.768 kHz Crystal Oscillator• 4 Output Port • 122.1!Ls Instruction Cycle• 4 x 4 Key Matrix Input (K 1-K4, M 1-M4) • -20 to 75°C Operating Temperature• 38 LCD Driver• 68 pad die(112 Duty, 112 Bias, 88 Segment)FUNCTIONAL BLOCK DIAGRAMSDDATA RAMA3-AOLDSEGMENTOUTtLATCH SEGMENT~ ~~~~2~DISPLAY Iand OUT 38I S=======r~~~~~g~~~~~~~~~~~==~DRIVER ---+COMlCOM,INSTRUC­TIONOECOOEAVOD VSS2 Vsc VCMvss, VEE vcp VINI I I I 1 I111

• MSM5056·----~----------------,------LOGIC SYMBOLCHIP PAD LAYOUTSEGMENT OUTPUTOSCILLATION [RESETM,M,M,M,ACVOOVSS 1,~~~2VSCVCPVCMV INBOLDADJUSTMENT for~~i~:g:LL CRAMP'--___ -'~~ J TESTT4TsLAMP OUTPUTCHIP SIZE 5.42 x 4.13 (mm)PIN DESCRIPTIONDesignationVOOCircuit ground potentialVSS, Power sQurce (-1.5 V)VSCFunctionSolar cell connection terminalVSS 2 Power source for LCD driver (-3.0 V)This terminal is cOnl1ectedtoVoO terminal through a 0.1 fJ.F capacitor.VEE Power source for internal logic (-1.5 to -3.0 V)This terminal is connected to VOO terminal through a 0.1 fJ.F capacitor.VCP,VCMXT,XTBooster capacitor connection terminalsVCP terminal is connected to VcM terminal through a 0.1 fJ.F capacitor.Input and output terminals of ,oscillator inverter,32.768 kHz crystal is connected to these terminals.T,-Ts Terminals to test internal logic, T, - T3 and Tsare pulled down to VSS,.T 4 is output. Test pins must be normaly open.ACBOLO,VINTerminal to clear internal logic pulled down to VSS,.After power i~ turned on, the MSM5056 must be reset by this terminal.,Buzzer outputLamp outputAdjustment for solar cell cramp voltage, This termi!1al is connected to VSS, termilJal through 50 - 200 kG resistor.112

---------------------------e. MSM5056 •FUNCTIONAL DESCRIPTIONA block diagram of the MSM5056 is given onpage 111. Each block of logic will be brieflydiscussed. For more information, please refer tothe MSM5056 user's manual.Program RPMThe MSM5056 will address up to 1.75 Kwords of internal mask programmable ROM.Each word consists of 14 bits and allinstructions are one word. The instructions arerouted to a programmed logic array whichgenerates the signals necessary for control oflogic.Data RAMData is organized in 4 bit nibbles. Internaldata RAM consists of 90 nibbles.The RAM is addressed by page address andcolumn address. Normally page address isspecified with the page register, but directaddressing is available at Page O.Column address is directly addressed by theoperands of various instructions.ALUThe ALU performs 4-bit parallel operation ofRAM and AC contents, or RAM contents and animmediate digit. It sets or resets the flags (Z, C)depending on the condition.Program Counter (PC)The program counter is an 11-bit widecounter and specifies the address of theprogram ROM.The PC is incremented by one at everyexecution of an instruction,· and then specifiesthe next instruction to be executed. However, thecontents of thePC are rewritten by the executionota Jump or Branch instruction.There is no boundary in the ROM, so a Jumpor Branch instruction can be put anywhere in theROM.Input/Output PortInput Port (K1 - K2)The input port (K1 - K4) is a 4-bit parallelinput port. Each pin of the port is pulled down toVSS1 by an internal reSistor, and the status ofthe port can be fetched by an input instruction.Output Port (M1 - M4). The output port (M1 - M4) is a 4-bit paralleloutput port. This port consists of data latchesand buffers. The contents of data latches arerewritten by an output instruction. A key matrixis used in combination with K1 to K4.•~+MlM2 M3 M4Display FunctionThe MSM5056 is provided with a segmentoutput terminal which can directly drive a 1/2bias, 1/2 duty LCD and common drive outputterminals. COM1 and COM2. The segment drivecircuit consists of the display data latch,multiplexer and driver. If the data is sent to thedisplay data latch with the display instruction,the LCD drive waveform is output to the segmentdrive output terminal.Time BaseTime base of the CPU is provided byconnecting a 32.768 kHz crystal to the OSC1and OSC3 pin. One machine cycle is 1 22.1 /Ls.A hardware divider up .to 1 Hz is providedenabling programs to implement and a clockfunction by counting Signals between 16 and 1Hz. .Solar Cell Overcharge Protection CircuitWhen a solar cell is connected to prolong theusefull life of the battery, a resistor is insertedbetween the VIN pin and VSS1 to adjust theovercharge protection voltage....-----1 VSS,~"'\A\i","""--I V I NMSM5056KlK2K3K4113

• MSM5056··--~--------------------~----~------------------ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Limits UnitSupply Voltage 1 VOO-VSS, Ta = 25°C , -0.3 to +3.0 VSupply Voltage 2 VOO -VSC Ta =25°C -0.3 to +3.5 VSupply Voltage 3 VOO - VSS2 Ta = 25°C -0.3 to +6.0 VSupply Voltage 4 VOO -VEE Ta = 25°C -0.3 to +6.0 VInput Voltage VIN, Ta = 25°C VSS, -0.3 to +0.3 VStorage Temperature Tstg -55 to 125 °COPERATING CONDITIONSParameter Symbol Limits UnitOperating Voltage VOO-VSS, 1.25 to 1.65 VOperating Temperature Topr -20 to 75 °CDC CHARACTERISTICS(Voo =OV, VSS" VEE = -1.55V, VSS2 = -3.0V, CI = 30kfl, CG = 30pF, Ta = 25°C)LimitsParameter Symbol ·Condition UnitMin. Typ. Max.Operating voltage 1 -VSS, VSS, terminal 1.25 1.55 2.0 VOperating voltage 2 -VSC VSC terminal 0 2.0 3.0 VPower supply current 'DO VSS, terminal - 3.0 - p.AOscillation startvoltageOutput current 1COM-VOSCWithin 10 secondsVSS, terminal1.45 - - VIOH, VOH, =-0.2V -4 - -10M, VOM, = VSS, ± 0.2V 4/-4- -IOL, VOL, =-2.8V 4 - -Output current 2 IOH2 VOH2 =-0.2V -0.4 - -SEGMENTIOL2 VOL2=-2.8V 0.4 - -Output current 3 IOH3 VSS" VEE -1.25V I VOH3 -0.4 V -100 - -M,-M.IOL3 VSS2-2.3V I VOL3-0 .85V 3 - 8Output current 4 IOH. VOH. =-O.4V -50 -100 -200BOIOL. VOL. = -1.15V 3 10 30Input current IIH, VIN =-OV 5 10 15K,-K.IlL, VIN = -1.55V - - -0.2Oscillator built-incapacitorCDp.Ap.Ap.A/LAp.A- 20 - pFSolar battery crampVSS, = -1.8Vresistor RIN VIN terminal 50 - 200 kfl114

-------------------------------------------e. MSM5056.MEASURING CIRCUIT30pF0.1j.1F32.768kHzTYPICAL APPLICATIONLCDKlK2K3K4M4M3M2MlMSM5056BDVSCVINAC'--_-....... ---~-------1 RTR2CG : 5-35pFC1.C2.C3 : 0.1j.1FTR1. TR2 : hfe'" 200TR2 : VCEo..> 35VLl : 20-~OmHB : 1.5V': 50 - 200kO115

• M$M5056·~.----~----------------------------~------~---DESCRIPTION OF INSTRUCTIONSMnemonicInstruction Code131211109 8 7 6 5 4 3 2 1 0OperationADD ACC,AP 0 0 0 0 0 P 0 1 0 0 A AP ~ (AP) + (ACC)ADD #o,AP 0 1 1 0 o P 0 A AP--(AP) - 0AoCAP 0 0 0 0 0 P 0 1 0 1 A Af' -- Decimal adjust{(AP) + (ACC) + (C)}c SUBACC,AP 0 0 /) 0 1 P 0 1 0 0 A AP -- (AP) - (ACC)0:; ... SUB #0, AP o '1 1 0 1 P 0 A AP --(AP) - 08.0 SBCAP 0 0 0 0 1 P 0 1 0 1 A AP-- Decimal adjust(.):;{(AP) - (ACC) - (C)}E CMPACC,AP 0 0 0 0 1 P 1 1 1 0 A (AP) - (ACC).c=E« CMP #o,AP 0 1 0 1 1 P 0 A (AP) - 0INCAP 0 1 1 0 0 P 0 0 0 1 A AP"':"(AP) + 1oECAP 0 1 1 0 1 .P 0 0 0 i A A--(AP) - 1XORACC,AP 0 0 0 0 .0 P 0 1 1 1 A AP -- (AP) "'It" (ACC)XOR #o,AP 0 1 1 1 1 P 0 A AP --(AP)VDBITACC,AP 0 .0 0 0 0 P 1 1 1 0 A (AP) V (ACC)c BIT#o,AP 0 1 0 1 0 P 0 A (AP)Vo.2iii BISACC,AP 0 0 0 0 .0 P 0 1 1 0 A AP -- (AP) V (ACC)...Q)c. BIS#o,AP 0 1. 0 0 0 P 0 A AP --(AP) VD0-iii BICACC,AP 0 0 0 0 1 P 0 1 1 0 A AP -- (AP) I\(ACC)BIC #0, AP 0 1 0 0 1 P 0 A AP -- (AP) 1\ 0ASRAP 0 0 0 0 0 P .0 0 1 1 A L-(C) 0 - (AP):::I~en ASlAP 0 0 0 0 1 P 0 .0 1 1 A (C) -- (AP) -- 0elZ 0 0 0 0 .0 0 1 0 1 0 0 0 0 0 Z--Oc0 ClC .0 0 0 0 0 0 1 0 0 1 0 0 0 0 C--O:;ClA 0 .0. 0 0 0 0 1 0 1 1 0 0 0 0 Z --0, C--O...8.0CIIIIu:...Q)SEZ 0 0 0 0 1 0 1 0 1 0 0 0 0 0 Z"-1SEC 0 0 0 0 1 0 1 0 0 1 0 0 0 0 C-1SEA!0 0 0 0 1 0 1 0 1 1 0 0 0 O. Z-1,C"-1MOVACC,AP 1 1 1 1 0 P 0 0 0 0 A AP-(ACC)MOVACC,AX 1 1 1 1 0 0 0 X A AX --(ACC)MOV#D,AP 0 1 1 1 0 P 0 A. AP --0'0cIII MOVAP,ACC 1 1 1 1 1 P 0 0 0 0 A ACC --(AP)=~MOV AX, ACC 1 1 1 1 1 0 0 X A ACC-(AX)0CHGAP 1 1 1 0 0 P 0 0 0 0 A (ACC)-(AP)CHGAX 1 1 1 0 .0 0 0 X A (ACC)-(AX)116.

--------------------------~----------------------__e. MSM5056 •DESCRIPTION OF INSTRUCTIONS (CONT.)MnemonicInstruction Code131211109 8 7 6 5 4 3 2 1 0OperationJMP adrs 1 0 0 a lO a9 a8 a7 ae as a. a3 a2 a, ao PC -adrsJMP @AP 0 0 0 0 0 P 1 1 0 1 A PC - (PC) + (AP) + 1JMPIO @AP 0 0 0 0 1 P 1 1 0 1 A PC - (PC) + ((AP)A7H) + +1BEQ +nBZE +nBNEa.+nE BNZ +n:;,...,BCS +nBLT +nBCC +nBGE +n0 0 0 1 1 0 0 1 0 n. n3 n2 n, no PC - (PC)+n+1, if Z=10 0 0 1 1 0 1 1 0 n. n3 n 2 n, no PC - (PC) +n + 1, if Z =00 0 0 1 1 0 0 0 1 n. n3 n2 n, no PC - (PC)+n+1, if C=10 0 0 1 1 0 1 0 1 n. n3 n2 n, no PC - (PC) + n + 1, if C = 0BGT +n 0 .0 0 1 1 0 1 1 1 n. n3 n2 n, noPC -(PC)+n+1,ifZ=0and C=OBLE +n 0 0 0 1 1 0 0 1 1 n. n3 n2 n, noPC - (PC) +n+ 1, if Z= 1orC=1INP Port, AP 1 1 0 1 0 P Port A AP - (Port)..... -:;, -:;,0. OUT AP, Port 1 1 0 1 1 P Port A Port - (AP)0.-1:::;'-0 OUT #0, Port 0 0 0 1 0 0 Port D Port -0> OSP digit, AP 0 0 1 0 0 P digit A digit - (AP). (ACC)C1Ia.IIIOSPF digit, AP 0 0 1 1 0 P digit A digit - (AP) via tablei5e HALT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Halt CPU::::>-0..1::08NOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No Operation117

OKI semiconductorMSM6051CMOS 4BIT. HIGH PERFORMANCE SINGLE CHIP VERY LOW POWERMICROCONTROLLER WITH LCD DRIVERGENERAL DESCRIPTIONOKl's MSM6051 is a low-power and high-performance single-chip microcontroller employingcomplementary metal oxide semiconductor technology. Integrated onto a single chip are a 4-bit ALU,35K bits of mask programmable ROM, 480 bits of data RAM, crystal oscillator, voltage doubler, timer,LCD driver, input port and output port.The MSM6051 is widely used in electronic products requiring low power operation, for example,stopwatches with lap time memory, calculator watches and handy terminals.FEATURES• Low Power Consumption 3 !LA Typical• 2560 X14 Internal ROM• 120 x 4 Internal RAM• 9 Input Port• 4 Output Port• 4 x 4 Key Matrix Input (K1-K4, M1-M4)• 66 LCD Driver (including 3 common)(1/3 Duty, 1/3 Bias, 189 Segment)• 59 Instructions• 1.5 V or 3 V Operating Voltage(Masking Option)• 32.768 kHz crystal Oscillator• 91.5 /Ls Instruction Cycle• -20 to 75°C Operating Temperature• 101 pad dieFUNCTIONAL BLOCK DIAGRAMSDDATA RAM120 word x 4bitLDM1IM4LOSEGMENTounSSEGMENTOPTIONPROGRAMAOM256 word x 14 bitINSTRUC­TIONDECODER! ! j j j j !VSS 1 VSS3 vepVDD VSS2 VEE VCM! ! 1 j ! ! jAC T1 T2 T3' T4 T5 32Hz118

--------------------------. MSM6051 •LOGIC SYMBOLCHIP PAD LAYOUTOSCILLATION (INPUT PORT [(Sl-S4)INPUT PORT [(Kl-K4)OPTION INPUTOUTPUT PORT [(Ml-M4)LOADXTXTSEGMENTOUTlSEGMENTOUTeeBDLD\ l,roM~'BUZZER OUTPUTLAMP OUTPUTCLOCK PULSEOUTPUTRESETSEG60VDDXlXTXTOUTAC2S2S3VEEVCHKlK2K3K4MlM2M3M4LOSEG1~~~~~~~~SEG34OPINVDDVSS2VSS3VCPVCMSlS4VSS1DOLDACT3T1T4T2T532HzSEG33SEGMENT OUTPUTCHIP SIZE 5.85 x 4.10(mm)PIN DESCRIPTIONDesignationVDDCircuit ground potentialVSS 1 Power source (-1.5 V)FunctionVSS 2 Power source for LCD driver (-3.0 V)This terminal is connected to VDD terminal through a 0.1 JLF capacitor.VSS3 Power source for LCD driver (-4.5 V)This terminal is connected to VDD terminal through a 0.1 JLF capacitor.VEE Power source for internal logic (-1.5 to -3.0 V)This terminal is connected to VDD terminal through a 0.1 JLF capacitor.VCP, VCMXT,XTBooster capacitor connection terminalsVCP terminal is connected to VCM terminal through a 0.1 JLF capacitor.Input and output terminals of oscillator inverter,32.768 kHz crystal is connected to these terminals.Tl-T5 Terminals to test internal logic, T 1 - T3 and T 5 are pulled down to VSS 1•T4 is output. Test pins must be normally open.AC Terminal to clear internal logic pulled down to VSS 1•After power is turned on, the MSM6051 must be reset by this terminal.BDLDBuzzer outputLamp outputLO Load data terminal of M 1 to M 4.AC2XTOUTReset terminal for external circuit.Clock output for external circuit.119

• MSM6051 .------------~--------------------------------------FUNCTIONAL DESCRIPTIONA block diagram oUhe MSM6051 Js given onpage 118. Each block of logic will be brieflydiscussed. For more information, please refer tothe MSM6051 user's manual.Program ROMThe MSM6051 addresses up to 2.5 K wordsof internal mask programmable ROM. Each wordconsists of 1 4 bits, and a:II instructions are oneword. The instructio.ns are routed to aprogrammed logic array which generates thesignals necessary for control. of logic.Data RAMData is organized in 4 bit nibbles. Internaldata RAM consists of 1 20 nibbles.The RAM is addressed by page address andcolumn address. Normally page address isspecified the with page register, but directaddressing is available at Page O.Column address is directly addressed byoperand of various instructions.ALUThe ALU performs 4-bit parallel operation ofRAM and ACC contents, or RAM contents andan immediate digit. It sets or resets the flags (Z,C, G) depehding on the condition.Program Counter (PC)The program counter is 12 bits wide andspecifies the address of the program ROM.The PC is incremented by one at everyexecution of the instruction, and then specifiesthe next instruction to be executed. However, the·contents of the PC are rewritten by the executionof a Jump, Call or Branch instruction.There is no boundary in the ROM, so a Jumpor Branch instruction can be put anywhere in theROM.5tackThe MSM6051 has a 3 level stack apart fromdata RAM. The contents of the PC are loadedinto the stack when a call instruction is executedor an interrupt is generated.Input/Output PortInput Port (51 - 54)The input port (S1 - S4) is a 4-bit parallelinput port. Each pinof the port is pulled down toV SS 1 by an internal resistor, and the status ofthe port is fetched by a SWITCH instruction.Input Port (K1 - K4)The input port (K1 - K4) is a 4-bit parallelinput port. Each pin of the port is pulled down toVSS 1 by an internal resistor, and the status ofthe port is fetched by a KSWITCH instruction.Input Port (OPIN)The input port (OPIN) is single input port.OPIN is pulled down to VSS , by an internalpower save circuit, and the status of the port isfetched by an input instruction.Output Port (M1 - M4)The output port (M1 - M4)is a 4-bit paralleloutput port. This port consists of data latchesand buffers, and the contents of data latches arerewritten by a matrix instruction.Display FunctionThe MSM6051 is provided with the segmentoutput terminal which can directly drive a 1/3bias, 1/3 duty LCD, and the common.driveoutput terminals COM1, COM2 and COM3.The segment drive .circuit consists of thedisplay data latch, multiplexer and driver. If thedata is sent to the display data latch with thedisplay instruction, the LCD drive waveform isoutput to the segment drive output terminal.Time BaseThe time base of the CPU is provided byconnecting 32.768 kHz crystal to the XT and XTpin. One machine cycle is 91.5 fls.A hardware divider up to 1 Hz is providedenabling programs to implement a clock functionby counting signals between 32 and 1 Hz.Also, a 1/100 second digit counting functionis provided as a hardware feature to make foreasy implementation of a stopwatch function.120

--------------------------. MSM6051 •ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Limits UnitSupply Voltage 1 VDD -VSS, Ta = 25°C -2.0 to +0.3 VSupply Voltage 2 VDD -VSS2 Ta =25°C -4.0 to +0.3 VSupply Voltage 3 VDD - VSS3 Ta = 25°C -6.0 to +0.3 VSupply Voltage 4 VDD -VEE Ta = 25°C -4.0 to +0.3 VInput Voltage VIN, Ta = 25°C VSS, -0.3 to +0.3 VStorage Temperature Tstg -55 to 125 °cOPERATING CONDITIONSParameter Symbol Limits UnitOperating Voltage VDD-VSS, 1.25 to 1.65 VOperating Temperature Topr -20 to 75 °cDC CHARACTERISTICS(VDD =OV, VSS" VEE = -1.55V, VSS 2 = -3.0V, VSS3 = -4.5V, CI = 30kn, Ta = 25°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Power supply current IDD VSS terminal - 3.0 - /-LAOscillation start Within 5 seconds 1.45 - - Vvoltage-VOSC VSS, terminalIOH, VOH, =-0.2V -4 - -Output current 1 IOMH, VOMH, =VSS, ± 0.2 4/-4 - -COMIOML, VOML, = VSS2 ± 0.2 4/-4 - -IOL, VOL, =-4.3V 4 - -IOH2 VOH2 =-0.2V -4 - -Output current 2 IOMH2 VOMH2 = VSS,±0.2 4/-4 - -SEGMENTIOML2 VOML2 = VSS2±0.2 4/-4 - -IOL2 VOL2 =-4.3V 4 - -Output current 3 IOH3 VOH3 =-0.5 V -10 - -AC2 LOAD XTOUTIOL3 VOL3 = -1.15V 10 - -Output current 4 IOH4 VOH4=-0.5V -100 - -M,-M4IOL4 VOL4 =-1.0V 2 - 10Output current 5 IOH5 VOH5 = -0.55V VSS, =-1.25V -12.5 -25 -83LD VEE =-2.0V /-LAIOL5 VOL5 = -0.85V VSS 2=-2.0V 1 - -Output current 6 IOHe VOHe = -0.55V Vss,=-1.25V -17 -30 -62SD VEE =-2.0V /-LAIOLe VOLe = -0.85V VSS 2=-2.0V - 5 -/-LA/-LA/-LA/-LA121

• MSM6051 •• --------~----------------------~---------------Parameter Symbol ConditionsMin.LimitsTyp. Max.UnitInput current 1 IIH, VIH, =OVS,-S.IlL, VIL,=-1.55VInput current 2 IIH2 VIH2 =OVK,-K.IIL2 VIL2 = -1.55VI nput current 3 IIHa VIHa =OV .OPINliLa VILa = -1.55VOscillator built-incapacitanceCD2-5----20 100p.,A- -0.213 26p.,A- -0.230 45p.,A- -0.220 - pFMEASURING CIRCUITVEEVCPVCMXTXTC4C5=C1.C2.C3C5X-tal.C4 0.1 JLF30 pF32.768 kHzTYPICAL APPLICATIONLCDC1C2toC5BL5-35 pF0.1 JLF1.5 V20mHLampS1 --'-S2 ___S3....L...S4 .....:...X-tal=S1S2S3S4XT(CD=20 pF)MSM6051LDBDVSS,VDDBC1122

------------~------------------~------------------. MSM6051 •DESCRIPTION OF INSTRUCTIONSMnemonicInstruction Code131211109 8 7 6 5 4 3 2 1 0OperationAOOACC,AP 0 0 0 0 0 P 0 1 0 0 A AP - (AP) + (ACC)AOO#O,AP 0 1 1 0 0 P 0 A AP-(AP) +0AOCAP 0 0 0 0 0 P 0 1 0 1 A AP - Decimal adjust{(AP) + (ACC) + (C)lAOCNAP 1 1 0 0 0 P N A AP - N adjust {(AP) + (C)lSUB ACC,AP 0 0 0 0 1 P 0 1 0 0 A AP - (AP) - (ACC)c::SUB#D,AP 0 1 1 0 1 P D A AP-(AP) -D0~SBCAP 0 0 0 0 1 P 0 t 0 1 A AP - Decimal adjustQi{(AP) - (ACC) - (C)la.0 SBCNAP 1 1 0 0 1 P N A AP - N adjust ((AP) - (C) I0~ CMP ACC, AP 0 0 0 0 1 P 1 1 1 0 A (AP) - (ACC)E:5 CMP#D,AP 0 1 0 1 1 P 0 A (AP) -0~INCAP 1 1 1 0 0 P 0 0 0 0 A AP - (AP) + 1INCAX 1 1 1 0 0 0 0 X A AX-(AX) + 1DECAP 1 1 1 0 1 P 0 0 0 0 A AP -(AP)-1DEC AX 1 1 1 0 1 0 0 X A AX -(AX)-1XORACC,AP 0 0 0 0 0 P 0 1 1 1 A AP - (AP) -V- (ACC)XOR #D,AP 0 1 1 1 1 P D A AP - (AP) "'f DBITACC,AP 0 0 0 0 0 P 1 1 1 0 A (AP) V (ACC)c:0 BIT #D,AP 0 1 0 1 0 P D A (AP) V D~ BISACC,AP 0 0 0 0 0 P 0 1 1 0 A (AP) V (ACC)Qia.0 BIS #0, AP 0 1 0 0 0 P D A (AP)VD-iii BIC ACC, AP 0 0 0 0 1 P 0 1 1 0 A (AP) /\ (ACC):.c.....Q)BIC#D,AP 0 1 0 0 1 P D A (AP) /\ D~RORAP 0 0 0 0 0 P 0 0 1 0 A L. (C) - (AP)---i(J) ROlAP 0 0 0 0 1 P 0 0 1 0 A L(C)-(AP)~a; ASRAP 0 0 0 0 0 P 0 0 1 1 A L. (C) 0 - (AP)--l"0II: ASLAP 0 0 0 0 1 P 0 0 1 1 A (C) -(AP)-OClZ 0 0 0 0 0 0 1 0 1 0 0 o 0 0 Z-Oc:0 ClC 0 0 0 0 0 0 1 0 0 1 0 0 0 0 C-O:; .... ClG 0 0 0 0 0 0 1 0 0 0 0 0 0 0 G-OQ)a.001IIIu::ClA 0 0 0 0 0 0 1 0 1 1 0 0 0 0 Z -0, C -0, G-OSEZ 0 0 0 0 1 0 1 0 1 o 0 0 0 0 Z-1SEC 0 0 0 0 1 0 1 0 0 1 0 0 0 0 C-1123

eMSM6051 e~------------------------------------------~-----­DESCRIPTION OF INSTRUCTIONS (CONT.)MnemonicInstruction Code131211109 8 7 6 5 4 3 2 1 0OperationoSEG 0 0 0 0 1 0 1 0 0 0 0 0 0 0 G-1SEA 0 0 0 0 1 0 1 0 1 1 0 0 0 0 Z-1,C-1,G-1....MOVACC,AP 1 1 1 1 0 P 0 0 0 0 A AP-(ACC)~(J) MOVACC,AX 1 1 1 1 0 0 0 X A AX-(ACC)

-------------------------------------------------.. MSM6051 •DESCRIPTION OF INSTRUCTIONS (CONT.)MnemonicInstruction Code131211109 8 7 6 5 4 3 2 1 0Operation'SMATRIXAP 1 1 0 1 1 P 0 0 1 0 A OUTPUT PORT (M1-M4)--(AP)MATRIXMn0 0 0 1 0 0 0 0 1 0 M4 M3M2M, OUTPUT PORT (M1-M4)--Mn (n=1, 2, 3, 4).e- XTCPON/OFF 0 0 0 1 0 0 1 0 0 0 0 o b, bo XTOUT ON/OFF::J0:;:. PITCHN 0 0 0 1 0 0 1 1 0 0 N PIT reg.--N::Ja..E MSAadrs 1 0 1 0 1 aa a7 as a 5 a4 a3 a2 a, ao Stack -- (PC), PC ..... adrs,MSOLAMP ON/OFFMelody start0 0 0 1 0 0 1 0 1 0 0 000 Melody stop0 0 0 1 0 0 0 0 0 1 0 o b, bo LD ON/OFFDSP digit, AP 0 0 1 0 0 P digit A Digit (Low part) -- (AP), (ACC)DSPH digit, AP 0 0 1 0 1 P digit A Digit (High part) -- (AP), (ACC)>- FORMATAP 1 1 0 1 1 P 0 0 1 1 A FMT reg. -- (AP)tISc.IIIFORMATN 0 0 0 1 0 0 0 0 1 1 N FMTreg.--NisDSPF digit, AP 0 0 1 1 0 P digit A Digit (Low part) -- (AP) via table...Q)DSPFH digit, AP 0 0 1 1 1 P digit A Digit (High part) --(AP) via tab IHALT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 HaltINTENAB 0 0 0 1 0 0 1 0 1 1 1 0 0 032/16/20 0 0 1 0 0 0 1 0 0 b3 0 b, 0INTDSAB 0 0 0 1 0 0 1 0 1 1 0 1 0 032/16/2 0 0 0 1 0 0 0 1 0 0 0 b2 0 boEnable timer interruptDisable timer interruptACTIVATE 0 0 0 1 0 0 1 0 0 1 0 0 0 0 Activate main routineINTMODEAP 1 1 0 1 0 P 0 1 0 0 A AP -- Interrupt modeIII KENAB 0 0 0 1 0 0 0 1 1 1 1 o 0 0 Enable INPUT PORT (K1-K4).r. KDSAB 0 0 0 1 0 0 0 1 1 1 0 1 0 0 Disable INPUT PORT (K1-K4)0OIl STATUSAP 1 1 0 1 0 P 1 0 1 0 A AP --Statuse PAGEAO 1 1 0 1 1 0 0 1 0 1 A Preg --(AO)"E0Co) PAGEN 0 0 0 1 0 0 0 1 0 1 N Preg --N::lQ.Co)ADRSAP 1 1 0 1 1 P 0 1 1 0 A Areg--(AP)ADRSN 0 0 0 1 0 0 0 1 1 0 N Areg --NRATEAP 1 1 0 1 0 P 1 0 0 1 A AP -- DIVIDER (8 Hz-1 Hz)RSTRATE 0 0 0 1 0 0 1 0 0 0 1 o 0 0 DIVIDER (8 Hz-1 Hz)--OFLAGINAP 1 1 0 1 0 P 1 1 1 0 A AP -- S1 on flag, S2 on flagS1 RATE AP 1 1 0 1 0 P 1 1 0 0 A AP --S1reg.S2RATEAP 1 1 0 1 0 P 1 1 0 1 A AP --S2reg.BACKUP 0 0 0 1 0 0ON/OFF0 0 0 1 b3 b2 0 0 Backup ON/OFFNOP 0 0 0 0 0 0 0 0 0 0 000 0 No operation125

OKI semiconductorMSM6351CMOS 4BIT HIGH PERFORMANCE AND VERY LOW POWER SINGLE CHIPMICROCONTROLLER WITH LCD DRIVERGENERAL DESCRIPTIONOKl's MSM6351 is a low-power, high-performance single-chip microcontroller employing silicongate CMOS technology. Integrated onto a single chip are 4-bit ALU, 61 K bits of mask programmableROM,·4096 bits of RAM, 20 bits of 110 port, serial 110 port, time-base counter, LCD driver, 3interrupts, crystal oscillator and voltage trjpler.The MSM6351 is widely used in electronic products requiring low power consumption, a largenumber of LCD drivers and a large size of memory.FEATURES\• Low Power Consumption 3 p..A Typical• 4096 x 15 Internal ROM• 1024 x 4 Internal RAM• 20 Input/Port Ports• 62 LCD Drivers1/3 Duty, 1/3 Bias or 1/4 Duty 1/3 Bias(Selectable by software)• Serial I/O Port8 bits or 5 bits data frame modeAsynchronous or synchronousreceiver/transmitter modeInternal or external clock mode• 15 stages Time Base Counter• Watch Dog Timer• Capture function by external trigger signal• 3 Interrupt SourcesReal time interruptExternal interruptSerial 110 port interrupt• Melody Circuit• 65 Instructions• Sub-routine Nesting: 7 levels• 32.768 kHz Crystal Oscilator• Machine Cycle: 61.0 p..sec.• Power Supply: 1.5V or 3.0V (selectable bymask option)• 100 pad die orl 00 Pin Flat Package• Silicon gate CMOS Process126

------------------------. MSM6351 •FUNCTIONAL BLOCK DIAGRAMLOGIC SYMBOLPORTO CPORn CPORT2CPORT3 CPORT4 CPO.OSINPO.lSOUTPO.2PO.3SCKPl.0Pl.1BoP1.2P1.3 seGOSEGlP2.0SEG2££.1. SEG3Pg·2SEG4P2.3==: J SERIAL PORTBUZZERDRIVERP3.0 LCDP3.1 DRIVERP3.2P3.3P4.QgEG58P4·1P4.2SEG59P4.3SeGruLSEG6lXTOUTVoo XT VooX'fVSS1RESETTESTeRESETTEST1TEST2TEST3VSS2VSS3VEEVCMVCPl POWERJSUPPLY127

• MSM6351 • ------,.-------------------PIN DESCRIPTIONDesignationPO.O -PO.3Function4 bits input/output port.PO.O and PO.1 have a secondary function of capture trigger signal input pins.P1.0 - P1.3 4 bits input/output port.P2.0 -P2.3 4 bits input/output port.P2.0, P2.1 and P2.2 have a secondary function of external interrupt signalinput pins.P3.0 -P3.3 4 bits input/output port.P4.0 -P4.3 4 bits input/output port.SINSOUTSCKSEGO-SEG61Serial input port.Serial output port.Serial port clock input/output pin.LCD drive output pins.These outputs can derive 1/3 dutY-1 /3 bias LCD which has 177 segments or1/4 dutY-1 /3 bias LCD which has 232 segments.DesignationBDXTOUTXT,XTBuzzer drive output pin.Clock output pin.FunctionInput and output pins of oscillator inverter.RESET System reset input pin pulled down to VSS1 .TEST1 -3 Internal logic test pin pulled to VSS1.-VDDVSS1VSS2VSS3VEEVCP, VCMCircuit ground potentialPower source (-1 .5V)Power source for LCD driver (-3.0V)This pin is connected to VDD pin through a capacitor.Power source for LCD driver (-4.5V)This pin is connected to VDD pin through a apacitor.Power source for internal logic.This pin is connected to VDD pin through a capacitor.Booster capacitor connection pins.VCP pin is connected to VCM pin through a capacitor.128

OKI semiconductorMSM6052CMOS 4BIT SINGLE CHIP LOW POWER MICROCONTROLLER FORTELEPHONEGENERAL DESCRIPTIONThe OKI MSM6052 is low-power, high-performance single-chip 4-bit microcontroller employingcomplementary metal oxide semiconductor technology, especially designed for use in sophisticatedtelephone sets. Integrated onto a single chip are 4 bits of ALU, 28K bits of mask programmable ROM,2560 bits of data RAM, programmable timer, oscillator, 12-bits of input port, 12-bits of output port and4-bits of input/output port. In addition to these units, a DTMF generator is provided.With the MSM6052, sophisticated telephone sets become feasible through a single chip insteadof the conventional 3-chip configuration.FEATURES• Low Power Consumption 0.3mA Typical @3V(DTMF output off)• 2048 x 14 Internal ROM• 640 x 4 Internal RAM• 3 x 4 Input Port• 3 x 4 Output Port• 1 x 4 Input/Output Port• DTMF Generator• Buzzer Sound Output• 4-Bit Programmable Timer Applicable forOutput of Dial Pulse• Interrupt by Progammable Timer• 5 Level Stack• Power Down Mode• 52 Instructions• Instructions Useful for Data Management(Data Search and Block Data Transfer)• 2.5 to 6.0V Operating Voltage• 3.58 MHz Oscillator• 1 7.9 Ils Instruction Cycle• -20 to 75°C Operating Temperature• 28 Pin DIP or 40 Pin DIPFUNCTIONAL BLOCK DIAGRAMR.R2~~RS~Heg'3••C.C2-g~8~03D.EO.E02E03EO.10.10218~10EHS --l'------''---'XTXi'32kHzTIMING'GENERATOR[iPOUTPROGRAMMABLETIMERDTMFOUTDTMFCIRCUITINSTRUCTIONDECODER! !AC TEST1 1"DO VssBDt.::::::::~===========~JIl _________________ ~DATA RAM640 word x 4 bitPROGRAM ROM2048 word x 14 bit129

• MSM6052 •• ----------------------------~--------~--------~PIN CONFI.GURATION(Top View) 40 Lead Plastic DIP(Top View) 28 Lead Plastic DIPE03E04C1C2C302RSR703VDDLOGIC SYMBOLKEYBOARD [INPUTR1R2R3R4E01E02E03E03] OUTPUT PORTKEYBOARD [. INPUTINPUT PORT [KEYBOARD [OUTPUTOUTPUT [PORTHOOK SWITCHRSRSR7] 10PORTR8OUTPUT ENABLE11DIALPUSLE12 DPOUTOUTPUT1314 DTMFOUT DTMFOUTPUTC1 BD BUZZER OUTPUTC2C3 32kHz 32kHz OUTPUTC4ACRESETTEST) POWEROSCILLATION (130

----------------------------------------~----------. MSM6052 •PIN DESCRIPTIONDesignationVDDVSSACTESTXT,XTHSDPOUTDTMFOUTBDPource sourceCircuit ground potentialFunctionTerminal to clear internal logic, pulled down to VSS.After power is turned on, the MSM6052 must be reset by this terminal.Terminal to test internal logic, pulled down to VSS.This terminal must be open in normal operation.Input and output terminals of oscillator inverter.3.58 MHz ceramic resonator is connected to these terminals.Input terminal connected to the hook switch, pulled up tp VDD.Output terminal of dial pulse.Dial pulse rate (10 pps or 20 pps) and Make Break ratio (40% or 33 %) canbe selected by software.Output terminal of DTMF signalOutput terminal of buzzer sound32 kHz Output terminal of 32 kHz clockR,-R.Rs-RsInput port pulled down to VSS.1,-1. Input port having clocked pull-down resistor to VSS.Only when this port is accessed, pull-down resistors are connected to thisport.C,-C.0,-0.Output port10,-10. Tri-state bidirectional port10EOutput terminalWhen 10, -104 is accessed, input completion signal (when read) orload signal (when written) is output from 10E terminal.131

e MSM6052 e'--------------------------------------------------FUNCTIONAL DESCRIPTIONA block diagram of the MSM6052 is given onpage 129. Each block of logic will be brieflydiscussed. For more information, please refer tothe MSM6052 user's manual.Program ROMThe MSM6052 will address up to 2 K wordsof internal mask programmable ROM. Each wordconsists of 14-bits and all instructions are oneword. The instructions are routed to aprogrammed logic array which generates thesignals necessary for control of logic.Data RAMData is organized in 4-bit nibbles. Internaldata RAM consists of 640 nibbles.All locations are addressed by 10-bitaddress registers (AR " AR2), 2-bit bank register(B), 4-bit page register (P) or a part of theinstruction's operand.ALUThe ALU performs a 4-bit parallel operationon RAM and ACC contents, or on RAM contentsand an immediate digit. It sets or resets the threeflags (Z, C, G) depending on the condition.Program Counter (PC)The program counter is an 11-bit widecounter that specifies the address of programROM.The PC is incremented by one at everyexecution of the instruction, and then specifiesthe next instruction to be executed. However, thecontents of the PC are rewritten by the executionof a Jump, Call or Branch instruction.As there is no boundary in the ROM, and aJump, Call or Branch instruction can be putanywhere in the ROM.StackThe MSM6052 has a 5 level stack apart fromthe data RAM. The contents of the PC are loadedinto stack when a Call instruction is executed oran interrupt is generated. Nesting of subroutineswithin subroutines can continue up to 4 times,including the interrupt.• Input PortPort (R1 - R4)4-bit input port. Each pin of the port is pulleddown to VSS by an internal reSistor, and statusof the port is fetched by an input instruction.Port (R5 - R8)4-bit input port. Each pin of the port is pulleddown to VSS by an internal resistor, and thestatus of the port is fetched by an inputinstruction.Port (I1 -14)4-bit input port. Each pin of the port is pulleddown to VSS by an internal resistor and'transistor. Only when it is desired to fetch statusof the port, input current flows through thesepins. Status of the port is fetched by an inputinstruction.• Output PortPort (C1 - C4)4-bit output port. These ports consist of datalatches and buffers, and the contents of the datalatches are rewritten by an output instruction.Port (01 - 04)4-bit output port. This port consists of datalatches and buffers, and the contents of the datalatches are rewritten by an output instruction.Electrical characteristics of 03 and 04 aredifferent from those of 01 and 02. 03 and 04 ofthe ports are used as XMIT MUTE and MUTEnormally.Port (E01 - E04)4-bit output port. This port consists of datalatches and buffers, and the contents of datalatches are rewritten by an output instruction.• Input/Output PortPort (I01 - 104)4-bit bidirectional port. This port consists ofdata latches, output buffers and input buffers.The contents of the data latches are rewritten byan output instruction, and status of the port isfetched by an input instruction.Address Registers (AR1, AR2)The address registers are used to specify the1 O-bit address of data RAM, when a data searchinstruction (ROAR) or block data transferinstruction (MVAR) is executed.This register is an up/down counter, and isincremented or decremented by 1 withexecution of the instruction.Timing GeneratorBy connecting a 3.58 MHz ceramic resonatorto the XT and XT terminal, the timing generatorgenerates a basic timing signal to control theMSM6052 .The MSM6052 can operate in 2 modes,normal operating mode and power down mode.STOP instruction is used to place the MSM6052in the power down mode. The oscillation stopsand all functions are stopped. However, .thecontents of RAM and all registers are maintained.132

--------------------------------------------------. MSM6052 •Programmable TimerThe programmable timer consists of a 4-bitdown counter and a 1/100 prescaler.Any of a 7990.1 Hz clock, 1997.5 Hz clockand 998.8 Hz clock is input to the 1/100prescaler. Output of the 1/100 pres calerdecrements the 4-bit down counter by 1 .When the contents of the 4-bit down counteris decremented to 0, the programmable timergenerates an interrupt.This programmable timer can be used as adial pulse generator. The dial pulse rate (10 pps,20 pps) and Make/Break ratio (40%, 33%) of thedial pulsll which the programmable timergenerates are selectable.DTMF CircuitOTMF circuit is used to generate a OTMFsignal. 12 kinds of OTMF signal (0 to 9, #, *) canbe output by an output instruction.BDCircuitThe BO circuit generates the square wavewhich can be used as the confirmation sound,warning sound and so on. 15 kinds of sound(4.66 to 0.82 kHz) are output by an outputinstruction specifying the frequency.ABSOLUTE MAXIMUM RATINGSParameterSupply VoltageInput VoltageOutput VoltageStorage TemperaturePower DissipationSymbolVOOVIVoTstgPoConditions Limits UnitTa = 25°C -0.3 to 7.0 VTa =25°C -0.3 to VOO+0.3 VTa = 25°C -0.3 to VOO+0.3 V- -55 to 125 °CTa = 25°C 200 mWOPERATING CONDITIONSParameterOperating VoltageMemory RetensionVoltageOperating TemperatureSymbolVOOVOOMToprLimitsUnit2.5 to 6.0 V1.2to 6.0V-20 to 75 °CDC CHARACTERISTICS(VOO = 3V, Ta = -20 to 75°C)Parameter,SymbolConditionsLimitsMin. Typ. Max.Unit"H" Input VoltageVIHVOO=3VVOO=6V2.2 - - V4.4 - - -V"L" Input VoltageVILVOO=3VVOO=6V- - 0.8 V- - 1.6 V"H" Output Current (1)"L" Output Current (1)"H" Output Current (2)"L" Output Current (2)"H" Output Current (3)"L" Output Current(3)10HllOLlIOH2IOL2IOH3IOL303,0.OPOUTC,-C,0,,02, BOVOH=2.6V -200 - - p.,AVOL=O.4V 500 - - p.,AVOH=2.6V -1 - - mAVOL=O.4V 10 - - p.,AVOH=2.6V -20 - - p.,AVOL=0.4V 10 - - p.,A133

• MSM6052 .------~--------~--------------------------------~DC CHARACTERISTICS (CONT.)ParameterSymbolConditionsMin.LimitsTyp. Max.Unit"H" Output Current (4) 10H."L" Output Current (4)"H" Output Current (5)"L" Output Current (5)Pull-up ResistanceIOL410Hs10LsRUpPull down Rdwon 1Resistance (1)Pull down Rdwon 2Resistance (2)Input Leak CurrentCurrentConsumption (1)CurrentConsumption (2)Memory retentionCurrentIlLlOOplOOT100M10,- 10. VOH=2.6V10EEO , -E04 VOL=O.4VVOH=2.6V32 kHzVOL=O.4VHSR,-Ra1,-14, AC, TEST10,- 104 o :SVIN :SVOOVOO= 2.5 to 6.0VOTMFoutput VOO=3VoffVOO=6VOTMFoutput VOO=3VonVOO=6VONHOOKTa=25°CVOO=2.5VTa=-20t075°C-150 - - /LA300 - - /LA-40 - - /LA25 - - /LA17 - 150 kO33 - 300 kO10 100 kO- - ±2 /LA- 0.3 0.6 mA- 1.2 2.4 mA- 1.2 2.4 mA-- 3.5 7.0 mA- 0.01 0.2 /LA- - 2 /LAAC CHARACTERISTICS(VOO = 3V, Ta = -20 to 75°C)ParameterSymbolConditions,Min.LimitsTyp. Max.UnitKey Input TimeTone Output VoltageTKINVOUTVOO=2.5 to 6.0VRow onlyRL =1 kOVOO=2.5VVOO=4.0VVOO=6.0V33 - - ms150 250 350200 350 570 mV300 480 850 rmsHigh/Low Level RatioOistortion RatiodBCR%OISVOO=2.5 to 6.0VRL=l kO1 2 3 dB- 1 5 %Rise/FaliTime (1)Rise/Fall Time (2)tTLHltTHLltTLH2······tTHL203,04, OP OUTCL=50 pFC,-C4CL=50 pF- - 0.5- - 0.5- - 0.5- - 10/LS/LSRise/Fall Time (3)tTLH3tTHL30,,02, BO, 32 kHzCL=50 pF- - 5- - 10/LSRise/Fall Time (4)tTLH4tTHL410,-104, 10E, EO, -.... E04CL=50 pF- - 1- - 1/LS134

---------------------------------------------------.. MSM6052 •DESCRIPTION OF INSTRUCTIONSMnemonicInstruction Code1312 11 1 10 1 9 1 8 7 6 5 1 4 3 21 1 1 0OperationADD ACC,AP 0 0 0 0 0 P 0 1 0 0 A AP +- (AP) + ACCADD #D,AP 0 1 1 0 0 P D A AP +-(AP) + D() ADCAP 0 0 0 0 0 P 0 1 0 1 A AP +- (AP) + ACC + C·til.Q SUB ACC,AP 0 0 0 0 1 P 0 1 0 0 A AP +- (AP) - ACC1:1c:

• MSM6052 •• -------------------------------------------------DESCRIPTION OF INSTRUCTIONS (CONT.)MnemonicInstruction Code1312 11 10 9 8 7 6 5 4 3 2 1 0OperationCHGAX 1 1 1 0 0 0 X A (AX) --ACCROAR 1 1 0 0 0 0 0 0 0 0 0 0 0 0 ACC -(AR,)ROAR+H 1 1 0 0 0 0 0 0 1 Oil 0 0 0 0 ACC - (AR,), AR, -AR,±lACC-(AR,)ROAR+H,Z 1 1 0 0 0 0 0 1 o Oil 0 0 0 0 if (AR ,)=0 then PC - PC + 1else AR,-AR, ±1, repeatACC -(AR,)ROAR+H,N 1 1 0 00 0 1 0 o Oil 0 0 0 0 if (AR ');FO then PC - PC + 1else AR, - AR, ±1, repeatACC - (AR,), L-L-1ROAR + H, Z, L 1 1 0 0 1 0 0 1 o Oil 0 0 0 0 if (AR ,) =0 or L=Othen PC- PC+lelse AR, - AR, ±1, repeatACC - (AR ,), L - L - 1ROAR+H,N,L 1 1 0 0 1 0 1 0 o Oil 0 0 0 0 if (AR ,)"fO or L=Othen PC -- PC + 1else AR, -AR, ±1 ,repeat....~MVAR 1 1 0 1 0 0 0 0 0 0 0 0 0 0 AR2-(AR,)Ulc: MVAR + (-) 1 1 0 1 0 0 0 0 1 Oil 0 0 0 0 AR2- (AR,),~ AR,-AR, ±1 ,AR2-AR2 ±1.l!:!roAR2-(AR,),Cl MVAR+H,Z 1 1 0 1 0 0 0 1 o Oil 0 0 0 0 if (AR ,)=0 then PC - PC +1else AR, -AR,±l,AR2 - AR2±1, repeatAR2-(AR,)MVAR+H,N 1 1 0 1 0 0 1 0 o Oil 0 0 0 0 if (AR ,) 1'0 then PC - PC + 1else AR,-AR, ± 1,AR2 - AR2±1, repeatAR2-(AR,), L -L-1MVAR+H,L 1 1 0 1 1 0 0 0 o Oil 0 0 0 0 if L=O then PC - PC +1else AR, - AR , ± 1,AR2 - AR2± 1, repeatAR2-(AR,),L-L-1if (AR ,) =0 or L=OMVAR + H,Z, L 1 1 0 1 1 0 0 1 o Oil 0 0 0 0 then PC - PC +1else AR,-AR, ± 1,AR2 - AR2± 1, repeatAR2-(AR,), L-L-lif (AR,)+O or L=OMVAR+H,N,L 1 1 0 1 1 0 1 0 o Oil 0 0 0 0 then PC .-c PC + 1else AR, - AR, ± 1 ,AR2 - AR2 ± 1, repeatQ) CALLadrs 1 0 1 8'0 a9 aa a 7 a 6 a 5 a 4 a 3 a 2 a, ao STACK - (PC), PC - adrsc::s RET 0 0 0 0 0 0 1 1 0 0 0 0 0 0 PC -- (STACK) + 1e.0 RTI 0 0 0 0 1 0 1 1 0 0 0 0 0 0 PC - (STACK) or:::lCI)PC --(STACK) +1136

--------------------------------------------------e. MSM6052 •DESCRIPTION OF INSTRUCTIONS (CONT.)MnemonicInstruction Code1312 11 10 9 8 7 6 5 4 3 2 1 . 0OperationJMP adrs 1 0 o a 10 a 9 aa a 1 a 6 a 5 a4 a3 a 2 a 1 ao PC-adrse.E::I JMP@AP 0 0 0 0 0 P 1 1 0 1 A PC - (PC) + (AP) + 1..,JMPIO @AP 0 0 0 0 1 P 1 1 0 1 A PC - (PC) + ((AP) A 7H} +1BEQnif Z=1 then PC-PC - n or(BZEn) 1 1 1 0 1 P 0 1 0 n4 n3 n 2 n 1 no PC-PC+n+1else-PC-PC+1BNEnif Z=O then PC-PC - n or(BNZn) 1 1 1 0 1 P 1 1 o n4 n3 n2 n 1 no PC-PC+n+1else PC - PC +1if C=1 then PC - PC -n orBCSn 1 1 1 0 1 P 0 0 o n4 n3 n 2 n 1 no PC-PC+n +1else PC - PC +1if C=O then PC - PC - n orBCCn 1 1 1 0 1 P 1 0 o n4 n3 n 2 n 1 no PC-PC+n+1.c else PC - PC +1(.)c:asif G=1 then PC -PC - n orOJ BGTn 1 1 1 0 1 P 0 0 1 n4 n3 n 2 n 1 no PC-PC+n+1else. PC - PC +1if G=O then PC -PC - norBLEn 1 1 1 0 1 P 1 0 1 n4 n3 n 2 n 1 no PC -PC +n+1else PC - PC +1ifG=10rZ=1BGEn 1 1 1 0 1 P 0 1 1 n4 n3 n2 n 1 no then PC - PC - n orPC-PC+n+1,else PC - PC +1if G=O and Z=OBLTn 1 1 1 0 1 P 1 1 1 n4 n3 n 2 n 1 no then PC - PC -n orPC-PC+n+1else PC - PC+ 1INPORT,AP 0 0 0 1 0 P PL A AP-(PORT);::."5::Ie.e.- OUTAP,PORT 0 0 1 o PH P PL A PORT-lAP)c:::I-0 OUT #D, PORT 0 0 1 1 PH 0 PL D PORT-DSTOP 0 0 1 1 1 0 0 0 0 0 0 0 0 0 Stop system clockIII HALT 0 0 1 1 1 0 0 0 0 1 0 0 0 0 Halt CPU.0;.c ACT 0 0 1 1 1 0 0 0 1 0 0 0 0 0 Activate CPU ,(5"0c: EI 0 0 1 1 1 0 0 1 1 0 1 0 0 0 Enable timer interruptasDI 0 0 1 1 1 0 0 1 1 0 0 1 0 0 . Disable timer interruptgc:0 ET 0 0 1 1 1 0 0 1 1 0 0 0 1 0 Enable timer activate(.):::l DT 0 0 1 1 1 0 0 1 1 0 0 0 0 1 Disable timer activateQ.0 EC 0 O. 1 1 1 0 0 1 1 1 1 0 0 0 Enable output port (C l-C4) .DC 0 0 1 1 1 0 0 1 1 1 0 1 0 0 Disable output port (Cl-C4)137

• MSM6052 •• ----------~------------------~----------------­D"ESCRIPTION OF INSTRUCTIONS (CONT.)ef!!"MnemonicInstruction Code1312 11 10 9 8 7 6 5 4 3 2 1 0OperationOM 0 0 1 1 1 0 0 1 1 1 0 0 1 0 Set 110 port (101-104) tooutput modeCCll 1M 0 0 1 1 1 0 0 1 1 1 0 0 0 1 Set 1/0 port (101-104) too~00 input mode::>-0Q.c()

OKI semiconductorMSM6352CMOS 4BIT SINGLE CHIP LOW POWER MICROCONTROLLER FORTELEPHONEGENERAL DESCRIPTIONThe OKI MSM6352 is a low-power, high-performance single-chip 4-bit microcontroller employingcomplementary metal oxide semiconductor technology, especially designed for use in sophisticatedtelephone sets. Integrated onto a single chip are a 4-bit ALU, 28K bits of mask programmable ROM,2560 bits of data RAM, programmable timer, oscillator, 1 2-bits of input port, 1 2-bits of output port and4-bits of input/output port. In addition to these units, a DTMF generator is provided.With the MSM6352, sophisticated telephone sets become feasible through a single chip insteadof the conventional 3-chip configuration.FEATURES• Low Power Consumption 0.3mA Typical @3V(DTMF output off)• 2048 x 14 Internal ROM• 640 x 4 Internal RAM• 3 x 4 Input Port• 3 x 4 Output Port• 1 x 4 Input/Output Port• DTMF Generator (Single Tone Mode or DualTone Mode)• Buzzer Sound Output• 4 Bits Programmable Timer Applicable forOutput of Dial Pulse• Watch Dog Timer• On Hook Dialing and Off Hook DialingFunctionFUNCTIONAL BLOCK DIAGRAM• InterruptProgrammable Timer-InterruptReal Time Interrupt• 5 Level Stack• Power Down Mode• 52 Instruction Set• Instructions Useful for Data Management(Data Search and Block Data Transfer)• 1.5 to 5.0V Operating Voltage• Low Voltage Detector• 3.58 MHz Oscillator• 1 7.9 fls I nstruction Cycle• -20 to 75°C Operating Temperature• 28 Pin DIP or 40 Pin DIP• Software Compatibility with MSM6052R.R2~~R5~~H8DATA RAM640 word ~"bit1112.3.~C.g~-Col8~03O.EO.E02E03EO •• 0.Ig~104_INSTRUCTIONDECODERPROGRAM ROM2048 word)( 14 bilXTXr32kHzTIMINGGENERATORI IAC TE~TI I"00 VSS~====~_=_=_=_=__ =_=_= __ =_=_=_=_= __~_J139

• MSM6352 • -------------------...:------PIN CONFIGURATION(Top View) 40 Lead Plastic DIP(Top View) 28 Lead Plastic DIPLOGIC SYMBOLKEYBOARD [INPUTE01E02E03E03] OUTPUT PORT101KEYBOARD [ 102INPUT 10310410EINPUT PORT [DPOUTDTMFOUT] 10PORTOUTPUT ENABLEDIALPUSLEOUTPUTDTMFOUTPUTC1 BD BUZZER OUTPUTKEYBOARD [ C2OUTPUT C3 32kHz 32kHz OUTPUTC4ACRESET01OUTPUT [ 02 TEST TESTPORT 0304) POWERHOOK SWITCHOSCILLATION (140

---------------------'-----. MSM6352 •PIN DESCRIPTIONDesignationVDDVSSACTESTXT,XTHSDPOUTDTMFOUTBD32kHzR1 -:- R4R5-RsPource sourceCircuit ground potentialFunctionTerminal to clear internal logic, pulled down to VSS.After power is turned on, the MSM6052 must be reset by this terminal.Terminal to test internal logic, pulled down to VSS.This terminal must be open in normal operation.Input and output terminals of oscillator inverter.3.58 MHz ceramic resonator is connected to these terminals.Input terminal connected to the hook switch, pulled up tp VDD.Output terminal of dial pulse.Dial pulse rate (10 pps or20 pps) and Make Break ratio (40% or 33 %) canbe selected by software.Output terminal of DTMF signalOutput terminal of buzzer soundOutput terminal of 32 kHz clockInput port pulled down to VSS.11-14 Input port having clocked pull-down resistor to VSS.Only when this port is accessed, pull-down resistors are connected to thisport.C1-C401-04Output port101-104 Tri-state bidirectional port10EOutput terminalWhen 101 -104 is accessed,input completion signal (when read) orload signal (when written) is output from 10E terminal.141

I. IOlMS-64 SERIES

OKI semiconductorMSM6404HIGH-SPEED 4-BIT SINGLE CHIP MICROCQNTROLLERGENERAL DESCRIPTIONThe OKI MSM6404 microcontroller is a low power, high-performance single-chip deviceimplemented in complementary metal oxide semiconductor technology. 32K bits of mask programROM, 1024 bits of data RAM, 36 Input/Output lines, a programmable timer/event-counter, andoscillator are integrated onto one chip. Program memory is byte wide and data-paths are organized in4 bit nibbles. RAM and I/O lines are bit addressable. 122 instructi.ons. include binary, BCDoperations; bit set, reset, test; a bit I/O; relative jumps; multifunctional instructional {increment,modify, skip) a bit wide table output; subroutine call and return.FEATURES• 4000 x a MASK ROMAn evaluation board is available for up to Bkx B.• 256 x 4 RAM (including the stack area)• 9 x 4 Ports, 36 I/O lines4 lines for input ports having a latch, and theother 32 lines for bit operation are available.• Three built-in counters1 2-bit time-base counter1 2-bit programmable timera-bit high-speed programmable timer/eventcounter• Built-in a-bit serial I/O register (with 3-bitcounter)• Five interrupts with five priority levels(4 internal, 1 external)• 32 stack levels {in RAM)• Power down features• Instruction execution time952 ns 4.2 MHz clock• Instruction systems suitable for control• 122 instructions• Mask optionP60-63 for input port• Full static operation• Low power consumptionTYP O.4,.,.W at VDD=2VTYP 5,.,.W at VDD=5V OHz clock• 5V single power supply, 42-pin DIP or44-pin FLATBLOCK DIAGRAM3210 3210 3210 3210 32111 3210_3210 3210INTO Il;!1 LLsoSCK eTa elKLTCK LSI145

• MSM6404 •• -------------~-----'------~-PIN CONFIGURATION(Top View) 42-pin Plastic DIPP40P4lP42P43P30P20P21P22P23POOPOIP02P03(Top View) 44-pln Plastic Flat PackageP310P32P33OSC,esc.TESTP20P21P22P23~lli::?~~If~f0 - '" 8 0 Z!? !? z 0 0Q.1L 1LQ.coii: '" ['" gQ.P62P61P60NCP73P72P71P90P83P82P81PIN DESCRIPTIONPin nameInput/C!utputFunctionWhen resetpo~P01/SCKP02/S0P03/SIP1O/CINP11/TMOP12/TCKP13P20/INTP21P22P23Input/output. Input/outputInputP30-33 Input/outputP4O-43Input/outputP50-53 Input/outputP60-63 Input/outputP70-73 Input/outputP80-83 Input/outputOSCoOSC,TESTRESETVOOGNOInput/outputOutputInput4-bit input/output port.POl to P03 are also used as serial interfaceterminals.4-bit input port with latch .Built-in pull up register for all bit input.4-bit input port with a latch. P20 is shared with INTinput. (Fall trigger input) P21 - 23 are level input.Built-in pull up register for all bit input.4-bit input/outp·ut port4-bit input/output port I .4-bit input/output port4-bit input/output port *14-bit inpllt/output port4-bit input/output portI 8-bit output pMX'tal connection terminal for system clock oscillation(Test terminal for Maker)System reset input terminalPower source voltage supply111"111"The latch isreset."1 "ClO""0""0"ClO""0"OscillationwavePulseoutputNote: When each port is used for output, it is possible to drive one TTL (one input).*1 Can be made as a port dedicated to input (mask option).146

-------------------------. MSM6404 •INSTRUCTION LISTMnemonic Description Code Byte CycleLAI n A-n 9n 1 1LLI n L-n 8n 1 1LHLI nn HL-nn 15nn 2 2LMI nn M(w)-nn 14nn 2 2LAL A-L 21 1 1LLA L-A 2D 1 1LAH A-H 22 1 1LHA H-A 2E 1 1LAM A-M 38 1 1LMA M-A 2F 1 1LAM+ A -M, L -L+1, Skip if L=O 24 1 10.&. LAM- A -M, L -L-1, Skip ifL=F 25 1 1.c(/)::JCL-0'" 0...JLMA+ M -A, L -L+1 ,SkipifL=O 26 1 1LMA- M -A, L-L-1 ,SkipifL=F 27 1 1LAMM n2 A-M,H-HVn, 39-3B 1 1LAMD mm A-Md 10mm 2 2LMAD mm Md-A 11mm 2 2LMTD mm Md(w) - T (M(w), A), T =ROM table 19mm 2 3LMCT M(w)-CT 3E59 2 2LCTM CT-M(w) 3E51 2 2LMSR M(w)-SR 3E5A 2 2LSRM SR-M(w) 3E52 2 2LTMM TM-(M(w),A) 3E50 2 2PUSH ST -C, A, H, L, SP -SP-4 1C 1 3POP C, A, H, L -, ST SP -SP+4 1D 1 3X A~M 28 1 1Q)C> n,

eMSM6404e-------------------------------------------------INSTRUCTION LIST (Continued)Mnemonic Description Code Byte CycleINH H -H+1. Skip if M =0 32 1 1c: INMD mm Md -Md+1.SkipifMd =0 12mm 2 2IIIE~ DCA A -A-1. Skip if A =F34 1 1" IIICl:;:, DCM M-M-1.SkipifM =F 37 1 1c:IIIE DCll -l-1.Skip ifL=F35 1 1~.E " DCH H -H-1.SkipifH =F36 1 1DCMD mm Md -Md-1.SkipifMd =F 13mm 2 2ADS A - A+M. Skip if Cy =1 02 1 1ADCS A. C -A+M+C. Skip if Cy=1 01 1 1ADC A.C-A+M+C 03 1 1AIS n A -A+n. Skip if Cy =1 3E4n 2 2DAA A-A+6 06 1 1DAS A-A+10 OA 1 1AND A-AVM 00 1 1~"OR A-AVM 05 1 1E:5EOR A-AVM 04 1 1~~"'CMA A-A OB 1 1CIA A-A+1 OC , 1 1RAl Rotate left with C OE 1 1RAR Rotate Right with C OF 1 1TC SkipifC=1 09 1 1SC C-1 07 1 1RC C-O 08 1 1CAl n SkipifA=n 3EOn 2 2CLI n Skipifl =n 3E2n 2 20.ECPI p. n Skip if Pp=n 17pn 2 200CMI n Skip if M =n 3E1n 2 2c:gCAM SkipifA=M 16 1 1TAB n2 Skip if Abit (n2) =1 54-57 1 1RAB n2 Abit(n,)-O 64-67 1 1~III0.0SA8 n2 Abit(n,)-174-77 1 1iii TM8 n2 Skip if Mbit (n,) =1 58-5B 1 1RMB n2 Mbit(n,,)-O 68-68 1 1148

-------------------------. MSM6404 •INSTRUCTION LIST (Continued)Mnemonic Description Code Byte Cycle5MB n Mbit(n,)-l 78-7B 1 1TFB n2 Skip if Fbit (n,) =1 5C-5F 1 1RFB n2 Fbit(n,) -0 SC-SF 1 1SFB n2 Fbit(n,) -1 7C-7F 1 1c:0TPB n2 Skip if Pbil (n,) ';'1 50-53 1e1CDc. RPB n2 Pbit(n,) -0 SO-S3 1 10iiiSPB n Pbit(n,)-l 70-73 1 1TPBO pn2 Skip if Ppbit (n,) =1 30pO-3 2 2RPBO pn2 Ppbit (n,) =0 30p4-' 2 2SPBO pn2 Ppbit (n,) =1 30pB-B 2 2MEl MEIF-1 3ESO 2 2MOl MEIF-O 3ES1 2 2EITB EITBF-1 30C9 2 2EITM EITMF-1 30CA 2 2EICT EICTF-1 30CB 2 2EIEX EIEXF-1 30C8 2 2OITB EITBF-O 30C5 2 2OITM EITMF-O 30CS 2 2OICT EICTF-O 30C7 2 2OIEX EIEXF-O 30C4 2 2C. TITB Skip If EITBF =1 30C1 2 2::lt:::.Sl TITM Skip If EITMF =1 30C2 2 2oSTICT Skip If EICTF =1 30C3 2 2TIEX Skip If EIEXF =1 30CO 2 2TOEX Skip If IROEX =1 3020 2 2TOTB Skip If IROTB =1 3000 2 2TOTM Skip If IROTM =1 3001 2 2TOCT Skip If IROCT =1 3002 2 2TOSR Skip If IROSR =1 3003 2 2ROEX IROEX-O 3024 2 2ROTB II~OTB-O 3004 2 2ROTM IROTM-O 3005 2 2ROCT IROCT-O 300S 2 2ROSR IROSR-O 3007 2 2149

• MSM6404 • ----:------'------------------INSTRUCTION LIST (Continued)Mnemonic Description Code Byte CycleECT CTF -1 (start) 3DBB 2 2E ESR SRF -1 (start) 3DBA 2 2~ .~.c: Q).- '"DCT CTF ..... O (stop) 3DB7 2 2(/) ~li;-.::::l0DSR SRF -0 (stop) 3DB6 2 2TCT Skip If CTF =1 3DB3 2 20 TSR Skip If SRF =1 3DB2 2 2JCP a6 PC-a6 CO-FF 1 1JP a'2 PC-a'2 4a'2 2 2CZPaST - PC+l , PC -2a,SP-SP-4Ba 1 4IfI.c:()c'"!IiCAL a12ST -PC+2, PC -a 12,SP-SP-4Aa'2 2 4OPTPs, P4 -T (M(w), A),T=ROMtable18 1 3RT PC -ST, SP -SP+4 IE 1 4RTSPC -ST, SP -SP+4,Skip unconditionalIF 1 4'JA PC -(PC -A)+1 IA 1 1JM PC - (M(w), A) IB 1 2:; IP A-P 20 1 1Q.:; IPD P A-Pp 3DpD 2 2S2:;Q.OP P-A23 1 1EOPD P Pp-A 3DpC 2 2NOP No Operation 00 1 1E!::J- HALT HaltCPU 3DB8 2 2a. c08STOP Slop Clock 3DB9 2 2150

----~----------------------------------------------.MSM6404.ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions LimitsSupply Voltage Voo -0.St07, VInput Voltage VI Ta=25°C -O.Sto VOO VOutput Voltage Vo -O.StoVOO VTa = 25°C per package 200 max. mWPower DissipationPoTa = 25°C per output 50 max. mWStorage Temperature Tstg - -55to+150 DC,UnitOPERATING RANGESupply VoltageParameter Symbol Conditions Limits UnitVOOI(OSC) ~ 1 MHz St06 VI(OSC) :;;4.2 MHz 4.5t05.5 VData-Hold Voltage VOOH I (OSC) =OHz 2t06 VOperating Temperature TOp - -40 to +S5 DCMOSLoad 15FanOut N -TIL Load 1DC CHARACTERISTICS(Voo = 5V± 10%, Ta = -40 to +85°C)Parameter Symbol Conditions Min. Typ. Max. Unit"H"lnput Voltage'1:2 VIH - 2.4 - VOO V"H"lnput Voltage'S;'4 VIH - S.6 - VOO V"L"lnput Voltage VIL - -O.S - O.S V"H" Output Voltage'l :5 VOH 10="':15p.A 4.2 - - V"L" Output Voltage'l VOL 10=1.6mA -' - 0.4 V"L" Output Voltage '5 VOL 10 = 15p.A - - 0.4 VInput Current'S IIH/IIL VI=VOO/OV - - 15/-15 p.AInput Current'2:4 IIH/IIL VI=VOO/OV - - 1 I-SO p.A"H" Output Current'l 10H VO=2.4V -0.1 - - mA"H" OutputCurrent'l 10H VO= OAV - - -1.2 mAInput Capacity CI 1=1 MHz - 5 -- -Output Capacity Co Ta=25°C 7VOO=2V, no load-Current DissipationTa=25°C0.2 5 p.A(when stop condition)IOOSNo load - 1 100 p.ApFCurrent Dissipation 100Quarts oscillation1=4 MHz, no load- 6 12 mA'1 Applied to PO, Pl , PS, P4, P5, P6, P7 and PS'2 Applied to P2 's Applied to OSCo '4 Applied to RESET '5 Applied to OSC,151

• MSM6404 .'--------------------------AC CHARACTERISTICS(VDD = 5V± 10%, Ta = -40° to +85°C)Parameter Symbol Conditions Min. Typ. Max. UnitDClock Pulse WidthClock (OSC)tq,W-119 - -nSCycle Time tCY - 952 - - nSInput Data Setup Time tDS - 120 - - nSInput Data Hold Time tDH - 120 - - nSInput Data, InputClock Pulse WidthtDW - 120 - - nSSR Data Setup Time tss - 120 - - nSSR Data Hold Time tSH - 120 - - nSData Delay Time tDR CL=15pF - - tCy+300 nSData Delay Time atMode SwitchingData Delay Time atOPT InstructionData Delay Time atOPT InstructionCT ITM Data DelayTime using TBC ClockSR/TM Data DelayTime using PR ClockCT Data Delay Ti meusing PR ClockCT Data Delay Timeusing External ClocktDCR CL = 15pF - - 7/8tCy+300 nStDl1 CL = 15pF - - 6/8tCy+300 nStDI2 CL = 15pF - - 7/8tCy+300 nStCT/tTT CL = 15pF - - 2/8tCy+360 nStSR/tTR CL = 15pF - - tCy+480 nStCR CL= 15pF - - 1018 ICY + 480 nStcp CL = 15pF - - 2/8tCY+360 nSSR/TM Data DelayTime using External tSp/tTP CL =50pF - - 360 nSClockJSR Clock Invalid Time tSINH - 2/8tCY - - nSINT Invalid Time tliNH - 1/8tCY - - nS152

----------------------------------------------------'. MSM6404.TIMING CHARTSOutput ConditionPO,P"P,p.,p"p,P" p.POIPo,Pllp.P sPOIPllPo,PllOSCO0,1,3PA=4,5,67 or 8TBC clockPA = 9 or AOPT INST.OPT INST.CTTMPOI clock' SRP 12 clock' TMP,O clock' CT0Vi/ifi--rL~I.------------t-DR--------------------------~---~~~--------r-------------tD-C-R-------------~~---------I·, ~-----------tD-I-1----------J---------------.I'.-------------t-D-12----------------~J~------dtCT:tTT~tSR~~~tTR l~1·========tctcRR========~~CT-tcp-SRTM~tsp I---tTP---~, Output Data to port will be clock for SR, TM or CT.153

.MSM6404.,----------------------~------------~--------------Input Condition1MCascOPO.PI.p,p,.p •• p,P 6 .P 7 .P,SR clockTM clock-- tow I---1,---,POISR clockjINPUTI'- DATAtss tSH1MCascOts INHts INH: Po1 (SR clock) INH period during LMSRINST.(Note: POI is used for clock of SR)tIINH: P,o (interrupt) INH period during RPBand RPBD INST.154

--------------------------. MSM6404 •TYP. Current vs Voltage for High State Output(I0H) (YO H)~E:c.P-1.0-0.9-0.8--0.7-0.6-0.5-I---.."""Voo = 6Vr-...Nv'"-0.41\r-- -0.3 I-.. 4V'" '" \\-0.2I-0.10'i~ '\ \ \'" \ \ \2 3 4 5 6 7VOH (V)TYP. Current vs. Voltage for Low State Output(loll (VOL)(Ta = 25°C)~E...J.P201816141210864206V /I---Voo 5V/'IIII[I ",... ~ 4Vf/If'/ ./ I-- 3VfL2 3 4 5 6 7 8 9 10VOL (V)TYP. Maximum Oscillator Frequency vsf(OSC) Temperature(Ta)1110(CL = 15 pF)TYP. Maximum Oscillator Frequency vs.f(OSC) Supply Voltage(YOD)1110(Ta = 25°C. CL = 15 pF)98""N 7:c~6Uen9- 543r-....~oo=5V.......................r--98N 7:c~ 6UenQ 543////V/22o-40 -20 0 20 40 60 80 10002345678Ta (OC)Voo (V)155

e MSM6404 e-------------------.,..--------TVP.Supply Current YS. Supply VoltageODD)(VDD)10m(Ta=25°C)1 (OSC)=4MHz::No Load1mV.#'~-1JHZ2JHZ500kHz~100!,100kHzi-- OHz/',.....lOOno 2 3 4 5 6 7 8 9 10VOO(V)156

OKI semiconductorMSM6404VSMSM6404 PIGGY BACKGENERAL DESCRIPTIONThe MSM6404VS is a device whose built-in ROM is replaced by external EPROM using the piggybackmethod.FEATURES• Supply Voltage: 5V ± 5% • Frequency: DC - 4.2 MHz • Operating Temperature: 0 - 70°CNote: There are a few differences in the electrical characteristics of this chip and the evaluation chip.Please refer to next page for the detail.PUTTING METHOD OF ROMPlease refer to drawing below.M6404VSOKIJAPAN4X30PIN CONFIGURATIONPin Connection between MSM6404 VS and EPROMVeeTo AO - A 12of MSM6404VSToDl0 -D7of MSM6404VSNoIe: When putting 2732A,pin 1,2,27, 28 are not used.11 ADDRESS'Y11 DATA'YA12All10987654321AODO1.2345607GND- _vPP 1"""'-'""28A12 2 27A7 3 26A6 4 25A5 5 24A4 6 23A3 7276422A2 8 21Al 9 20AO 10 1900 11 1801 12 1702 13 16GND 14 15Vcc_PGM-N.C.-A8-A9All~~O-'CEg~::::=.--05-04-031157

• MSM6404VS .--------------------~--------------r_--~--------DIFFERENCES BETWEEN MSM6404 AND MSM6404VS (PIGGY-BACK)Item 6404 6404VS (Piggy-Back)1. Port Port PO, 1,3 are set to "1 " and port Port PO, 1,3 are set to "1" and port 2,in itialization 2,4,5,6,7,8 are reset to "0" 4,5,6,7,8 are reset to "0" during resetduring reset directly by signal put into the cycle being executed.RESET..2. Timer After being reset, timer stops It is undecidable whether the timerOperation counting until data are set in it. starts counting or not after being reset.Therefore, the timer should beinitialized by software.3. Shift registor Serial Out F/F (SOF/F) is set to "0" It is undecidable whether Serial Outafter being reset.F/F (SOF/F) is set to "0" or "1" afterbeing reset. Therefore Serial Out F/Fshould be initialized by software.4. Portinput/outputtimingInternal clock ~rData are inputat this momentInternal clockJlILtData are inputat this momentSynchronizedInternal clock with falling edge Internal clock ~~k=Data are outputat this moment~Data are outputat this moment5. Portinput/output(maracteristics)TTL FO=1LSTTL FO=1(lOL = 1.6 rnA O.4V)(lOL = 0.4 rnA O.4V)4- ~VDDP20-3 P20-3VDDVDDTTL compatible inputCMOS inputPOO-P83~ POO-83o-----t>-(Except P20-3)(Except P20-3)Available 4K byte Accessible up to 8K byteROM capacityIPLcall Not available Availableinstruction,158

OKI semiconductorMSM6408HIGH-SPEED 4-BIT SINGLE CHIP MICROCONTROLLERGENERAL DESCRIPTIONThe OKI MSM6408 microcontroller is a low power, high-performance single-chip deviceimplemented in complementary metal oxide semiconductor technology. 64K bits of mask programROM, 1024 bits of data RAM, 36 Input/Output lines, a programmable timer/event-counter, andoscillator are integrated onto one chip. Program memory is byte wide and data-paths are organized in4-bit nibbles. RAM and I/O lines are bit addressable. 122 instructions include binary, BCDoperations; bit set, reset, test; 8-bit I/O; relative jumps; multifunctional instructional (increment,modify, skip) 8-bit wide table output; subroutine call and return.FEATURES• 8000 x 8 MASK ROMAn evaluation board is available for up to 8Kx 8.• 256 x 4 RAM (including the stack area)• 9 x 4 Ports, 36 I/O lines4 lines for input ports having a latch, and theother 32 lines for bit operation are available.• Three built-in counters1 2-bit time-base counter12-bit programmable timer8-bit high-speed programmable timer/eventcounter• Built-in 8-bit serial I/O register (with 3-bitcounter)• Five interrupts with five priority levels(4 internal,1 external)• 32 stack levels (in RAM)• Power down features• Instruction execution time1.0 P.s 4.0 MHz clock• Instruction systems suitable for control• 1 22 instructions• Mask optionP60-63 for input port• Full static operation• Low power consumptionTYP 0.4p.W at VDD=2VTYP 5p.W at VDD=5V OHz clock• 5V single power supply, 42-pin DIP or44-pin FLATBLOCK DIAGRAM3210 3210 3210 3210 3210 3210_3UO 3210INTO L;!I, lLsoSCK eTa eLKTCK LSI159

.MSM6408·------------------------------------~--------~PIN CONFIGURATION(Top View) 42-pin Plastic DIP44 Pin Plastic Flat Package~ " '" _ 0 0",,,, 00it l :. :.....if if> 0. 0.If "P20P60P73P72P71P310P32P33oseoOSC,TESTP20P21 P83 P21P22 P82 P22P23POOPOlP02P03P13P12PllP23Pl08 ~ '" " o " 00.'" "It It z z 0: 0: ii: r."Ii:0.Pe2P60NCP73P72P71P90P83P82PelPIN DESCRIPTIONpo~Pin name Input/~utput FunctionP01/SCKP02/S0P03/SIP10/CINP11/TMOP12/TCKP13P20/INTP21P22P23Input/outputInput/outputInput4-bit input/output port.P01 to P03 are also used as serial interfaceterminals.4-bit input port with latch.Built-in pull up register for all bit input.P30-33 Input/output 4-bit input/output portP40-43 Input/output 4-bit input/output portP50-53 Input/output 4-bit input/output port4-billnput port with a latch. P20 is shared with INTinput. (l7all trigger input) P21 - 23 are levei in!lut.Built-in pull up register for all bit input.P60-63 Input/output 4-bit input/output port'1P70-73 Input/output 4-bit input/output portPSO-S3 Input/output 4-bit input/output portOSCoOSC,Input/outputTEST Output (Test terminal for Maker)I'S-bit output portX'tal connection terminal for system clock oscillationRESET Input ,System reset input terminalVDDGNDPower source voltage supplyNote: When each port is used for output, it is possible to drive one TTL (one input).*1· Can be made as a port dedicated to input (mask option).When reset111 ""1 "The latch isreSet."1 It"0""0""orr"0"110"OscillationwavePulse output160

--------------------------. MSM6408 •INSTRUCTION LIST0.0CL.If:.,Mnemonic Descri ption Code 8yte CycleLAI n A-n 9n 1 1LLI n L-n 8n 1 1LHLI nn HL-nn 15nn 2 2LMI nn M(w)-nn 14nn 2 2LAL A-L 21 1 1LLA L-A 2D 1 1LAH A-H 22 1 1LHA H-A 2E 1 1LAM A-M 38 1 1LMA M-A 2F 1 1LAM+ A -M, L -L+1, Skip if L=O 24 1 1LAM- A -M, L -L-1, SkipifL=F 25 1 1::lCL LMA+ M -A, L -L+1, Skip if L=O 26 1 1-ti010-'LMA- M -A, L -L-1, Skip ifL=F 271 1LAMM n, A-M,H-HVn, 39-38 1 1LAMD mm A-Md 10mm 2 2LMAD mm Md-A 11mm 2 2LMTD mm Md(w) - T (M(w), A), T =ROM table 19mm 2 3LMCT M(w)-CT 3E59 2 2LCTM CT-M(w) 3E51 2 2LMSR M(w)-SR 3E5A 2 2LSRM SR-M(w) 3E52 2 2LTMM TM - (M(w), A) 3E50 2 2PUSH ST -C, A, H, L, SP -SP-4 1C 1 3POP C, A, H, L, -ST SP -SP+4 1D 1 3Q)Clc01.s:::0>

• MSM6408 • --------------------------INSTRUCTION LIST (Continued)Mnemonic Description Code Byte, CycleINH H -H+1, Skip if M =0 32 1 1CQ)INMD mm Md -Md+1,Skip ifMd =0 12mm 2 2E~0DCA A-A-1, Skip if A =F 34 1 1Q)Cl:;:, DCM M-M-1,SkipifM=F 37 1 1cQ)E~0E0DCl L - l -1 , Skip if l = F 35 1 1DCH H -H-1, Skip if H =F 36 1 1DCMD mm Md!-Md-1, Skip if Md = F 13mm 2 2ADS A -A+M, Skip ifCy =1 02 1 1ADCS A, C -A+M+C, Skip ifCy=l 01 1 1ADC A,C-A+M+C 03 1 1AIS n A -A+n, Skip ifCy =1 3E4n 2 2DAA A-A+6 06 1 1DAS A-A+10 OA 1 1AND A-AVM OD 1 1~E ORA-AVM05 1 1:::~ EOR A-AVM 04 1 1CMA A-A OB 1 1CIA A-A+1 OC 1 1RAl Rotate left with C OE 1 1RAR Rotate Right with C OF 1 1TC SkipifC =1 09 1 1SC C-1 07 1 1RC C-O 08 1 1CAl n Skipif A =n 3EOn 2 2CLI n Skip ifl =n 3E2n 2 2~'" c. CPI p,n Skip ifPp=n 17pnE2 20()CMI n SkipifM =n 3E1n 2 2c0CAM SkipifA=M' 16 1 1TAB n2 Skip if Abit (n,) =1 54-57 1 1RAB n2 Abit(n2) -0 64-67 1 1~Q)gSAB n2 Abit(n,) -1 74-77 1 1iii TMB n2 Skip if Mbit (n,) =1 58-5B 1 1RMB n2 Mbit (n,)-O 68-6B 1 1162

-------------------------. MSM6408 •INSTRUCTION LIST (Continued)Mnemonic Description Code Byte Cycle5MB n Mbit(n,)-1 78-7B 1 1TFB n, Skip if Fbit (n,) =1 5C-5F 1 1RFB n, Fbit (n,)-O SC-SF 1 1c: SFB n, Fbit(n,)-1 7C-7F 1 10~ TPB n, Skip if Pbit (n ,) =1 50-53 1 1Q)0-0 RPB n, Pbit (n,)-O SO-S3 1 1iiiSPB n .. Pbit(n,)-1 70-73 1 1TPBO pn, Skip if Ppbit (n,) =1 30pO-3 2 2RPBO pn, Ppbit (n,) =0 30p4-7 2 2SPBO pn, Ppbit (n ,) =1 3Dps-B 2 2MEl MEIF-1 3ESO 2 2MOl MEIF-O 3ES1 2 2EITB EITBF-1 30C9 2 2EITM EITMF-1 30CA 2 2EICT EICTF-1 30CB 2 2EIEX EIEXF-1 30C8 2 2OITB EITBF-O 30C5 2 2OITM EITMF-O 30CS 2 2OICT EICTF-O 30C7 2 2OIEX EIEXF-O 30C4 2 2TITB Skip If EITBF =1 30C1 2 20.2 TITM Skip 11 EITMF =1 30C2 2 2~ETICT Skip 11 EICTF =1 30C3 2 2TIEX Skip 11 EIEXF =1 30CO 2 2TOE X Skip 11 IROEX =1 3020 2 2TOTB Skip If IROTB =1 3000 2 2TOTM Skip 11 IROTM =1 3001 2 2TOCT Skip If IROCT =1 3002 2 2TOSR Skip If IROSR =1 30D3 2 2ROEX IROEX-O 3024 2 2ROTB IROTB-O 3004 2 2ROTM IROTM-O 3005 2 2ROCT IROCT-O 300S 2 2ROSR IROSR -0 3007 2 2163

• MSM6408 • -----..,..--------------------INSTRUCTION LIST (Continued)Mnemonic Description Code Byte CycleECT CTF -1 (start) 3DBB 2 25ESR SRF -1 (start) 3DBA 2 2=:!2\.- .,.r:.G)en ...DCT CTF -0 (stop) 3DB7 2 2... DSR SRF -0 (stop) 3DB6 2 2.!

-------------------------. MSM6408 •ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Limits UnitSupply Voltage VDD -0.3t07 VInput Voltage VI Ta =25°C -0.3toVDD VOutput Voltage Vo -0.3toVDD VTa = 25°C per package 200 max. mWPower DissipationPDTa = 25°C per output 50 max. mWStorage Temperature Tstg - -55 to +150 °COPERATING RANGESupply VoltageParameter Symbol Conditions Limits UnitVDDf(OSC);;;1 MHz 3t06 Vf(OSC) ;;; 4.0 MHz 4.5to 5.5 VData-Hold Voltage VDDH f (OSC) =0 Hz 2t06 VOperating Temperature TOp - -40to +85 °CMOSLoad 15Fan Out N -TTL Load 1DC CHARACTERISTICS(Voo = 5V±1 0%, Ta = -40 to +85°C)Parameter Symbol Conditions Min. Typ. Max. Unit"H" Input Voltage '1,*2 VIH - 2.4 - VDD V"H" Input Voltage '3,*4 VIH - 3.6 .-VDO V"L" Input Voltage VIL - -0.3 - 0.8 V"H" Output Voltage'1,*5 VOH 10=-15/LA 4.2 - - V"L" Output Voltage" VOL 10 =1.6mA - - 0.4 V"L" Output Voltage '5 VOL 10 = 15/LA - - 0.4 VInput Current'3 IIH/IIL VI =VDD/OV - - 15/-15 /LAInput Current'2, '4 IIH/IIL VI =VDD/OV - - 1/-30 /LA"H" Output Current'1 10H VO=2.4V -0.1 - - mA"H" Output Current'1 10H VO=0.4V - - -1.2 rnAInput Capacity CI f=1MHz - 5pFOutput CapacityCoTa=25°C - 7 -VDD=2V, no load-Current Dissipation0.2 5Ta=25°C/LA(when stop condition)IDDSNo load - 1 100 /LACurrent DissipationIDDQuarts oscillation I - 6 12 rnAf=4 MHz, no load'1 Applied to PO, P1 , P3, P4, P5, P6, P7 and P8'2 Applied to P2 '3 AppliedtoOSCo '4 Applied to RESET '5 Applied to OSC 1165

• MSM~408 • --------'-----c-------------------AC CHARACTERISTICS(Voo = 5V±1 0%, Ta = -40 to +85°C)Parameter Symbol Conditions Min. Typ. Max. UnitClock Pulse WidthClock (OSC)tW - 125 - -nSCycle Time tCY 1 - - /LSInput Data Setup Time tDS - 120 - - nSInput Data Hold Time tDH - 120 - - nSIn put Data, In putClock Pulse WidthtDW - 120 - - nSSR Data Setup Time tss - 120 - - nSSR Data Hold Time tSH - 120 - - nSData Delay Ti me tDR CL = 15pF - - tCY +300 nSData Delay Time atMode SwitchingCT ITM Data DelayTime using TBC ClockSR/TM Data DelayTime using PR ClockCT Data DelayTimeusing PR ClockCT Data Delay Ti meusing External ClocktDCR CL = 15pF - - 7/8tCy+300 nStCT/tn CL = 15pF - - 2/8tCY +360 nStSR/tTR CL = 15pF - - ICY +480 nStCR CL=15pF - - 1018 tCY + 480 nStcp CL = 15pF - - '2/8tCY +360 nSSR/TM Data DelayTime using External tSp/tTP CL =50pF - - 360 nSClockSR Clock Invalid Time tSINH 2/8tCY - - nSINT Invalid TimetliNH_.118 tCY - - nS166

------------------------- • MSM6408 •TIMING CHARTSOutput ConditionPo, PI' p.p.,ps'p.P" p.OSC O0,1,3PA=4,5,67 or 8TBC clockPA = 9 or ACTTMW\Jiii-rL~I,------------t-D-R~~~~~~~~~~~~~~~~~~-----~1,----------tD-CR----------f~-------POI clock' SRP 12 clock' TMPIO clock" CTI ~.======~~tCR~=======~PIO ' POI' P12EXT clockCTI----tcP--SRTM-tsptTPI---I--.. Output Data to port will be clock for SR, TM or CT.167

• MSM6408 .--------------------------Input ConditionlMCasc OPO,PI,P,p"p.,p,p.,p"p.--------~i~J~:1f~------------------oSR clockTM clock-tDW-1\POISRclockIINPUT~ DATAtss tSHlMCasc Ots INHts INH: POI (SR clock) INH period during LMSR INST.(Note: POI is used for clock of SR)tIINH: p,. (interrupt) INH period during RPBand RPBD INST.168

--------------------------. MSM6408 •TYP. Current YS Voltage for High State Output(lOH) (VOH)TYP. Current ys. Voltage for Low State Output(lOL) (VOL)~EI.9-1.0-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.10(Ta = 25° C)-r--r--I-......"'"VDD- ~V'"\= 6V......., 4V ~ \~ "'"~I'\. \ \.~ \ \ \2 3 4 5 6 7VOH (V)(Ta = 25°C)20181614~ 12E...J 10.96V I /f..-VPDIIIIrl .,... ~ 4V'/II83V6 /'- 4'J205V2 3 4 5 6 7 8 9 10VOL (V)TYP. Maximum Oscillator Frequency YSf(OSC) Temperature(Ta)(CL = 15 pF)11TYP. Maximum Oscillator Frequency vs.f(OSC) Supply Voltage(VOO)(Ta = 25°C. CL = 15 pF)1101101098"'"N 7I~ 6Gen2 543r-....~DD=5V........-...........r--....98N7I~ 6Gen2 543//V//V22o-40 -20 0 20 40 60 80 10002345678Ta (OC)VDD (V)169

OKI semiconductorMSM6411CMOS 4-BIT SINGLE CHIP MICROCONTROLLERGENERAL DESCRIPTIONThe OKI MSM6411 microcontroller is a low-power, high-performance single-chip deviceimplemented in complementary metal oxide semiconductor technology. 1024 x 8 bits of programROM, 32 x 4 bits of data RAM, 11 Input/Output lines and oscillator. Program memory is byte wideand data paths are organized as 4-bit wide. 63 instructions include binary, logical operations; bit set,reset, test; multifunctional.FEATURES• 1024 x 8 Internal ROM• 32 x 4 Internal RAM• 11 110 Lines (8 I/O Lines, 3 Input Lines)• 8-bit serial I/O Register• 2 Interrupt Levels• 8 Stack Levels• 952 ns 4.2MHz (VOO 5V±1 0%)D FUNCTIONAL BLOCK DIAGRAM• 63 Instructions• Self-Contained Oscillator• -40 to +85°C Oper.ating Temperature• 3 to 6V Operating VOO• Low Power Consumption 5 f.LW Typical(STOP, VOO = 5V, no load)• Mask Option Crystal/CeramicOscillatorINST.DEC.ROM1024 x 8INT$ISOSCKRESET OSCo osc.f fVODGND170

----------------------------------------------------. MSM6411 •LOGIC SYMBOLPIN CONFIGURATION(Top View)16 PIN PLASTIC DIP (RS)5VOVRESETCLOCK2P2PIN DESCRIPTIONDesignation Input/Output Pin No. Function ResetPOO 10 4 Bits I/O port.P01/SCK11 poi to P03 are used both I/OP02/S0Input/Output12 port and terminal of shift resisterP03/SI 13"1 "P10 14P1115P12Input/Output1P13 24 Bits I/O port "1 "P20/INT 3 3 Bits input port with latch. Latch is reset.P21 Input 4 P20 is used as both input port and ("0")P22 5 input terminal of INT (input offalling edge trigger).OSCo Input 7. Input terminal of system clock. Clock pulse InOscillation circuit consists ofOSCo and OSCI.OSC, Output 6 Oscillation circuit consists ofOSCo and OSCI.RESET Input ,.9 Input terminal of system resetVDD 16 Main power source and circuitInputGND8 GND potential.171

• MSM6411 .---------------------------------------------------FUNCTIONAL DESCRIPTIONROMROM is organized in 1024 words by 8 bits. Itis used to stored developed applicationprograms (instructions). It is addressed by theprogram counter (PC).PCThe PC consists of a 10-bit binary counterand is used to address ROM.Stack and Stack PointerAn interrupt or CAL instruction causes. thecontents of the PC to be saved in the stack. ThePC is restored from the stack by RT instruction.All RAM locations (up to 8 levels) areavailable as the stack. Note that four words ofRAM are used for each level.The stack pOinter is a S-bit up-down counterthat points to the address of the next stack to beused. It allows the RAM locations to be used as apush-down stack.RAMRAM consists of up to 32 words 4 bits wide. Itis addressed by the H- and L-registers or by thecontents of the second byte of an instruction.L-REGISTERA 4-bit register which specifies RAMlocations A3-AO.H-REGISTERA 1-bit register which specifies RAM locationA4.ALUA 4-bit logic circuit that provides arithmeticand logical operations.ACCConsisting of a 4-bit register, theaccumulator holds the result of operations or thedata present on ports.CFLAGThe flag that holds a carry generated from theresult of operations.INPUT/OUTPUT Ports (2 x 4 bit)Organized into 4 bits, 2 ports are provided foreffecting and controlling data transfer to andfrom an external source. The ports are selectedby codes included in instructions.Input Ports (1 x 4 bit)Contained port 2 (P2), which is an input portwith latching function. P20 is set at falling edgeof the input signal P21 and P22 are set at "0"level inputs. Also, P20 is used as an interruptrequest flag. When P20 is set and an interruptoperation occurs, it is automatically reset.TIMING CONTROL (TC)A 0 level on the RESET pin for longer than 2machine cycles initializes the internal circuitry.Clock pulses are supplied to the XT pin froman external source. Also, by mask-option, itorganizes a circuit of oscillation with P20 andproduces clock pulses (by connecting externallyto crystal, ceramic or CR).172

--------------------------------------------------. MSM6411 •INSTRUCTION LISTMnemonic \ Description Code Byte CycleLAI n A-n 90-9F 1 1LLI n L-n 80-8F 1 1LHLI nn HL-nn 15nn 2 2LAL A-L 21 1 1LLA L-A 20 1 10.~LAM A-M 38 1 1£rn='0.. LMA M-A 2F 1 1"tica LAMD mm A-Md 10mm 2 2.3LMAD mm Md-A 11mm 2 2LMSR M(w)-SR 3E5A 2 2LSRM SR--M(w) 3E52 2 2PUSH ST-G,A, H, L, SP-SP-1 1C 1 3POP C,A,H,L-ST, SP-SP+1 10 1 3....=' IPD P A-Pp 3DpD 2 2.... 0.=' ....c.=,.50 OPD p Pp-A 3DpC 2 2ADS A-A+M, SKIP IF Cy = "1 " 02 1 1ADC C,A-C+A+M 03 1 1AIS n A -A+n, SKIP IFCy= "1" 3E4n 2 2DAS A-A+10 OA 1 1AND A-AAM 00 1 10~ EOR A-A¥M 04 1 1E.s::='= CMA A-A OB 1 1

eMSM6411 e.----------------------------------------------------INSTRUCTION LIST (CONT.), ......Mnemonic Oescription Code Byte CycleINMO mm Md - Md+1, SKIP IF Md = "0" 12mm 2 2"'cCQ)Q)E OCl l-l-1, SKIP IF l= "F" 35. 1 1EQ)Q) .......... uUQ)':0OCH H-H-1 36 1 1OCM M -M-1, SKIP IF M = "F" 37 1 1CTAB n2 SKIPIF [A bit n2J = "1 " 54-57 1 1TMB n2 SKIP IF [M bit n2) = "1 " 58-5B 1 10 RMB n2 [M bit n2) - "0"68-6B 1 1~~ 5MB n2 [M bit n2) - "1 " 78-7B 1 1Co0...TPBO p, n2 SKIP IF [Pp bit n2) = "1"iii30 pO-3 2 2,cUCRPBO p, n2 [Pp bit n2) - "0" 30 p4-7 2 2SPBO p, n2 [Pp bit n2) -"1 " 30 p8-B 2 2JCP a6 PC-a6 CO-FF 1 1JP a10 PC -a1040 - 4300 FF2 2~ ST - PC+2, PC -a1 0, AO A3co CAL a10SP-SP-1 OO-FF 2 4RT PC - ST, SP - SP+1 1E 1 4MEl MEIF-"1" 3E60 2 2MOl MEIF-"O" 3E61 2 2EICT EICTF-"1" 30CB 2 2EIEX EIEXF-"1" 30C8 2 2OICT EICTF-"O" 30C7 2 2a.;:OIEX EIEXF-"O" 30C4 2 2lii'ETlCT SKIP IF EICTF = "1 " 30C3 2 2TIEX SKIP IF EIEXF = "1 " 30CO 2 2TQEX SKIP IF IRQEX = "1 " 3020 2 2TQSR SKIP IF IRQSR = "1 " 3003 2 2RQEX IRQEX-"O" 3024 2 2RQSR IRQSR-"O" 3b07 2 2......8ESR SRF-"1" 30BA 2 2~.~.- CJl'cQ)OSR SRF-"O" 30B6 2 2CI) .....TSR SKIP IF SRF = "1 " 30B2 2 21740..... STOP STOP CLOCK 30B9 2 2~ (Lc08 NOP NO OPERATION 001 1

----------------------------------------------------1. MSM6411 •ABSOLUTE MAXIMUM RATINGParameter Symbol Conditions Limits UnitSupply Voltage VOO -0.3 -7 VInput Voltage VI Ta = 25°C -0.3 -VOO VOutput Voltage Vo -0.3- VOO VPower DissipationPoTa= 25°Cper one package200 max. mWTa= 25°0per one output 50 max. mWStorage Temperature Tstg :-55 - +150 °COPERATING CONDITIONSParameter Symbol Condition Limits UnitSupply VoltageVOOf(OSC) ~ 1 MHz 3-6 Vf(OSC) ~ 4.2MHz 4.5 -5.5 VData-Hold Voltage VOOH f(OSC) =OHz 2-6 VOperating Temperature TOp - -40-+85 °cMOSLoad 15Fan Out N -TTL Load 1175

eMSM6411 e----------------------------------------------------DC CHARACTERISTICS(Voo = 5V±1 0%, Ta = -40 - +85°C)Parameter Symbol Condition Min. Typ Max. Unit"H" Input Voltage *1, *2 VIH 2.4 ...., VOO V"H" Input Voltage *3, *4 VIH 3.6 - VOO V"L" Input Voltage Vll -0.3 - 0.8 V"H" Output Voltage"1, *5 VOH 10=-·15/LA 4.2 - - V"l" Output Voltage *1 VOL 10= 1.6mA - - 0.4 V"l" Output Voltage *5 VOL 10 = 15/LA - - 0.4 VInput Current *3 II~ VI=VOO/OV - -III~ -15 /LAInput Current *2, *4 I~IIIVI=VOO/OV - -Ao /LA"H" Output Current *1 10H VO=2.4V -0.1 - - rnA"H" Output Current *1 10H VO=0.4V - - -1.2 rnAInput Capacitance CI - 5 -f = 1 MHz, Ta = 25°C~Output Capacitance Co - 7pFPower Consumption(STOP)IOOSVoo = 2V,no loadTa= 25°C- 0.2 5 /LANo load - 1 100 /LAPower Consumption 100Crystal oscillation,No load, 4.2MHz- 6 12 rnA*1 Applied to PO and P1 .*2 Applied to P2.*3 Applied to OSCo*4 Applied to RESET*5 Applied to 0SC1176

--------------------------------------------------. MSM6411 •AC CHARACTERISTICS(VDD = 5V±1 0%, Ta = -40 - +85°C)Parameter Symbol Condition Min. Typ Max. UnitClock (OSCo) Pulse Width t

e MSM641.1 e-------------'-------------TIMING CHARTOSCOPO,P1,P2PO,P1tORP02/S0~-------------tSR--~----------~P01/SCKP03/SIP02/S0P-Jr-lUtsw tswINPUliOATA·tss'tsH--- tspXP2OSCOP01 SCK inhibit periodduring LMSR IN~T.178

----------------------___ 1. MSM6411.TYP. Maximum Oscillator Frequencyf(OSC)vs Supply Voltage(VDD)10987'N'::I: 6~ 50(/) 4g3210L1/IVvTa= 25°CCL= 15pF1 2 3 4 5 6 7 8 9 10VDD(V)TYP. Current VB Voltage for High State Output(lOH) (VOH)-1.0-0.9-0.8-0.7< -0.6r---..s::I: -0.59 ---0.4I""--0.3 4Vi"'""~-0.2-0.1 r- ~0" VDD =6V~5V '\..... 1'\1\" ~ r\ 1\'\" , ,2 3 4 5 6 7 8 9 10VOH (V)TYP. Maximum Oscillator Frequencyf(OSC)vs Temperature(Ta)CL= 15pF10987'N'::I: 6~ 50(/) 4g32'~b...~ ~I"'--. .....VDD=5VTYP:Current VB Voltage for Low State Output(lOL) (VoL>2018161412< 10..s-I986426V JI VfJII1/Ii"'"I-- 3VI--"" f- VDD=5Vj..- 4Vo -40 o 40 80 120-20 20 60 100Ta(OC)02 3 4 5 6 7 8 9 10VOL (V)179

• MSM6411 •• -------------------------------------------------TYP. Supply Current vs Supply Voltage(JDD)(VDD)10m1m100J.L10J.L~,,-vV~~/~ V...../ V/" .........V//I V V VTa=25°eNo Loadt(ose) = 4MHzI.. 2MHzI.. 1 MHzI_JJ500kHzV OHz100no 2 3 4 5 6 7 8 9 10VDD(V)180

OKI semiconductorMSM6422CMOS 4-BIT SINGLE CHIP MICROCONTROLLERGENERAL DESCRIPTIONThe OKI MSM6422 is a low power, high performance single-chip device implemented incomplementary metal oxide semiconductor technology.Integrated onto a single chip are 16K bits of mask program ROM; 256 bits of data RAM; 18Input/Output lines and oscillator. Program memory is byte wide and data-paths are organized in 4 bitnibbles. RAM and I/O lines are bit addressable. 63 instructions include Binary, BCD operations; Bitset, Reset, Test; Subroutine call and return.FEATURES• Low power consumption - 30 mW Typical• 2048 x 8 Internal ROM• 64 x 4 Internal RAM• 18 I/O Lines include 8 Bit Data Bus• Self-contained Oscillator• 631nstructions• 2 Interrupt Levels• 16 Stack Levels• -40 to +85°C Operating Temperature• 4.5 to 5.5V Operating VDD at 4.2 MHz3 to 6V Operating VDD at 1 MHz• TTL Compatible• 952ns Cycle Time @ 4.2MHz(VDD 5V ±1 0%)FUNCTIONAL BLOCK DIAGRAMROM2048x8wWr1 0t3210 3210 3210 3210 0/I"NTtGVNODOTiming&Controli I I00 RSSEC C S1 0 ET181

• MSM6422 •• --------------------------------------~-----------LOGIC SYMBOL (Top View)24 PIN PLASTIC DIP (RS)P51P50P4324 PIN FLAT PACKAGEoP42P41P40P33P32P31OSCoGNDP30RESETPIN DESCRIPTIONTerminal symbolInput/OutputFunctionResetPOOP01P02P03P10P11P12P13P30P31P32P33P40P41P42P43P50P51P20/lNT1/01/0I/OI/O1/0Input4-bit 1/0 ports(pseudo bidirectional "1 "configuration)4-bit 1/0 ports(pseudo bidirectional "1"configuration)4-bit 1/0 ports(pseudo bidirectional "1 "configuration)4-bit 1/0 ports(pseudo bidirectional "0"configuration)2-bit 1/0 ports(pseudo bidirectional "0"configuration)1-bit input port with a latch.Combined use with anThe latch isinterrupt input(falling edge reset to "0".trigger input)OSCoInputSystem clock (SYSCLK)input terminal. This providesan oscillation circle withOSC 1 terminal.-OSC,RESETVDDGNDOutputInputInputSystem clock outputterminal. This provides an-oscillation circle withOSCo terminal.RESET input terminal. -Power Supply terminals. -182

~------------------------------~----------------.MSM6422.FUNCTIONAL DESCRIPTIONProgram ROMOrganized into as many as 2,048 words by 8bits, ROM is used to store developed applicationprograms (instructions). It is addressed by theprogram counter (PC).Data RAMRAM consists of up to 64 words 4 bits wide. Itis addressed by the H- and L-registers or by thecontents of the second byte of an instruction.Input/Output Ports18 input/output port lines are provided foreffecting and controlling data transfer to andfrom an external source. The ports are selectedby codes included in instructions.P20/INT PIN (1 line)A low on this interrupt input pin sets theinterrupt request flag. The flag is automaticallyreset when an external interrupt occurs.The line can be used as an input port wheninterrupt is not used.12-BIT TIME BASE COUNTER (TBC)The. time base counter consists of a 1 2-bitbinary counter. An interrupt request is generatedeach time an overflow occurs from the division ofOSCo input signals by 212.PROGRAM COUNTER (PC)The program counter (PC) consists of a11-bit binary up counter. It is used to addressROM.STACK AND STACK POINTER (SP)An interrupt or subroutine call (CAL) causesthe contents of the program counter to be savedin the stack. The program counter is restoredfrom the stack by the RT instruction.All RAM locations (up to 16 leve.ls) areavailable as the stack. Note that four words ofRAM are used for each level.The stack pointer is a 4-bit up-down counterthat points to the address of the next stack to beused. It allows the RAM locations to be used as apush-down stack.L-REGISTERA 4-bit register which specifies RAM locationsA3-AO.H-REGISTERA 4-bit register whose two low-order bitsspecify RAM locations A5-A4.ALUThe 4-bit logic circuit that provides arithmeticand logical operations.ACCUMULATOR (Ace)Consisting of a 4-bit register, the accumulatorholds the result of operations or the datapresent on ports.C-FLAGThe flag that holds a carry generated from theresult of operations.TIMING CONTROL (TC)A 0 level on the RESET pin for longer than apredetermined period initializes the internalcircuitry and ports.Clock pulses are supplied to the OSCopinfrom an external source. A crystal or ceramicoscillator may be connected to OSCo and OSC 1to form an oscillator circuit to produce clockpulses.ABSOLUTE MAXIMUM RATINGParameterSupply VoltageInput VoltageOutput VoltagePower OissipationSymbolVOOVIVaPoConditions Limits Unit-0.3 -7 VTa=25°C -0.3 -VOO VTa = 25°Cper one package-0.3 -VOO V200 max. mWTa = 25°Cper one output 50 max. mWStorage'Temperature Tstg - -55 - +150 °C183

• MSM6422··----------------------~------~--------------------OPERATING CONDITIONSParameter Symbol ConditionHOSC) ~ 1 MHzSupply VoltageVOOHOSC) ~ 4.2MHzMemory-Hold Voltage VOOH -Operating Temperature TOp -MOS LoadFan OutNTTL LoadLimitsUnit3-6 V4.5 -5.5 V2-6 V-40 - +85 °C15 .-1 -DC CHARACTERISTICS(Voo = 5V± 10%, Ta = -40 - +85°C)Parameter Symbol Condition"H" Input Voltage *1, *2 VIH -"H" Input Voltage *3, *4 VIH -"L" Input Voltage VIL -"H" Output Voltage *1, *5--_.VOH 10=-15/l-A"L" Output Voltage *1 VOL 10 = 1.6mA"L" Output Voltage *5 VOL 10 = 15/l-AInput Current *3 IIH/IlLVI =VOO/OVMin. Typ. Max. Unit2.4 - VOO V4.2 - VOO V-0.3 - 0.8 V4.2 - - V- - 0.4 V- - 0.4 V- - 1~-15 /l-AInput Current *2, *4II~IlLVI =VOO/OV- -,%0 /l-A"H" Output Current *1 10H Vo =2.4V"H" Output Current * t 10H Vo =O.4VInput CapacityCIf = 1 MHz, Ta = 25°COutput CapacityCo-0.1 - - mA- - -1.2 mA- 5 -- 7 -pFCurrent Consumption(STOP)IOOSVOO = 2V, no loadTa = 25°CNo load- 0.2 5 /l-A- 1 100 /l-ACurrent Consumption 100Crystal oscillation,No load, 4.194304MHz- 6 12 mA*1 Applied to PO, P1, P3, P4, and P5*2 Applied to P2*3 Applied to OSCo*4 Applied to RESET*5 Applied to OSC 1184

--------------------------e MSM6422 eAC CHARACTERISTICS(Voo = 5V±1 0%, Ta = -40 - +85°C)Parameter Symbol ConditionClock (OSCo) Pulse WidthCycle TimeInput Data Setup TimeInput Data Hold TimeInput Data/Input ClockPulse Widthtq,wtCYtostOHtow-----1Min. Typ. Max. Unit119 - - ns952 - - ns120 - - ns120 - - ns120 - - nsData Delay TimetORCL=15pF- - tCY +300 ns1 MCtCYPO,P"P3P",P5P2o/INTw..185

e MSM6422e----------------------------------------------------INSTRUCTION SET"0«I,Mnemonic Hex op code Byte Cycle DescriptionLAI n 90-9F 1 1 Acc-nLLI n 80-8F 1 1 L-nLAL 21 1 1 Acc-LLLA 20 1 1 L-AccLAH 22 1 1 Acc-HLHA 2E 1 1 H-AccLAM 38 1 1 Acc-M0 LMA 2F 1 1 M-Acc....JX 28 1 1 Acc-MLMI nn 14·nn 2 2 M(W)-nnLHLI nn 15·nn 2 2 HL-nnLAMO mm 10·mm 2 2 Acc -MdLMAO mm 11 ·mm 2 2 Md -AccIPO P 30·pO 2 2 Acc -PpOPO P 30·pC 2 2 Pp-AccMEl 3E·60 2 2 MEIF-"1"MOl 3E·61 2 2 MEIF-"O"EIEX 30·C8 2 2 EIEXF-"1"EITB 30·C9 2 2 EITBF -"1"OIEX 30·C4 2 2 EIEXF-"O"e OITB 30·C5 2 2 EITBF-"O"C0 TIEX 30·CO 2 2 SKIP IF EIEXF="1"()TITB 30·C1 2 2 SKIP IF EITBF="1"TOEX 30·20 2 2 SKIP IF IROEX="1 "TOTB 30·00 2 2 SKIP IF IROTB="1"ROEX 30·24 2 2 IROEX

--------------------------. MSM6422 •INSTRUCTION SET (CONT.)Mnemonic. Hexopcode Byte Cycle DescriptionTAB n2 54-57 1 1 SKIP IF (Acc-Bit n2) = "1 "TMB n2 58-5B 1 1 SKIP IF (M-Bit n2) = "1 "RMB n2 68-6B 1 1 (M-Bit n2) - "0"Cl5MB n2 78-7B 1 1 (M-Bit n2) - "1 ".5=cTPBDp n2 3D·pO-3 2 2 SKIP IF (Pp-Bit n2) = "1 "t::as.s::ill -:a;RPBDp n2 3D·p4-7 2 2(Pp-Bit n2) - "0"SPBDp n2 3D·p8-B 2 2 (Pp-Bit n2) - "1 "TC 09 1 1 SKIP IF C = ''1 "RC 08 1 1 C-"O"SC 07 1 1 C-"1"ADS 02 1 1Acc-Acc+M,SKIP IF Cy="1"ADC 03 1 1 C, Acc - C+Acc+MAIS n 3E·4n 2 2Acc-Acc+n,SKIP IF Cy="1 "DAS OA 1 1 Acc -Acc+100 AND OD 1 1 Acc-AccAME.s:::!::

• MSM6422 •• ----------------------------------------------------TYP. Current (lOH) vs Voltage (VOH)for High state OutputTYP. Current (lOL) vs Voltage (Vodfor Low state OutputD-1.0-0.9-0.8-I'-.......,0.7~-0.6'"i: -0.5.9-0.4-4V-0.3'\ \\-0.2-0.1~ VOO=6V=- "\,5V= N~ \ \o'" \ \ \o 1 2 3 4 5 6 7 8 9 10VOH(V)TYP. Maximum Oscillator Frequencyf(OSC) vs Supply Voltage (Vo)N:I:60CI).P10987654321o/(Ta = 25°C, CL = 15pF)///o 1 2 3 4 5 6 7 8 9 10VOO (V)20181614

OKI semiconductorMSM6431CMOS 4-BIT SINGLE CHIP MICROCONTROLLERWITH BUILT-IN AID CONVERTERGENERAL DESCRIPTIONOKI MSM6431 is low-power, high-performance single-chip microcontroller implemented incomplementary metal oxide semiconductor technology.Integrated onto a single chip are 1 K byte of mask program ROM, 48 x 4 bits of data RAM, 10 inputloutputlines, oscillator and 8 bit A/Dconverter. RAM and 1/0 lines are bit addressable.FEATURES• Low power consumption -30 mW Typical• 1024 x 8 Internal ROM• 48 x 4 Internal RAM• 10 110 lines include 8 bit Data Bus• Self-contained Oscillator• 53 Instructions• 1 interrupt level• -40 to +85°C Operating Temperature• 4.5 to 5.5V Operating VDD at 4.2 MHz• 952 ns Cycle Time 4.2 MHz(VDD 5V ± 10%)• Internal 8 bit AID converter• Package: 24 pin DIP/24 pin FLATFUNCTIONAL BLOCK DIAGRAMRAM16x3x4 bitROM1024x8 bitT·eAGNDINTeA AI IN N3 2A A VI I RN N1 0i iG VN DD D0 0S SC C1 0AESET189

• MSM6431 • -----------'-------------------PIN CONFIGURATIONMSM6431-XXRS24 Lead Plastic DIPMSM6431-XXG.S24 Lead Plastic FlatPIN DESCRIPTIONDesignation Input/Output FunctionPOO4 bit Input/Output portP01(Pseudo-bidirectional port)Input/OutputP02P03P104 bit Input/Output portP11(Pseudo-bidirectional port)Input/OutputP12P13P60Input/Output2 bit Input/Output portP61(Pseudo-bidirectional port)P62 Output 1 bit Output portAINOAIN1 Input Analogue Input PinAIN2AIN3C Output Pin to external capacitor for AID conversionVR Input Analogue Reference Voltage InputAGND Input Analogue Reference GND InputINT Input Interrupt InputOSCoInputInput terminal of system clock.Oscillation circuit consists of OSCo and OSC ,OSC, Output Oscillation circuit consists of OSCo and OSC,RESET Input RESET InputVDD,GND Input Power SupplyReset"1""1 ""0""0"AINO--------190

-------------------------. MSM6431 •FUNCTIONAL DESCRIPTIONROMOrganized into 1024 words by 8 bits, ROM isused to store developed application programs(instructions). It is addressed by the programcounter (PC).Program Counter (PC)The program counter consists of a 10-bitbinary counter. It is used to address ROM.Stack and Stack PointerAn interrupt or CAL instruction causes thecontents of the program counter to be saved inthe stack. The program counter is restored fromthe stack by RT instruction.All RAM locations (up to 8 levels) are availableas the stack. Note that four words of RAM areused for each level.The stack pointer is a 5-bit up-down counterthat points to the address of the next stack to beused. It allows the RAM locations to be used as apush-down stack.RAMRAM consists of up to 48 words 4-bit wide. Itis addressed by H- and L-registers or by the contentsof the second byte of an instruction.L-RegisterA 4-bit register which specifies the columnaddress of RAM.H-RegisterA 2-bit register which specifies the row addressof RAM.ALUA 4-bit logic circuit which provides arithmeticnd logical operations.ACCConsisting of a 4-bit register, the accumulatorholds the result of operations or the data presenton ports.C-FlagThe flag which holds a carry generated fromthe result of operations.Input/Output Ports (11)11 input/output ports are provided for effectingand controlling data transfer to and from anexternal source. The ports are selected bycodes included in instructions.Analogue Input (4)4 analog input terminals AIN3-0 are provided.When not converting analog to digital, these areused as input ports.INT TerminalThe INT terminal is the input pin for interrupting.A interrupt request flag is set at the fallingedge of INT. With an interrupt occurring, this flagis reset automatically.Timing Control (T.C)A "0" level on RESET pin initializes the internalcircuitry.191

eMSM6431 e----------~-------------------------------------INSTRUCTION LISTMnemonic Hex op code Byte Cycle DescriptionlAI n 90-9F 1 1 Ace

--------------------------. MSM6431 •INSTRUCTION LISTMnemonic Hex op code Byte Cycle DescriptionTAB n2 54 -57 1 1 SKIP IF (Acc - Bit n2) = "1"TMB n2 58-5B 1 1 SKIP IF (M - Bit n2) = "2"RMB n2 68-6B 1 1 (M - Bit n2)

eMSM6431 e--------------~~-------------------------------ABSOLUTE MAXIMUM RATINGParameter Symbol Conditions Limits UnitSupply Voltage VDD -0.3 - 7 VInput Voltage VI -0.3 - VDD VOutput Voltage Vo iTa =:;!5°C -0.3- VDD VAnalogue Reference Voltage VR -0.3 - VDD VAnalogue Input Voltage VAl -0.3 - VR VPower DissipationPDTa = 25°Cper one packageTa= 25°Cper one output200 max. mW50 max. mWStorage Temperature Tstg -55 - +150 °cOPERATING CONDITIONSParameter Symbol Condition Limits UnitSupply VoitageVDDf(osc) ~ 1 MHz 3-6 Vf(osc) ~ 4.2 MHz 4.5 - 5.5 VData-Hold Voltage VDDH f(osc) = 0 Hi 2-6 VAnalogue Reference Voltage VR f(osc) = 4 - 4.2 MHz 2.6 - 3.5 VOperating Temperature Top -40 - +85 °cMOS Load 15 -Fan OutNTTL Load 1 -, 194

-----------'"---------------. MSM6431 •DC CHARACTERISTICS(Voo = 5V ±10%, Ta = -40 -+85°C)ParameterSymbolConditionMin Typ MaxUnit"H" Input Voltage *1, *2VIH-3.6 - VOOV"H" Input Voltage *3, *4"L" Input Voltage *1,*2, *3VIHVIL--4.7 - VOO-0.3 - 0.8VV"L" Input Voltage *4VIL--0.3 - 0.5V"H" Output Voltage * 1, *6VOH10 =-15j.1A4.2 - -V"H" Output Voltage *5VOHlo=-2mA2 - -V"L" Output Voltage *1VOL10 = 1.6 mA- - 0.4V"L" Output Voltage *6VOL10 = 15j.1A- - 0.4VInput Current *2IIH/IILV,=VOO/OV- - 1/-150j.lAInput Current *3IIH/IILVI = VOO/O V- - 15/-15j.lAInput Current*4"H" Output Current*1IIH/IILIOHV, = VOO/O VV = 2.4 V- - 1/-1-0.1 - -p.AmA"H" Output Current * 1IOHVo = 0.4 V- - -1.2JJ.AAnalogue Reference InputVoltageVRfosc = 4 -4.2 MHz2.6 - 3.5VAnalogue Input VoltageVAINfosc = 4 -4.2 MHz0 - VRVResolutionnfosc = 4 -4.2 MHz- - 8bitLinearity Oeviation Ratio *7ELfosc = 4 -4.2 MHz- - 1/-3LSBConversion Ratiotcfosc = 4 -4.2 MHz- - 4msInput CapacitanceOutput CapacitanceC,Cofosc = 1 MHzTa = 25°C- 5 -- 7 -pFPower ConsumptionStopIOOSVOO = 2 V, no load,Ta = 25°Cno load- 0.2 5- 1 100p.Aj.lAPower Consumption100Crystal Oscillation,no loadfosc = 4.194304 MHz- 6 12mANOTE: *1 AppliedtoPo'P"p.*4 Applied to RESET*2 Applied to INT*5 Applied to P62*3 Applied to asc o*6 Applied to asc,195

eMSM6431 e---------------------------------------------------*7 AD Conversion CharacteristicFF....::lC.....::lo19 /'& ,~o~'V'~-------------------L------------L-VR~VR2Analog InputAC CHARACTER ISTICS(VDD = 5 V ±10%, Ta = -40 ~ +85°C)Parameter Symbol Condition Min Typ Max UnitClock (OSCo ) Pulse Width tW - 119 - - nsCycle Time tCY - 952 - - nsInput Data Setup Time tDS - 120 - - nsInput Data Hold Time tOH - 120 - - nsInput Data/lnput ClockPulse Widthtow - *1 - - nsData Delay Time tOR CL=15pF - - tCY+300 ns*1 tow = tcy + 120 (ns)196

------------------------------------------------eMSM6431 e1MCos Cotcf>Wtcf>WPO,P1,P6PO,P1,P6t~I~JI-tORfINT=M-H197

• MSM6431 .-------------~-----------TYP. Current (loHI vs Voltage (VOH,PO, P1, P61 for High State OutputTa = 2Soc-1.0-0.9-0.8-0.7-0.61"'-...-o.s 1'.... SV "--0.4-0.3-0.2-0. 1r- t"'-....Voo =6VI"--...'"......"~ 1\4V 1,\ \f" 1\r...... ~v 1\, \ \ ,\ \00 1 2 3 4 .S 6 7 8 9 10VOH (VIso40302010oTYP. Current (lOLl vs Voltage {VOL!for Low state OutputTa = 2SOCI. VV V~ 4VI V~IYj/V ~ 3V ,j...-- ,...../J......-" I- sv1 1 f--Voo =6V-2 3 4 S 6 7 8 9 10VOL (VI198

-------------------------. MSM6431 •TYP. Current (lOH) vs Voltage (VOH,P62) for High state OutputTa = 25°C-20:;(.sJ:9-18-16-14-12-10-8-6-4-2r-... ~oo=6V......I\.f""".r-.... 5V \~ r\r--... r-.... 4V i\ \~ , ~~ r(V\ \ \\ \ \ \00 1 2 3 4 5 6 7 8 9 10VOH (V)TYP. Maximum Oscillator Frequencyf (OSC) vs Supply Voltate (Vo)Ta = 25°C, CL = 15 pF .10987654I1//Vv321oI2 3 4 5 6 7 8 9 10VOO (V)199

• MSM6431 • ---------------~--------TYP. Maximum Oscillator Frequencyf (OSC) vs Temperature (T a)CL=15pF109876..... ~I"'"VOO=5"" r-....4321. 0 -40 -20 0 20 40 60 80100120140Ta (OC)TYP. Supply Current (100) vsSupply Voltage (VOO)Ta = 25° C. No Load10m5m1m500""" /f(OSC) = 4 MHzV""~iMH~./' I I....... "..1 1 MH~~~ i--' 500 kHz~I--"""~5o"..~1,.0 100 kHz1"500m.VV/'./ " OHi100 no 2 3. 4 5 6 7 8 9 10Voo (V)200

OKI~~~. ~. I~~semiconductor--------------------------------------------------- .. ~MSM6442CMOS 4·BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVERGENERAL DESCRIPTIONThe OKI MSM6442 is a low power, high performance single chip device implemented incomplementary metal oxide semiconductor technology with 46 segment outputs and 2 commons.Also integrated onto this chip are 16K bits mask program ROM, 512 bits of data RAM, 28Input/Output lines and oscillator. 71 instructions include binary, BCD, logical operations; bit set,reset, test; subroutine call and return.FEATURES• Low Power Consumption 30mW (typ)• 2048 x 8 Internal ROM• 128 x 4 Internal RAM• Two built-in counters1 2-bit time-base counter8-bit programable timer/event counter• 16 Input/Output Ports and 46 LCDOutput Port and 2 Common Output• Self-contained Oscillator• 71 Instructions• 4 Interrupt Levels• 1 6 Stack Levels• -40 to +85°C Operating Temperature• 4.5 to 5.5V Operating VDD at 4.2 MHz3.0 to 6.0V Operating VDD at 1 MHz• TTL CompatibleFUNCTIONAL BLOCK DIAGRAMRAM16X8X4ROM2048X8OSC,OSC.TEST 1TEST 2'----- RESETVLCO COM2 SEG46 SEG 1 XT Xl TEST 3 INT 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0VM COMl SEG16 BZ INTOUT CIN--VOO-- GNO201

e MSM6442 e--------------------------...,..--LOGIC SYMBOL,vovRESET INPUTRESET OUTPUTPIN CONFIGURATION (TOP VIEW)HHHiHlliHIlTEST [CLOCKrLeDeLOCK [INTERRUPT INPUTINTERRUPT OUTPUTBUZZER OUTPUTPORTO[iPORTl '[iPORT 3PORT 4SEGMENTPIN DESCRIPTIONTerminalpoo -P03P10 -P13P30 -P33P40 -P43SEG1 -SEG16SEG 1 7 -COM1.COM2INTINTOUTRESETRESET OUTBZOSCe·OSC,XTXTSEG46Input!Output. Input!OutputInput!OutputOutput'Output'InputOutputOutputOutputInput!OutputInput!OutputTEST 1TEST 2 -TEST3 -VDD Input .,VLCDInput-VMInputlOutputGNDInput'''0'' indicates the VLCD voltage level202FunctionWhenreset1/0 port1/0 port (P10 and count input CIN are in "1 ',1common)I/O port1/0 port "0"LCD output port (can be assigned to data "0"·output in 4 bit wide)LCD output portLCD common output terminal 1LCD common output terminal 2liD"·Input port of external interrupt -Interrupt output port "1"Reset input port -Res~t output terminal "1 "Buzzer pulse output port in 2048 KHz"a"·Crystal OSC or ceramic OSC connectionCrystal OSC or ceramic OSC connection -(SYstem clock)32.768 kHz crystal oscillator connection(use for LCD control) )TEST terminal 1 (open) (Connected to VDD)TESTterminal2 (open) .TEST terminal 3 (open)Power supply (5V) -Power supply for LCD -(VDD-VLCD)/2 supply voltage outputor supply voltage input"0"*Power supply (OV) --

--------------------------. MSM6442 •FUNCTIONAL DESCRIPTIONROMOrganized into 2048 words by 8 bits, ROMis used to store developed application programs(instructions). It is addressed by the programcounter (PC).PROGRAM COUNTER (PC)The program counter consists of a 11-bitbinary counter. It is used to address ROM.STACKAn interrupt or CAL instruction causes thecontents of the PC to be saved in the stack. Also,the PUSH instruction causes the contents ofaccumulator, carry-flag, He and L-register to besaved in it. These are allowed to be restored bythe RT instruction or POP instruction.RAMOrganized into 1 28 words of 4 bits, RAM isaddressed by the H- and L-register or the contentsof the second byte of an instruction.L-REGISTERA 4-bit register which specifies the rowaddress of RAM and the port-address in the portoperation instructions. It is also used as aworking register.H-REGISTERA 4-bit register which specifies the columnaddress of RAM and is used as a workingregister.ALUA 4-bit logic circuit which providesarithmetic and logical operations.ACCUMULATOR (ACL)Consisting of a 4-bit register, theaccumulator holds the result of operations or thedate present on ports.C-FLAGThe flag that holds a carry generated fromthe result of operations.INPUT/OUTPUT Ports (16 bits)16 input/output ports are provided foreffecting and controlling data transfer to andfrom an external source. The ports are selectedby codes included in the instructions.12-bit TIME-BASE COUNTERThe time base counter consists of a 12-bitbinary counter. It is used to devide the frequencyof the OSCo input by 2'2 and generate theinterrupt request at every over-flow signal.8-bit TIMER EVENT COUNTERThe timer event counter consists of a 8-bitcounter (8-bit) register, comparing andcontrolling circuits. It is used to count pulses ofan internal or external source. Coincidently, ifvalue between the counter and the registercauses interrupt request occur.LCD DRIVERThe LCD driver is used to effect LCD displayby transferring data in a program to the registerassigned as port 5 and 6. It is available to selectdriving in static or dynamic operation (1/2 dutycycle) and frame frequency (128 HZ/64 Hz) andto drive up to 92 segments at 112 duty. Also, 16outputs(SEG 1-SEG 16) of the segment terminalscan be used as normal data outputs.A standard LCD clock is produced by theoscillation dividing a crystal oscillator (32.768kHz) connected to XT and XT terminals. This isalso used as standard clock of displaying, clockinterrupting and watch dog timer. (This clock canbe also produced by dividing a frequency of4.194304 MHz. Note the selection of the framefrequency, when the crystal oscillator is usedwithout a frequency of 4.194304 MHz.)INTERRUPTAs shown below, 1 - 4 is available to interrupt;1. External interrupt at the falling edge of INTsignal input2. Clock interrupt at every second (32.768 kHzcrystal oscillator)3. Time base counter interrupt at the occuranceof an overflow of the timer base counter.4. Timer event counter interrupt coincidingbetween the signals of the 8-bit counter ahdregister ..Interrupts 1 and 2 are also used to release thepower down mode.WATCH DOG TIMER (WDT)A timer for detecting the overrunning of theprogram. This timer produces the overflow Signalby dividing the 64 Hz frequency by 4 generatedfrom the oscillation of a frequency of 32.768kHz. It can be also halted, when unused.TIMING CONTROL (T.C)A 0 level on the RESET pin for longer thanpredetermined period initializes the internalcircuitry and ports.Clock pulses are supplied to the OSCo pinfrom an external source. A crystal or ceramicoscillator may be connected to OSCo and OSC 1to form an oscillator circuit to produce clockpulses.203

· .MSM6442.'----------------------------------------~--------INSTRUCTION SETMnemonic Hexopcode Byte Cycle DescriptionLAI n 90-9F 1 1 Acc ..... nLLI n 80-8F 1 1 L ..... nLAL 21 1 1 Acc-LLLA 20 1 1 L ..... AccLAH 22 1 1 Acc-HLHA 2E 1 1 H ..... AccLAM 38 1 1 Acc ..... M'0LMA 2F 1 1 M-Acctil.3 X 28 1 1 Acc+--+MLMI nn 14·nn 2 2 M(W) ..... nneLHLI nn 15·nn 2 2 HL-nnLAMO mm 10·mm 2 2 Acc ..... MdLMAO mm 11 ·mm 2 2 Md ..... AccL.MCT 3E·59 2 2 M(W) ..... CTLCTM 3E·51 2 2 CT ..... M(W)IPO p 30·pO 2 2 Acc ..... PpOPO p 30·pC 2 2 Pp ..... AccMEl 3E·60 2 2 MEIF ....... 1"MOl 3E ·61 2 2 MEIF ....... O"EIEX 30·C8 2 2 EIEXF-"1"EICT 30·CB 2 2 EICTF-"1"OIEX 30·C4 2 2 EIEXF-"O"OICT 30·C7 2 2 EICTF-"O"C0 TIEX030·CO 2 2 SKIP IF EIEXF="1"TICT 30·C3 2 2 SKIP IF EICTF="1 "TQEX 30·20 2 2 SKIP IF IRQEX="1"TQCT 30·02 2 2 SKIP IF IRQCT ="1"RQEX 30·24 2 2 IRQEX-"O"RQCT 30·06 2 2 IRQCT ....... O"INL 31 1 1 L ..... L+ 1, SKIP IF L="O"INH 32 1 1 H - H+ 1, SKIP IF H="O"...... -I:: - INM 33 ' .1 1 M - M+ 1, SKIP IF M="O"1::(1)(l)EOCL 35 1 1 L ..... L-1, SKIP IF L="F"E(I)(I) ..."'00(1) OCH 36 1 1 H - H-1, SKIP IF H="F"='0OCM 37 1 1 M - M-1, SKIP IF M="M"INMO mm 12·mm 2 2 Md - Md+ 1, SKIP IFMd="O"204

--------------------------. MSM6442 •INSTRUCTION SET (CONT.)CIMnemonic Hexopcode Byte Cycle DescriptionTAB n2 54-57 1 1 SKIP IF (ACC-Bit n2) = "1 "TPB n2 50-53 1 1 SKIP IF (P-Bit n2) = "1 "RPB n2 60-63 1 1 (P-Bit n2) - "0"SPB n2 70-73 1 1 (P-Bit n2) - "1"TMB n2 58-5B 1 1 SKIP IF (M-Bit n2) = "1 ".!: RMB n2 68-6B 1 1 (M-Bit n2) - "0"=0c: 5MB n2 78 -7B 1 1 (M-Bit n2) - "1 "..c:.- '"TPBD p n2 3D·pO-3 2 2 SKIP IF (Pp-Bit n2) = "1 "[Xlu:;RPBDp n2 3D·p4-7 2 2 (Pp-Bit n2) - "0"SPBDp n2 3D·p8-B 2 2 (Pp-Bit n2) - "1"TC 09 1 1 SKIP IF C = "1"RC 08 1 1 C_HO"SC 07 1 1 C-"1"ADS 02 1 1 Acc - Acc+M, SKIP IFCy="1"ADC 03 1 1 C, Acc - C+Acc+MAIS n 3E·4n 2 2 Acc - Acc+n, SKIP IFCy="1"DAS OA 1 1 Acc -Acc+10AND OD 1 1 Acc-AccAME..c: OR 05 1 1 Acc-AccVM:!:EOR 04 1 1 Acc-AccVM

OKI semiconductorMSC6458OKI 4-BIT 1-CHIP MICROCONTROLLERGENERAL DESCRIPTIONThe MSC6458 is a high-speed, 4-bit 1-chip microcontroller with built-in FLT drivers/controllers developedto support relatively large control systems.FEATURES• ROM: 8000 x 8 bits• RAM: 512 x 4 bits• Ports: I/O 24 ports (8 having 10L = 20 rnA)Input 9 (2 also serving as interrupt inputs)• FLT drivers (Withstand 12 (IOH = 20mA)voltage 40V):12 (IOH = 6mA)• Interrupts: 7 lines (2 external, 5 internal)• Built-in counters: 12 bits, timebase counter16 bits, programmable counter8 bits, high-speedprogrammable timer/eventcounter• Serial I/O: Built-in 8-bit SIO register• Oscillation circuit: Crystal or ceramic oscillation• Number of instructions: 147• Cycle time: 930 ns ( 4.3MHz)• Operating ranges: 4.5 t05.5V ( 4.3MHz)Voltage: 3.0 to 6.0V (1 MHz)Temperature: -40 to +85°C• Power dissipation (typical)(display off): 9mA ( 5V, 4.3MHz)2mA ( 3V, 1 MHz)• Power down: STOP instruction• Package: 64-pin shrink DIP/64- pin FLATBLOCK DIAGRAMTOTlTIlSEG 0SEG 1. ,.SEG 11OSCo-osc,-TESTTee r-L-__ -RESET-VDD-GND210 3210 32103210321020_3210 3210L!'::':o ~L aN ~I'LSCKINT1 TMO LsoTCK SI206

-------------------------. MSC6458 •LOGIC SYMBOLPIN CONFIGURATION (TOP VIEW))('Ial64 PIN PLASTIC ~.:SHRINK DIPRESETTEST5VOVFLTPowerPORT' [PORT2(PORT7[."TUS6\l,.TlOSEG'"IlIlTl."":m .....I!iJ"DImE '~' 'lOOT!,.almPORTalPIN DESCRIPTIONTerminalPOOP01/SCKP02/S0P03/S1Input!OutputInputlOutputFunction1/0 port __1/0 port (also used as serial clock input SCK)1/0 port (also used as serial data output SO)1/0 port (a!so serial data input 51)Whenreset"1 "P10/CINP11/TMOP12/TCKP13Input!Output1/0 port (also used as count input CIN)1/0 port (also used as timer output TMO)1/0 port (also used timer clock input TCK)1/0 port"1 "P20/lNTOP22/TNTfP30 -P33InputInputlOutputInput Port with Latch (falling edge sensitive)also used as interrupt input INTOInput Port with Latch ('0' level sensitive)also used as interrupt input INn1/0 port-"1"P60 -P63Input!Output1/0 port"0"P40 -P43P50 -P53OutputlInput110 port (lOL =20mA MAX)"0"P70 -P72P80 -P83SEGO -SEG11T11/SEG12-T8/SEG15InputOutputOutputInput port with pull down registerPull down register of P70 - P72 can be removedby instructionFL T segment driver (dynamic)FLT segment driver (dynamic)/Timing outputliD""0"T7/0UT7-TOIOUTOOSCOOSC1RESETTESTVFLTVDDGNDOutputInputlOutputInputOutputInputInputFLT segment driver (static)lTiming outputCrystal connection terminal for system clockoscillationSystem reset inputTest pin (Open)Power supply forFLT drivingSystem Power Supply"0"-----207

• MSC6458 • --..:....-----'-----------------FUNCTIONAL DESCRIPTION1. ROMThe ROM, organized in 8 bits, has amaximum capacity of 8000 bytes.2. RAMThe RAM is organized in 4 bits per word,with a capacity of 512 words.It is separated into two banks each 256words long. Bank selection is accomplished iliainternal ports. The RAM location in the banks isaddressed by the Hand l registers or by thesecond byte of each instruction.3. Ports (24 I/O, 7 input)The 24 pseudo-bidirectional I/O ports effector control the exchange of data with externalsources. The ports are specified by the lregister or by codes contained in instructions.Ports 4 and 5 may draw 10l up to 20mA.The seven input ports have built-in pulldownresistors. Up to 84 keys can be scanned byassembling them in key matrices with the timingoutputs of the Fl T drivers (with 1 2' segments x,1 2 timings on display; also during automaticdisplay).4. Interrupt Input Pins (2 terminals)The INTO/P20 and INT1 /P22 pins areinterrupt input pins. External interrupt requestflags of INTO/P20 pin and INT1/P22 pin can beset by using interrupt input pins:INTO/P20 pin ... positive edge or negative edge~ut.INT1 /P22 pin ... "0" level input.These flags are automatically reset whenthe appropriate external interrupts occur. Thesepins are available for use as input ports when notused as interrupt input pins.5. FL T Drivers/Controllers (Automatic Display)The Fl T drivers have a withstand voltage of40V in the positive direction from the GND level.They comprise 12 ports that can draw 20mA as10H (Timing outputs) and 12 ports that can draw6mA as such (Segment outputs).A choice of four display modes is supportedas listed below. A display RAM area is allocatedas part of the RAM space. Data is automaticallydisplayed when transferred to the display RAM:(Two different display frequencies areselectable.) Static output data can be displayedby controlling the Fl T drivers by programming.Display modes (@4.194304 MHz)(1) 12 Segments x 12 Timings '1/12 duty (85.3/341 .3 Hz)(2) 16 Segments x 8 Timings1/8 duty (128/512 Hz)(3) 16 Segments x 4 Timings +40utp!!t·1/4 duty (256/1 024Hz)(4) 16 Segments +8 output'Program controlled'output: static outputs6. Stack (STACK) and Stack Pointer (SP)The PC is saved in the stack when aninterrupt occurs or a CAL instruction isexecuted. It is recovered by the execution of anRT instruction., One fourth of the RAM space (128 wordsmaximum, 32 levels) is available as a stack area.A 4-word RAM area is used for "one" level in thestack.The stack pOinter is an 8-bit up-downcounter (the MSB and 2 bits from lSB beingfixed at '1') indicating the next stack address touse. It enables the RAM space to be us~d as apushdown stack. Data can also be transferredbetween stack pointer and the H/l registers.7. InterruptsSeven interrupt lines are provided for eightsources and eight levels of interrupts as follows(two external inputs):(1) Display interrupt, Update to timing signals (positive edge)(2) External interrupt1Negative edge on the INTO/P20 pin(3) External interrupt2Positive edge on the INTO/P20 pin(4) External interrupt3'0' input on the INT1 /P22 pin(5) Timebase interrupt1 2-Bit timebase, counter overflow(6) Timer interrupt16-Bit timer and timer register matched signal(7) Counter interrupt8-Bit counter and counter register matchedsignal(8) Serial/O interrupt8-Bit shift register shift end signal8. 12-Blt Timebase CounterThe timebasecounter is made up of a 12-,bitbinary counter. It generates an interrupt requestevery time it overflows as a result of dividing theOSCO input 2'2.9. 16-Blt Programmable Timer/Event CounterComprising a 16-bit register, a 16-bit binarycounter, a comparator circiut, and a, controlcircuit, the programmable timer generates aninterrupt request when the register and countervalues are matched.10. 8-Blt High-Speed ProgrammableTimmer/Event Counter ,The high-speed programmable timer/eventcounter comprises an 8-bit register, an 8-bitbinary counter, a comparator circuit, and acontrol circuit. Starting and stopping the countercan be controlled by instructions. It generates aninterrupt request when the register and countervalues are matched.208

-------------------------. MSC6458 •11. 8-Bit Seriall/OSerial 110 consists of an 8-bit shift register,a 3-bit shift counter, and a control circuit. It isused for serial data input and output. Serial datainput and output takes place synchronized witha shift clock, which is selectable betweeninternal and external clocks. The shift counterautomatically terminates a data transfer oncounting eight shift clock pulses and generatesan interrupt request.12. Registers (Ace, H, L, F)The accumulator (Acc) is a 4-bit registerused to perform data transfers or calculationswith the RAM, other registers, ports and so on.The Hand L registers are each a 4-bitregister. They transfer data to and from Acc andSP (stack pointer) and address the RAM. The Lregister is also used to specify ports to use.The F register is made up of fourindependent flip-flops. It can be used as aprogram "flag" or general-purpose registerbecause each of these flip-flops permitsset/reset testing and transferring 4-bit paralleldata to and from Acc by instructions.13. Timing Control (TC)A '0' input on the RESET pin for a certainperiod initializes internal circuitry and ports.As the input side of clock pulses, the OSCOpin accepts clock pulses from an externalsource. Clock pulses may also be obtained byconfiguring an oscillation circuit with a crystaloscillator or ceramic resonator connected toOSCO and OSC1.209

• MSC6458 • -----------------------'-----Load Instructions, etc.Mnemonic Code Bytes Cycles DescriptionLAI n 90-9F 1 1 A

--------------------------. MSC6458 •Interrupt Control InstructionsMnemonic Code Bytes Cycles DescriptionMEl 3E·60 2 2 MEIF

• MSC6458 • -------------------------Increment/Decrement InstructionsMnemonic Code Bytes Cycles DescriptionINA 30 1 . 1 A +-A+1, Skip if A = "0"INl 31 1 1 l +- l+1, Skip if l = "0"INH 32 1 1 H +- H+1, Skip if H = "0".INM 33 1 1 M +- M+1, Skip if M = "0"DCA 34 1 1 A +-A-1, Skip if A = "F"DCl 35 1 1 l+-l-1,~kipifl= "F"DCH 36 1 1 H +- H-1, Skip if H = "F"DCM 37 1 1 M +- M-1, Skip if M = "F"INMD mm 12· mm 2 2 Md +-Md+ 1, Skip if Md = "0"DCMD mm 13· mm 2 2 Md +- Md-1, Skip if Md = "F"Bit Handling Instructions, etc.Mnemonic Code Bytes Cycles DescriptionTAB n2 S4-S7 '1 1 Skip if A (n2) = "1"RAB n2 64-67 1 1 A (n2) +- "0"SAB n2 74-77 1 1 A (n2) +-"1"TPB n2 SO-S3 1 1. Skip if P (n2) = "1"RPB n2 60-63 1 1 P (n2) +- "0"SPB n2 70-73 1 1 P (n2) +- "1"TMB n2 S8-SB 1 1 Skip if M (n2) = "1"RMB n2 68-6B 1 1 M (n2) +-"0"5MB n2 78-7B 1 1 M (n2) +- "1"TFB n2 SC-SF 1 1 Skip If F (n2) = "1"RFB n2 SC-6F 1 1 F (n2) +- "0"SFB n2 7C-7F 1 1 F (n2) +- "1"TPBD p,n2 3D· pO-3 2 2 Skip if Pp (n2) = "1"RPBD p,n2 3D· p4-7 2 2 Pp. (n2)".... "0"SPBD p,n2 3D· pB-B 2 2 Pp (n2) +- "1"TC 09 1 1 SkipifC = "1"RC 08 1 1 C+-tlO"SC 07 1 1 C+-"l"212

--------------------------. MSC6458 •Arithmetic InstructionsMnemonic Code Bytes Cycles DescriptionADCS 01 1 1 C, A

• MSC6458 • -------------------------Counter Control Instructions, etc.Mnemonic Code Bytes Cycles DescriptionLCTM 3E· 51 2 2 CTR

--------------------------. MSC6458 •Explanations of Instruction SymbolsAHLFMMdM(w)Md (w)M (2w)STSPPCPPpCTRCTCTFTMRTMSRSRF(X, Y)T (X, Y)nnnn2(n2)aaXmmCCy: Accumulator (4-bit): H register (4-bit): L register (4-bit): F register (4-bit): RAM word addressed by the Hand L registers: RAM word addressed by second byte of an instruction code: Two RAM words addressed by the Hand L register/H3-0 and L3-1 (a-bit): Two RAM words addressed by second byte of an instruction code (a-bit): Four RAM words addressed by the Hand L register/H3-0 and L3-2 (16-bit): Four RAM words (16-bit) allocated as a stack area: Stack pointer (a-bit): Program counter: Port specified by the L register (4-bit): Port specified by 4 high-order bits of second byte of an instruction code (4-bit): a-Bit counter/register: a-Bit programmable counter: Programmable counter start flag: 16-Bit timer/register: 16-Bit programmable timer: a-Bit shift register: Shift register start flag: ROM address data specified by a11-4 as X and a3-0 as Y (12-bit): ROM table data specified by a 11-4 as X and a3-0 as Y (a-bit): Immediate data (4-bit): Immediate data (a-bit): Two low-order bits of an instruction code: Bit specified by the two low-order bits of an instruction code: ROM address data: ROM address data (X-bit): RAM address data (a-bit): Carry flag: Flag indicating a carry in a calculation result215

OKI semiconductorMSC6458VSMSC6458 PIGGY BACKGENERAL DESCRIPTIONThe MSC6458VS is a device whose built-in ROM is replaced by external EPROM using thepiggyback method.FEATURES• Supply Voltage: 5V±5% • Operating Temperature: 0 - 70°C• Frequency: DC - 4.3MHzROM INSERTIONPlease refer to drawing below.C6458OKIJAPANPIN CONFIGURATIONPin Connection between MSC6458 VS and EPROMToAO -A13of MSC6458VSA ADDRESS'vi10-1 11MSC6458VS 'vi DATANote: When inserting a 2764,pin 26 is not used.VeeA13A12An10987654321AODO123456D7GND- - '--VppA12A7A6A5A4A3A2AlAD000102GND"1"'-'2s2 273 264 255 246 23727128228 219 2010 1911 1812 1713 1614 15,JPGMA13 -A8-A9-AllOEAl0CE07-06-05-g;Jl216

OlMS-6S SERIES

OKI semiconductorMSM6502/6512CMOS 4 BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVERGENERAL DESCRIPTIONThe OKI MSM6502/6512 is a low-power, high-performance 4 bit single-chip microcontroller implementedin complementary metal oxide semiconductor technology.Integrated within this one chip is a 108 (4 x 27) dot LCD Driver. Also integrated in this chip are16K bits of mask program ROM, 512 bits of data RAM, Input/Output lines, a programmabletimer/counter, and oscillator.The advantages of the MSM6502/6512 in comparison with the OLMS-40 Series include, amongother features, a lower drive voltage, multiplexed interrupts, a larger number of drivable liquid crystalelements, a buzzer output, and larger memories.FEATURES• ROM• RAM• NumberofInstructions• Clock Oscillation• Cycle Time• Timer Interrupt• I/O Ports• Input ports• LCD Drive• Buzzer• Interrupt2000 x 8 bit128 x 4 bit68Crystal 32.768 kHz91.5/LsDual (16 & 128 Hz)4 bit x 2 Port4 bit x 1 Port108 (4 x 27)picture elements2K/1 K/512 Hz/SoftThree types(external, two timertypes)FUNCTIONAL BLOCK DIAGRAM• Stack• Power down• Operating powersupply voltage• Consumptioncurrent(VDD=3V,OSC=32.768 kHz)• PackageNesting RAM stackpointer = 7 bitsHalt mode available2.4V - 3.6VMSM6502; 45/LA (Typical)30/LA (Halt mode)MSM6512; 30/LA (Typical)1 2/LA (Halt mode); 56 pin FLAT (Small type)00 R 4 32 1 TSSE '"'----" NCCS TEST T0' ETV Go No 0219

• MSM6502/6512 • ----------------------LOGIC SYMBOLPIN CONFIGURATION (TOP VIEW)CrystalresonatorconnectionJ PortO, (input/output ports)ResetInterruptTest pins l+3VOVTEST3TEST4VDDGND2526BZilZJ Port1(input/output ports)J LCDcommon outputLCDsegment outputJ BuzzeroutputP02P03P10P21P22P23BZilZ42 SEG13IfIPIN DESCRIPTIONDesignationPin No.FunctionGND 24VDD 21,49OSCo 22--OSC, 23CircuitGND potentialMain power sourceCrystal OSC input, internal clock inputCrystal OSC input, internal clock outputPO, P11 t04St08Pseudo-bidirectional ports for 4-bits parallel 110. To input data from these ports,it is necessary to write "1" beforehand.The port to be selected is specified by the L register. The register contents andthe corresponding specified ports are listed below.Content of L registerPort Specified0.8 PO1.9 P12.0AHP23.0BHP34.0CHP4S.ODHPS6.7.0EH.OFHNo designationP29t012Note: P3, P4, PS are internal ports.Input ports for 4-bit parallel input with no latching function.INT 16Input pin to request an interruptfrom the external circuit. Theinput flag is set bythe fali of the input signal.220

----------------------. MSM6502/6512 •Designation Pin No. FunctionRESET 15 The reset mode starts after "a" is input to the RESET pin for more than 2machine cycles.The reset signal has priority over all of other signals and performs the followingoperations automatically:(1 ) Resets all bits of the PC (Program counter) to "0".(2) Sets all bits of the parallel I/O ports (POO to P13) to "1 ".(3) Resets the internal resister (H, L, ACC, C, P3, P4, P5).(4) Resets the skip flag.(5) Resets all bits of the time base counter (TBC).(6) Resets the interrupt request flag (lRQF).(7) Resets the interrupt enable flag (ElF).(8) Resets the master interrupt enable flag (MEIF).(9) Sets all bits of the stack pointer (SP) to "1 ".(10) Initializes the segment and common outputs.(11) Sets all bits of the index register (lDR) to "1 ".Since the RESET pin is pulled up to VDD by an internal resister (approx. 800kil), itis possible to achieve power ON/reset by connecting it with anexternal capacitor.LCD Drive PinsA special AC waveform designed to comply with liquid crystal properties isSEGO-26 29t048 required for liquid crystal drive purpose. The MSM6502B is equipped with a50t056 1/4 duty 1 /3 bias liquid crystal drive circuit with four common output ports andCOM 1 -4 25 to 28 27 segments to enable displays of 108 picture elements. On/off selection ofpicture element displays involves writing "a" or "1" in the corresponding bits inthe RAM OOH to thru 1 AH display area, and subsequent automatic hardwarecontrolled display. The frame frequency is 64 Hz.BZ/BZ 13,14 BZ and BZ are used in the generation of alarms and other sounds. Theselectable frequencies include three hardware frequencies (TBC output) 51 2,1024, and 2048 Hz, and a software type based on P50 data. These frequenciesare selected at P3.When one of the.hardware frequencies is selected by P3, output of thatfrequency is continuous. But selection of the software type results in output ofP50 contents to generate a melody by program.INSTRUCTION LISTGrouping Mnemonic Code Byte Cycle FunctionLAI n Sn 1 1 Acc-nLLI n 7n 1 1 L-nLHLI nS 6A nS 2 2 HL-nSLXI nS 69 nS 2 2 X-nSLAM BO 1 1 Acc-MLoad LAL B1 1 1 Acc-LLAH B2 1 1 Acc-HLMA B4 1 1 M -AccLLA B5 1 1 L-AccLHA B6 1 1 H-AccLMAD m7 1B m7 2 2 M -Acc221

• MSM6502/6512 • ----------------------INSTRUCTION LIST (CO NT.)Grouping' Mnemonic Code Byte Cycle FunctionLAMD , m7 1A m7 2 2 Acc-MILMT 67 1 2 M -ROMLoadPUSH HL BC 1 2 STACK -HL, SP -SP-2PUSH CA BD 1 2 ~TACK -C, Acc, SP -SP-2POP HL BE 1 2 HL -STACK, SP -SP+2POP CA BF 1 2 C, Acc.-STACK, SP -SP+2XAM B8 1 1 Acc-~MExchange XAMD m7 1C m7 2 2 Acc~MXHS 3F 1 1 HL-~SPINA 10 1 1 Acc - Ar:;c + 1 , Skip if Acc= 0INL - 11 1 1 L-L+1,SkipifL=OINM 12 1 1 M-M+l,SkipifIncrementM=Oanddecrement INX 5C 1 1 X-X+1DCA 14 1 1 Acc -Acc-1,Skip ifAcc= FDCL 15 1 1 L-L-1 SkipifL=FDCM 16 1 1 M-M-l,Skip ifM=FDCX 5D 1 1 X-X-1DSC 60 1 1 C,Acc+-:-C+Acc+M < HL >, Adjust if C=ODAC 61 1 1 C,Acc-C+Acc+(M < HL > +6), Adjust ifC=OADS 62 1 1 Acc -Acc+M., Skip ifCy=lADCS 63 1 1 C,Acc -C+Acc+M < HL > ,Skip if C=lAIS n On 1 1 Acc-Acc+n, Skip if Cy=lCMA 65 1 1 Acc-AccEOR 66 1 1 Acc -Acc¥MOperation AND 4C 1 1 Acc -Acc/\M)OR 4D 1 1 Acc -AccVMCAM 6B 1 1 SkipifAcc=MCPAL 6C 1 1 Skip if Acc = LCAXL 6D 1 1 Skip if Acc = XLCAXH 6E 1 1 Skip if Acc = XHSC 1F 1 1 C-"l"RC 1EJ 1 1 C_uO"TC 4E 1 l' SkipifC="l"222

-----------------------. MSM6502/6512 •INSTRUCTION LIST (CONT.)Grouping Mnemonic Code Byte Cycle FunctionOperationRAL 18 1 1RAR 19 1 1,.-- Acc----.(*) -C -3-2-1---(*),.-- Acc ---,(*) - C - 3-2-1-0-(*)5MB n2 30-33 1 1 M bltn2 -"1"5MBO m7,n250- 53 2 2m7 m7M bitn2-"1"SPB n2 20-23 1 1 Pbitn2 -"1"RMB n2 34-37 1 1 M bit n2 -"0"BitOperationRMBO m7,n254- 57 2 2m7 m7M bitn2 -"0"RPB n2 24-27 1 1 Pbitn2-"0"TMB n2 38-3B 1 1 Skip il M bit n2 = "1"TMBOm7,n258- 5B 2 2 Skip iIM bitn2 ="1"m7 m7TPB n2 28-2B 1 1 Skip ilP bit n2 ="1"TAB n2 2C-2F 1 1 Skip il Acc bit n2 = "1"[ITIRB n2 49-4B 1 1 illROF bit n2="1" Skip & IROF bit n2 -"0"InterruptEI 5E 1 1 MEIF-"1"01 5F 1 1 MEIF-"O"J a11 9000-97CF 2 2 PClO-0-a11CAL a11 AOOO-A7CF 2 3 STACK-PC+2, SP-SP-3, PClO - o-a11Branch JCP a6 CO-FF 1 1 PC5-0-a6RT 3C 1 2 PC -STACK, SP-SP+3RTS 30 1 1 PC -STACK., SP-SP+3, then SkipInput!OutputCPUControlIP B3 1 1 Acc-POP B7 1 1 P-AccHALT 4F 1 1 HLF-"1"NOP 00 1 1 No Operaiion223

eMSM6502/6512 e ---------------------------------------------ELECTRICAL CHARACTERISTICABSOLUTE MAXIMUM RATINGParameterSymbolConditionsLimitsUnitPower Supply VoltageVDD-0.3-7 VInput Voltage V,Ta=25°C-0.3-VDDVOutput VoltageVo-0.3-VDDVPower DissipationPDTa=25°Cper package200 mVStorage Tern peratu reTstg--55 -+150 °COPERATING RANGEParameterSymbolConditionsLimitsUnitPower Supply Voltage VDD f(osc)=32.768 kHzOperating Temperature Top -2.4 -3.6 V-20-+70 °Co224

----------------------. MSM6502/6512 •D.C. CHARACTERISTICS(VDD = 3V, Ta = -20 -+70°C)Parameter Symbol"H" Input Voltage VIH"L" Input Voltage VIL"H" OutputVoltage(l )VOHConditions--IO=-1.0mAMIN. TYP. MAX. Unit2.6 - - V- - 0.4 V2.0 - - V"L" OutputVoltage(2)VOLlo=1.0mA-~1.0 VV3MSM6502MSM6512IO=-5/-LAIO=-2/-LA2.8 - 3.0 VLCO OriveOutput Voltage(3)V,V,MSM6502MSM6512MSM6502MSM6512IO=±2/-LAIO=±0.5/-LAIO=±2/-LAIO=±0.5/-LA1.8 - 2.2 V0.8 - 1.2 VVoMSM6502MSM6512IO=5/-LAIO=±2/-LA0.0 - 0.2 VOSCo Input CurrentIIH/IILVI =VOOIVI =OV- - 2/-2 /-LAInput Current(4)IIH/IILVI =VDDIVI =OV- - 1/-10 /-LAInput Current(5)IIH/IILVI =VOOIVI =OV- - 1000/-1 /-LAInput Current(6)IIH/IILVI =VOOIVI =OV- - 1/-40 /-LAPO,Pl"H" Output CurrentIOHVo=OV- - -50 /-LA100MSM6502MSM65121(osc) = 32.768 kHzat no load- 45 70- 30 55/-LACurrentConsumptionIOOHLTMSM6502MSM65121(osc) =32.768 kHzat HL T execution- 30 40- 12 25/-LAIOOSMSM6502MSM6512Statis- 15 25'- 5 15/-LAOscillation StartTimeTOSC-- - 10 SEC225

.MSM6502/6512·----------------------------------------~---(1) Applied to BZ, BZ(2) Applied to BZ, BZ, PO, P1(3) Applied to COMMON, SEGMENT------ V3------ V2------V1(4) Applied to RESET, INT(5) Applied to P2 (When input is unable)(6) Applied to P2 (When input is able)~- - - - VoSWITCHING CHARACTERISTIC(VDD =3V, Ta =-20 -+70°C)Parameter Symbol Conditions MIN.TYP. MAX. UnitClock (OSCo) Pulse Widthtq,W -15- - MSCycle TimetCY -(1 )- - MSPOP1P2Data Valid TimetDV-(2)- - MSPOP1P2Data Invalid TimetDiV --- (3) MS~? Data Delay Ti metDDSCL=50pF-- (4) MS(1) tCY = 3 x 1/t(osc)(2) tDV = 112 x 1/f(osc)(3) tDIV = 1 x 1 !f(osc) + 1 OMS(4) tDDS = 5/2 x 1/t(osc) + 15MS1MC tCYOSCotc/>wtc/>wPOP1P2Input modeINVALIDINVALIDtDIVtDVPOP1Output ModeOLD DATANEW DATAtDDS226

-----------------------. MSM6502/6512 •TYPICAL PERFORMANCE CURVES for MSM6502-5-4-3«.sJ:9 -2High-level Output Current (lOH)- Output Voltage (VOH)'-(BZ, BZterminal)f'\(Voo =3V, Ta= 25°C)-11\(COMMON, SEGMENT terminal)-.l~(PO, Pl terminal)o o 1 2 3 4 5 6 7 8 9 102520VOH(V)Middle-level Output Current (11, 12)- Output Voltage (V1, V2)(VOO= 3V, Ta= 25°C)«.s..J91098765432Low-level Output Current (loL>- Output Voltage (VoL>/IrIo o10m5m-V(PO, Pl terminal)I- (BZ,I Bi iermlnal)(VOO= 3V, Ta= 25°C)(COMMO,N SEGMENT terminal)2 3 4 5 6 7 8 9 10VOL (V)(Ta= 25°C, No load)«15105.5 0N.:-5-10-15-20Vl V2/ /II LI) ) (COMMON, SEGMENTterminal)II II-25o 1 2 3 4 5 6 7 8 9 10V" V.(V)5Cl.91mr::-Current Consumption (lDD)- Power Supply Voltage (VDO) ~5001'-1001'-501'-101'-51'-HOSC) = 32,768 KHzV VoJzV500n100no 1 2 3 4 5 6 7 8 9 10VDO(V)227

• MSM6502/6512 .---....:.-------,--------------TYPICAL PERFORMANCE CURVES for MSM6512-S-4< -3..sJ:.9 -2High-level Output Current (lOH)- Output Voltage (VOH)(Voo =3V. Ta= 2S0C)-(BZ. BZterminal)'\\-1\(COMMON. SEGMENT terminal>, I I ~ (PO. P1 terminal)o o 1 2 3 4 S 6 7 8 9 10VOH(V)

8 BIT SERIES (OKI ORIGINAL)

OKI semiconductorMSM62580CMOS 8-BIT SINGLE CHIP MICROCONTROLLER WITH 16K BIT E2PROMGENERAL DESCRIPTIONThe MSM62580 is a CMOS one-chip microcontrollar with on-board 16K bit E2PROM for applicationssuch as IC-cards, etc.The powerful instruction set consists of 95 instructions including special instructions for IC cards,executed by the 8-bit CPU in 800 ns at 5.0 MHz clock frequency.The MSM62580 has improved hardware and software for security. Consequently, this chip suitsapplication such as IC cards of low cost, high security and high reliability.APPLICATION EXAMPLES• IC Cards• Mechanical Controls• Automobile Controls• Industrial Controls• Compact Disc Players• AudiolVideo Equipment• Household Appliances• MusicallnstrumentsFEATURESHigh speed instruction cycleHigh number of instructions, and an efficient instruction set(For example)• Instructions forserial interface• Index addressing• 1 byte call addresing CZPSmall package sizeSIN, SOUT, DL Y• Instructions forauto incrementand auto crecrement• Simplified E2PROM write/erase operation by using control ROM.From D.C to 5 MHz clock frequency• 9600 baud-rate serial interface using "DL Y" instruction.INC, DECSPECIFICATIONS• Single chip, low power CMOS • Clock frequency• 8-Bit Microcontroller • Instrucion cycle• 3K Bytes program ROM • Number of instructions:• 512 Bytes control ROM • Operation current• 2K Bytes E2PROM • Ambient range• 128 Bytes data RAM • Number of pads• Supply voltage• Die sizeo - 5.0 MHz800ns @ 5 MHz954 mA typoo to 70°C5+5 V ± 10%5.0 x 4.5 mm231

• MSM62580 • -------------------------BLOCK DIAGRAMS-I/OVDDc:::J--E'PROM2kx8elKGND• E2PROM is not used as instruction area.ALUE2PROMROMRAMArithmetic Logic UnitElectrically Erasable-Programmable ROMRead Only MemoryRandam Access Memory (Data memory)PIN DESCRIPTIONDescription Input/Output FunctionS-1I0 Input/Output Serial data input/output port.Quasi bidirectional 110 port.Set "1" level after "Reset".VDD - Main power sourceGND - Circuit GND potentialRES Input "Reset" has priority over every other signal.RES input initialize the processor.Active "0" level.CLK Input External clock input232

-------------------------. MSM62580 •REGISTER DIAGRAM17 , ,01Accumulator17, ,01B·registerl>

• MSM62580 • -----------,-----------------ABSOLUTE MAXIMUM RATINGSParameterSymbolConditionsLimitsUnitSupply VoltageVDDTa = 25°C -0.5 to 7VInput VoltageVITa = 25°C -0.3 to VDD +0.5VOutput VoltageVoTa = 25°C -0.3 to VDD +0.5VStorage TemperatureTstgo to +70°COPERATING CONDITIONSParameterSymbolLimitsUnitSupply VoltageVDD4.5 to 5.5VOperating TemperatureTOpo to +70°CD.C. CHARACTERISTICS(VDD = 5V± 10%, Ta = 0 to +70°C)ParameterSymbolConditions Min Typ MaxUnitOperating CurrentIDDf = 5 MHz - 4 10mAClK-0.3 - 0.5low Input VoltageRESVil- -0.3 - 0.5VSIO-0.3 - 0.8ClK2.4 - VDDHigh Input VoltageRESVIH- 4 - VDDVSIO2.0 - VDDlow Output VoltageVOL10l MAX = 1 .6mA 0 - 0.4VHigh Output VoltageVOHIOH MAX = -100;;'A 2.4 - VDDVInput Current (ClK, RES)Input Current (SIO)IIH1/11l1IIH2/11l2VI=ONDD- - 20- - -1p.AmAInput CapacitanceOutput CapacitanceCICof=1MHzTa=25°C- 15 -- 20 -pFpFNotes: = ClK, RES has poll down resistance SIO has pull up resistance.,234

--------------------------------------------------eMSM62580eA.C. CHARACTERISTICS(VDD = SV± 10%, Ta = 0 to +70°C)Parameter Symbol Min TypClK Cycle Time TCY 200 -ClK Cycle low Width TCl 0.4*TCY -ClK Cycle High Width TCH O.4*TCY -ClK Cycle Rise Time TCR - -ClK Cycle Fall Time TCR - -RES Pulse Width TRW 8*TCY -SIO INPUT Rise Time TSR - -SIO INPUT Fall Time TSF - -Max Unit- ns0.6*TCY ns0.6*TCY nsS.Of-Is5.0 f-IS- f-Is5.0 f-Is5.0 f-IsNote:at output capacitance Co = 30pFTIMING CHARTSClK~-----------TCY-- ---------TCl---~TCR2.4V 2.4VTCH-~TCFO.SVSIOTSRTSFRES\ r----TRW------l.i /' ~-O.8V O.8V¥235

• MSM62580 • -----------,---------------­INSTRUCTION LISTMNEMONIC oprOPERATION BYTE CYCLEFLAGSC P H ZMOV A, opr B A

-----------------------. MSM62580·MNEMONIC opr OPERATION 8YTE CYCLEFLAGSC P H ZXCH A, opr 8 A .... 8 1 2 *0 A .... 0 1 2 *@D A .... (D) 1 2 *N A- (N) 2 2 *XCH 0, opr 8 0-8 1 2SP 0- SP 1 2XCH C, opr P C-P 1 1 * *ADD A, opr @D A +- A+(D) 1 1 * * *N A +- A+(N) 2 2 * * *#N A+- A+ #N 2 2 * * *ADC A, opr @D A+-A+(D)+C 1 1 * * *N A+-A+(N)+C 2 2 * * *#N A+-A+#N+C 2 2 * * *DAA Decimal adjust 1 1 * *CMP A, opr @D A +- (D) 1 1 * *N A +- (N) 2 2 * *#N A+- #N 2 2 *. *CMP @D, opr @8A (D) +- (8A) 1 4 * *EOR A, opr @D A+- AV(D) 1 1 *N A +- AV(N) 2 2 *#N A+- AV#N 2 2 *OR A, opr @D A+- AV(D) 1 1 *N A+- AV(N) 2 2 *#N A+- AV#N 2 2 *AND A, opr @D A +- A (D) 1 1 *N A +- A #(N) 2 2 *#N A +- A #N 2 2 *237

• MSM62580 .--------...,-----------------MNEMONIC oprOPERATION BYTE CYCLEFLAGSC P H ZINC opr A A+-A+1 1 1 *D D+-D+1 1 1@D (D) +- (D) + 1 1 1 *N (N) +- (N) + 1 2 2 *DEC opr A A +- A-1 1 1 *,D D+-D-1 1 1@D (D) +- (D)-1 1 1 *N (N) +- (N)-1 2 2 *RRC opr A C;C .... A7 -0:1 1 1 * *@D 4C .... (D)7-0:::J 1 1 * *N l;C .... (N)7-0:1 2 2 * *RLC opr A CC+-A7-0+l 1 1 * *@D [C +- (D)7-0~ 1 1 * *N Cc +- (N)7-0~ 2 2 * *PUSH oprPOP oprPSW(SP)+-A,(SP -1)+-CCR,SP+-SP-21 3D (SP)+-D, SP""'SP-1 1 2PSWCCR+-(SP -1), A+-(SP - 2),SP+-SP+2D D+-SP+1, SP+-SP+1 1 21 3 * * * *JZ opr addr if Z= 1, PC+-PC+2+addr 2 2/3JNZ opr addr if Z= 1, PC+-PC+2+addr 2 2/3JC opr addr if C= 1, PC+-PC+2+addr 2 2/3JNC opr addr if C=1, PC+-PC+2+addr 2 2/3JB opr baddr,addr if(baddr) = 1 ,PC+-PC+ 3 +addr 2 3/4JNB opr baddr,addr if(baddr) = 1, PC+-PC+3+addr 2 3/4DJNZ opr Rn,addrRn-Rn-1, if Rn=O,PC+-PC+2+addr (n=4-7)2 3/4JMNE opr #N,addr if (D) "* #N, PC-PC+3+addr 3 3/4JDNE apr #N,addr itO", #N, PC+-PC+3+addr 3 3/4238

-------------------------. MSM62580 •MNEMNIC opr OPERATION BYTE CYCLEFLAGSC P H ZJMP opr addr PC+-addr(O-4K) 2 2CAL opraddr~P)+-PC+2, PC+-addr(O-4K)P+-SP-22 4CZP opr addr (SP)+-PC+2,PC+-ZP,SP+-SP-2 1 4RT PC+-(SP), SP+-SP + 2 1 3NOP No Operation 1 1CLR opr A A+-O 1 1 1RC C+-O 1 1 0SC C +- 1 1 1 1RB baddr (baddr) +- 0 2 2SB baddr (baddr) +- 1 2 2CPL opr A A+-A 1 1 *C C+-C 1 1 *CHK opr P P+-C, if A=odd, C+-1 ELSE C+-O 1 1 * *SIN C +- SIO 1 1 *SOUT SilO +- C 1 1DLY opr #N DELAY N+3 CYCLES 2 3-258239

OKI semiconductorMSM66301OKI ORIGINAL HIGH PERFORMANCECMOS SINGLE-COMPONENT 8/l6-BIT MICROCONTROLLERGENERAL DESCRIPTIONThe OKI MSM66301 is a an new generation, high performance single component microcontrollerinplemented in sill icon gate complementary metal oxide semiconductor technology (CMOS).Integrated within this chip are 16-bit ALU, 16K bytes of mask program ROM, 512 bytes of data RAM,48 I/O lines, built-in 16-bit timers, 1 O-bit AID converter, serial I/O port pulse, width modulator (PWM),and oscillator.FEATURES• 8-Bit External Data Bus Interface• 16-Bit Internal Architecture• 64K address space for program memory(including 16K bytes onchip ROM)• 512K address space for data memory(including 512 bytes onchip RAM)• High speed executionMinimum Cycle for Instruction: 400ns(10MHz)• The Abundance of Powerful Instructions8/16 data transfer operation8/16 bit arithmetic operation16(8) bit x 16(8) bit ~ 32(16) bit32(16) bitl16 (8) bit ~ 32(16) bit16(8) bit ± 16(8) bit ~ 16(8) bit8/1 6 logic operationBit operationSiring operationUser stack operationROM table access operation• The same instruction allows both byte' andword width operation according to DataDescriptor.That is to say, the same algorithm and thesame source program lines are applicable tobyte and word width data manipulation withonly changing Data Descriptor.• Many Addressing Modes• 8 Input lines, 40 InputiOutput lines• Built-in 16 bit timer x 4Each timer has the following 4 modes.Auto reload timer modeClock out modeCapture register modeReal time output mode• Serial Port x 1 ch.(variable bit length, baud rate generators fortransmitter & receiver)Asyncronous normal modeAsyncronous multi processorcommunication modeSyncronous normal modeSyncronous multi processorcommunication mode• 16 bit Pulse Width Modulator x 2• Transition Detector x 4• 10 bit A/D converter (8 channel)• 1 non-maskable interrupt, 1 6 maskableinterrupts• Stand-by Functionsoftware Clock stopsoftware CPU stophardware CPU stop• 64 pin Shrink DIP/64 pin plastic flatpackage/68 pin PLCC240

------------------------. MSM66301 •PIN CONFIGURATIONADO/POO 1AOf/POtAD21P02AOS/P03AD41P04AD51P05ADB/PoeAD71P07AS/P11Al01P12Al1!P13A12/Pt4A14/P16A1S/PH 1A16/P20 1CLKOUT/P23RESOUT 21ALE 2PSEN 2.RiiWRREADY,EA 7mRES 29OseD6§lITGND•VDDVREFAGNDPS7/A17P5S/AISP54/AI4P53/A13P52/AI2P47ffRANS3P4&ITRANS2P45ITRANSfP44ITRANSOP43/PWM1P42/PWMOP41/TM1CKP4QITMOCKP37fTM310P36ITM21OP35/TM11OP34fTMOiOP33/iNT"1P32/iNTOP31/RXDP30ITXDP27IRXCP26ITXCP25/HLDAP24IHOLDFUNCTIONAL BLOCK DIAGRAMTMCK1TMCKOTMIO.TMI02TMlO1TMIOORxDRxDRxCTXCEAREADY-ALE-~-AD-WRTRANS3 -TRANS.TRANS1TRANSGVREFA17-A10AGNDROMAD7ADD"8ASPWM1PWMDt tV GD ND DSYSTEM CONTROL!tllfnflft00 C R R.F H H T TSSLEELOLNNCCKSSTLDTTo 1 0 E 0 0 ·A. 1 0U T UT TPS P4 P3 P2 PI PO2.41

eMSM66301 e----------------------------------__ ------------PIN DESCRIPTIONDesignation Input/Output FunctionPoo- P07/PO: a-bit I/O port. Each bit can ·be assigned to input oroutput.ADo-AD7 I/O AD: Outputs the lower a bits of program counter duringexternal program memory fetch, and receives theaddressed instruction under the control of PSEN.Also outputs the address, Outputs or inputs dataduring an external data memory accessinstruction, under control of ALE, RD, and WR.P1O- P17/ I/O P1 : 84:>it I/O port. Each bit can be assigned to input oroutput.As- A15 A: Outputs the middle a bits of program counter(PCa-15) during external, program memory fetch.Also outputs the middle a bits of address duringan external data memory access instructions.P20- P22f P2: 8-bit I/O port. Each bit can be assigned to input oroutput.A1S-A1S A: Outputs the upper 3 bits of address during externaldata memory access instructions.P23/CLKOUTCLKOUT: clock output pin. Output frequency range isequal to or twice the system clock.P24/HOLD I/O HOLD: Input pin to request the CPU to enter thehardware power-down state.P25/HLDA HLDA: HOLD ACKNOWLEDGE: the HLDA signalappears in reponse to the HOLD signal andindicates that the CPU has entered thepower-down state.P2s/TxC TxC: Transmitter clock input pin.Pu /RxC RxC: Receiver clock input pin.P30/TxDP3: -a-bit I/O port. Each bit can be aSSigned to input oroutputP31/RxD TxD: Transmitter data output pin.P3211NTO RxD: Receiver data input pin.P3311NT1 I/O INT: Interrupt Request Input pin.Falling edge trigger or level trigger isselectable.P34/TMOI0 TMOIO - TM310: One of the following signals is outputor input:P35/TM110 •clock twice the frequency range of the 16bit timer overflowP3s/TM210• load trigger signal to the capture registerinputs~tting•value outputThe signal that is input or output depends on the mode.P37/TM310242

-------------------------. MSM66301 •PIN DESCRIPTION (Continued)Designation Input/Output FunctionP4o/TMOCK.P4: 8 bit 1/0 port. Each bit can be assigned to input oroutput.P4dTM1 CK TMOCK, TM 1 CK: clock input pins of timer 0, timer 1 .P42/PWMO 1/0 TRNS: Transition Detector.The input pins which sense the falling edgeand set the flag.P43/PWM1PWM: Pulse Wide Modulator output pin.P44-P4?1TRANSO - TRNS:JP50-P5?1 INPUT P5: 8 bit input port.AIO-AI? AI: analog sygnal input pin to AID converter.RESOUT OUTPUT Output 'H' level when the CPU is in RESET cycle.Reset to 'L' level by program.ALE OUTPUT Address Latch The timing pulse to latch the lowerEnable:8 bit of the address output fromport 0 when the CPU accesses theexternal data memory.PSEN OUTPUT Program Store The strobe pulse to fetch to exter-Enable:nal program memory.RD OUTPUT Output strobe activated during a BUS read.Can be used to enable data on to the bus from theexternal data memory.WR OUTPUT Output strobe during a bus write.Used as write strobe to external data memory.READY INPUT Used when the CPU accesses low speed peripherals.EA INPUT Normaly set to 'H' level.If set to 'L' level, the CPU fetches the code to externalprogram memory.FLT INPUT If FLT is 'H' level, ALE, WR, RD, PSEN are set 'H' levelwhen reset.If FLT is set to 'L', ALE, WR, RD PSEN are set to floatinglevel when reset.RESET INPUT RESET input pin243

• MSM66301 .--~------------------------------~--------------PIN DESCRIPTION (Continued)Designation Input/Output FunctionOSCo,OSC, Oscillation circuit consists of OSCo, OSC ,.NMI INPUT non maskable interrupt input pin (falling edge)VREFAGNDVDDGNDreference voltage input pin for AID converterground for AID convertersystem power supplygroundREGISTERS15 0• ACCUMULATOR CACCDCONTROL REGISTERS (CR)•PROGRAM STATUS WORD pswIPROGRAM COUNTER pcILOCAL REGISTER BASE LRBISYSTEM STACK POINTER sSPI•POINTING REGISTERS (PR)INDEX REGISTER1INDEX REGISTER2DATA POINTERUSER STACK POINTERXlX2DPusp• LOCAL REGISTERSerO rl rOerl r3 r2er2 r5 r4er3 r7 r6• SPECIAL FUNCTION REGISTERS (SFR)All of the 1/0 functions are controlled by SFRs.Also, some of the internal functions (Timer, WDT,etc, ...) are controlled by SFRs. SFRs are located in the top of RAM space (OOOH - 007FH).244

--------------------------. MSM66301 •MSM66301 Special Function Registers [1]8/16 WhenAddress Name Abbrebiation R/W Operation reset0000 System Stack Pointer SSPl R/W 8/16 FF0001 SSPH FF0002 local Register Base lRBl R/W 8/16 unknown0003 lRBH0004 Program Status Word PSWl R/W 8/16 000005 PSWH 000006 Accumulator ACCl R/W 8/16 000007 ACCH 000008 Source Index Register SI R/W 16 unknown0009 for Block TransferOOOA Destination Index Register 01 R/W 16 unknownOOOBOOOCOOOEfor Block TransferCounter Register CX R/W 16 unknownfor Block TransferSource/Destination BSDI R/W 8 unknownBank Register0010 Stand-By Control Register SBYCON R/W 8 000011 Watch Dog Timer WDT R/W 80012 Peripheral Control Register PRPHF R/W 8 010016 Work Area for Emulator R/W 16 unknown00170018 Interrupt Request Flag IRQl R/W 8/16 000019 IRQH 00001A Interrupt Enable Flag IEl R/W 8/16 00001B IEH 00001C External Interrupt EXICON R/W 8 00Control Register-245

• MSM66301·----------------------------------------~--------MSM66301 Special Function Registers [2]8/16 WhenAddress Name Abbrebration R/W Operation reset2460020 Port 0 Data Register P'O R/W 8 Unknown0021 Port 0 Mode Register POlO R/W 8 000022 Port 1 Data Register P1 R/W 8 unknown0023 Port 1 Mode Register P110 R/W 8 000024 Port 2 Data Register P2 R/W 8 unknown0025 Port 2 Mode Register P210 R/W 8 000026 Port 2 Special Function P2SF R/W 8 00Control Register0028 Port 3 Data Register P3 R/W 8 unknown0029 Port 3 Mode Register P310 R/W 8 00002A Port 3 Special Function P3SF R/W 8 00Control Register002C Port 4 Data Register P4 R/W 8 unknown0020 Port 4 Mode Register P410 R/W 8 00002E Port 4 Special Function P4SF R/W 8 00Control Register002F Port 5 P5 R 80030 Timer 0 Counter TMO R/W 16 000031 000032 Timer 0 Register TMRO R/W 16 000033 000034 Timer 1 Counter TM1 R/W 16 000035 000036 Timer 1 Register TMR1 R/W 16 000037 000038 Timer 2 Counter TM2 R/W 16 000039 00003A Timer 2 Register TMR2 R/W 16 000038 00003C Timer 3 Counter TM3 R/W 16 000030 00003E Timer 3 Register TMR3 R/W 16 00003F 00

-------------------'--------. MSM66301 •MSM66301 Special Function Registers [3]8/16 WhenAddress Name Abbrebiation R/W Operation reset0040 Timer 0 Control Register TCONO R/W 8 000041 Timer 1 Control Register TCON1 R/W 8 000042 Timer 2 Control Register TCON2 R/W 8 000043 Timer 3 Control Register TCON3 R/W 8 000046 Transition Detector Reg. TRNS R/W 8 000013 Stop Mode Buffer Flag R/W 8 00247

eMSM66301 e------------------------------------------------MSM66301 Special Function Registers [4]8/16 WhenAddress Name Abbrebiation R/W Operation reset0046 Transition Detector TRNS R/W 8 000048 Transmitter Clock Generator STTM R/W 8 000049 Transmitter Clock Generator STTMR R/W 8 00Control Register004A Transmitter Control Register STTMC R/W 8 00004C Receiver Clock Generator SRTM R/W 8 000040 Receiver Clock Generator SRTMR R/W 8 00Control Register004E Receiver Control Register SRTMC R/W 8 000050 Transmitter Mode Control Register STCON R/W 8 000051 Transmitter Data Buffer STBUF W 8 unknown0054 Receiver Mode Control Register SRCON R/W 8 000055 Receiver Data Buffer SRBUF R 8 unknown0056 Receiver Eroor Status Register SRSTAT R 8 000058 AID Scanning Mode Register ADSCAN R 8 000059 AID Select Mode Register ADSEL R/W 8 000060 AID Convert Result Register 0 ADCROL0061 ADCROH0062 AID Convert Result Register 1 ADCR1L0063 ADCR1H0064 AID Convert Result Register 2 ADCR2L0065 ADCR2H0066 AID Convert Result Register 3 ADCR3L0067 ADCR3H0068 AID Convert Result Register 4 ADCR4L0069 ADCR4H006A AID Convert Result Register 5 ADCR5L006BADCR5H006C AID Convert Result Register 6 ADCR6L0060 ADCR6H006E AID Convert Result Register 7 ADCR7L006FADCR7HR 8/16 unknownR 8/16 unknownR 8/16 unknownR 8/16 unknownR 8/16 unknown8/16 unknownR 8/16 unknownR 8/16 unknown248

--------------------------. MSM66301 •MSM66301 Special Function Registers [5]8/16 WhenAddress Name Abbrebiation R/W Operation reset0070 PWM 0 Counter PWMCOL 00R/W 8/160071 PWMCOH 000072 PWM 0 Register PWMROL 00R/W 8/160073 PWMROH 000074 PWM 1 Counter PWMC1L 00R/W 8/160075 PWMC1H 000076 PWM 1 Register PWMR1L 00R/W 8/160077 PWMR1H 000078 PWM 0 Control Register PWCONO R/W 8 00007A PWM 1 Control Register PWCON1 R/W 8 00249

• MSM66301 .~~----------------------------------------------ADDRESSING MODEThe MSM66301 supports 512KB (64KB x 8BANKs) 05 data space and 64KB of prog~am spacewith verious typeS of addressing methods. These methods divide into the following types.1. RAM ADDRESSING (FOR DATA SPACE)1.1 Register Direct AddressingRDRDPl-·--------l»/WffiDP0%/ffiJ1.2 Displacement Addressinga) Zero PageL[~OOOH0010Hob) Direct Pager-- ex. ST A,off XXI OH,!.. - - - - - - - --RAMxxOOHxxl0H1.3 POinting Register Indirect Addressinga) Data Pointer (DP) IndirectSLL[DP]---;- ,!DPb) User Stack Pointer (USP) Indirectr--- ex. ----------------------------~----------------------------_,SRL 10H [USP]0-2551r'------,.U"'S.."P---RAM250

-------------------------. MSM66301 •c) Index register (X1, X2) Indirectex. ---------------------------------~INC 300H [X 11X1I ,.,~,1.4 Immediate AddressingMOVSSP, # ;1 ~~27~F~H~~2. ROM ADDRESSING (FOR PROGRAM SPACE)2.1 Direct AddressingLex. _JMP-,-----200H_~ _I------.JI._ROM_ '-------Fh0WflVA 0>,," "2.2 Pointing Register Indirect Addressinga) Data Pointer (DP) IndirectLC[~[DP]DPb) User Stack Pointer (USP) Indirectex.---·--------------------------------------------,10H [USP]T ~I i_-..:::.;US;:.:..p_----'~55 T- ~c) POinting Register (X1, X2, DP, USP) Indirect with 16bit displacementex. ----------------------------------------------------~--~CMPC300H0-65535[X1]--II'X1251

, • MSM66301 .------------------------­INSTRUCTIONSData TransferInstruction Function Instruction FunctionL A,- A - -LB A, * AL - *ST A,_ A --+MOV *, A * --STB A,* AL--+A MOVB A, * AI--*MOV -, # * - Imme. MOVB -,A - ALMOVer. _er- * MOVB *, #- -MOV d, * (d)- -MOVB r, - r - -MOVMOVDP, _X1, _1m me.DP MOVB d, * (d)- - *X1- -MOVB PSWO, * PSWO- -MOV X2,_ X2- * MOVB SCB,- SCB- *MOV USP, * USP- *MOV PSW,. PSW- -MOV SSP, • SSP- *MOV LRB,. SSP- *CLR* * - 0 CLRB * - - 0SWAP A15-8~A7-O SWAPB A7-4-A3-0XCHG A, A-* XCHGB AL-*XNBL A, A3-0---*3-0TRNS USP, LRBTRNS LRB, USPPush & PopUSPW3- LRB'2-0USP2-0- 0LRB,2'-O- USP,5-3LRB'5-'3 - 0Instruction Function Instruction FunctionPUSHU * • --+ USER STACK PUSHUB --+* * USER STACKPOPU A A-USER STACK POPUB A AL - USERSTACK-PUSHS --+* SYSTEM STACKPOPS * * - SYSTEM STACK252

----------------,-----------. MSM66301 •Rotate & ShiftInstruction Function Instruction FunctionROL • Rotate-ROLB • Rotate -ROR • Rotate-RORB • Rotate -SLL • Shift- Logical SLLB · Shift - LogicalSRL· Shift - Logical SRLB * Shift- LogicalSRA· Shift - Arithmetic SRAB • Shift- ArithmeticIncrement & DecrementInstruction Function Instruction FunctionINC· • - *+1 INCB * * - *+1DEC * * - *-1 DECB · • - * - 1ROM Table ReferenceInstruction Function Instruction FunctionLC A,* A - • (ROM) LCB A,* AL - • (ROM)CMPC A,* A-. (ROM) CMPCB A, • AL - * (ROM)253

• MSM66301 • --------------------'--------Arithmetic OperationInstruction Function Instruction FunctionMUL er1: A - AXerO MULB A. - ALxrODIV erO: A- erO: Afer2 DIVB A - AfrOADD A, * A- A+* ADDB A, * AL - AL +*ADD *, A * - *+A ADDB *,A * - * +ALADD *, d * - * + !d) ADDB *, d * - * + (d)ADD *, # * - * + Imme. ADDB *, # * - * + Imme.ADC A, * A A+* +C ADCB A,* AL -ADC *, A * - * +A+C ADCB *,A * -ADC *, d * * + (d) +C ADCB *, d * -ADC *, # * - * +Imme. +C ADCB *, # * -SUB A,* A- - A - * SUBB A, * ALAL +* +C* +AL +C* + (d) +C* +Imme. +CAL -*SUB *, A * *-A SUBB *,A * *-ALSUB *, d * - * - (d) SUBB *, d * *- (d)-SUB *, # * - * -Imme. SUBB *, # * - * -Imme.SBC A, .. A- A-*-C SBCB A, * AL - AL -* CSBC *,A * - *-A-C SBCB *,A * - * - AL - CSBC *, d * - * - (d) - C SBCB *, d * - * - (d) - CSBC *, # * - * -Imme.-C SBCB *,# * - * -Imme. - C254

--------------------"'-----. MSM66301 •Logical,OperationInstruction Function Instruction FunctionAND A,. A~Aand * ANDB A, • AL~ALand·AND -, A *AND *, d-AND -, #-~~ ~* and A ANDB -,A • • and AL~- and (d) ANDB " d . ~* and (d)-~- and Imme. AN DB " # - and Imme.OR A,- A~A or- ORB A,- AL~AL or-- -~ ~OR -, A - or A ORB -,A~OR -, d - or (d) ORB -, d---~OR -, # - or Imme. ORB -, #-~*~-- or ALor (d)or Imme.XOR A, -~AXOR *, A-~XOR *, d *XOR -, # *~Axor * XORB A, - AL AL xor-- xor A XORB *,A-~* xor AL~* xor (d) XORB *, d-~- xor (d)~* xor Imme. XORB -, #-~- xor Imme.ComparisonInstruction Function Instruction FunctionCMP A, * A - * CMPB A, * AL - *CMP *, A * - A CMPB *, A * -ALCMP -, d - - (d) CMPB *, d * - (d)CMP -, # - -Imme. CMPB *, # * -Imme.255

eMSM66301 e--------------------------------------------------Stack OperationInstructionFunctionADD A. [+USP] USP USP+2,A A + [USP]ADC A. [+USP] USP - USP+2,ASUB A. [+USP] USP USP+2,A A- [USP]SBC A. [+USP] USP - - USP+2,AANDA. [+USP] USP USP+2,AORA.[+USP] USP USP +2,A Aor [USP]XOR A. [+USP] USP- - USP +2,ACMP A. [+USP]USP-USP + 2, A - [USP]A +[USP] +CA- [USP]-CA and [USP]Axor [USP]Decimal AdjustInstructionFunctionDAADASDecimal Adjust for AddDecimal Adjust for SubstructBit OperationInstruction Function Instruction FunctionSBR * bit- 1 SB * bit 1RBR * bit- 0 RB * bit- 0MBR C, * C- bit MB C, • C - bitMBR *, C bit- C MB *, C bit - CTRB * Z - bitExecuteInstructionFunctionEX * Execute Specified Data as the'lnstruction256

-------------------------. MSM66301 •Jump & CallInstruction Function InstructionSJ adrs Short Jump SCAl adrsShort CallFunctionI"* JumpCALJC EQ, adrs Jump if '=' JC NE, adrsJC lE, adrs Jump if '< =' JC IT,adrsJC GE, adrs Jump if' > =' JC GT, adrsJBS bit, adrs Jump if bit-on JBR bit, adrsJRNZ, DP, adrs loop Function VCAladrs*Call SubroutineJump if' 'f- >' xJump if'*'

8 B,IT SERIES (INTEL COMPATIBLE)

OKI semiconductorMSM80C35/48MSM80C39/49MSM80C40/50CMOS 8-BIT SINGLE CHIP MICROCONTROLLER, GENERAL DESCRIPTIONThe OKI MSM80C48/MSM80C49/MSM80C50 microcontroller is a low-power, high-performance8-bit single chip devicer implemented in silicon gate complementary metal oxide semiconductortechnology. Integrated within these chips are 8K/16K/32K bits of mask program ROM,512/1024/2048 bits of data RAM, 27 I/O lines, built-in 8 bit timer/counter, and oscillator. Programmemory and data paths are byte wide. Eleven new instructions have been added to the NMOS version'sinstruction set, thereby optimizing power down, port data transfer, decrement and port floatfunctions.Available in 40-pin plastic DIP (RS) or 44-pin plastic flat packages (GSK).FEATURES• Lower power consumption enabled by CMOSsilicon gate process• Completely static operation• Improved power-down feature• Minimum instruction cycle 1.36 p,s (11 MHz)@VCC=+5V±10%11 MHz version of MSM80C50 (6 MHz

• MSM80C35/48, 80C39/49, 80C40/50 .1--------------FUNCTIONAL BLOCK DIAGRAMSINGLESTEPDATA MEMORY (AAM)64 x 8 MSMBOC48RS128 x 8 MSM80C49RS256 ~ 8 MSM80C50ASPIN CONFIGURATION(Top View) 40 Lead Plastic DIPTOXTAL1XTAL2VeeT1P27RESETP2655 P2,INT P2.EA P1 7AD?SENWRALEPl.Pl,Pl.P13DBoPl,DB,Pl,DB,PloDB3VDDDB.PROGDB,P23DB. P2,DB7 P2,VssP20Pin NameP1 0 - P1 7P20 - P27DBo - DB7TO, T1INTRDWRALEPSENRESETSSEAXTAL 1, 2: I nput/output port (PORTH: Input/output port (PORT2): Data bus port (BUS PORT): Test: Interrupt: Read: Write: Address Latch Enable: Program Store Enable: Reset: Single Step: ROM Mode: Crystal Controlled Oscillator262

--------------...... MSM80C35/48, 80C39/49, 80C40/50 •.PIN DESCRIPTIONDesignation InputlOutput FunctionPI 0- PI7 Input/Output 8-bit quasi-bidirectional port(PORT I)P20-P27 Input/Output 8-bit quasi-bidirectional port(PORT 2)The high-orderfour bits of external program memory addresses can beoutput from P20-P23, to which the 1/0 expander MSM82C43RS may alsobe connected.DBo-DB7 Input/Output Bidirectional port(BUS)The low-order eight bits of external program memory address can beoutput from this port, and the addressed instruction is fetched under thecontrol of PSEN signal. Also, the external data memory address is output, anddata is read and written synchronously using RD and WR signals.The port can also serve as either a statically latched output port or anon-latching input port.TO InputlOutput The input can be tested with the conditional jump instructions JTO and(Test 0)JNTO. The execution of the ENTO ClK instruction causes a clock output tobe generated.T1 Input The input can be tested with the conditional jump instructions JTI andJNTI . The execution of a STRT CNT instruction causes an internalcounter inputlo be activated.!NT Input Interrupt input. If interrupt is enabled, INT input initiates an interrupt.(Interrupt)Interrupt is disabled after a reset.Also testable with a JNI instruction. Can be used toterminate thepower-down mode. (Active"O"level)RD Output A signal to read data from external data memory. (Active "O"level)(Read)WR(Write)ALEAddress &Data latchClockA signal to write data to external data memory. (Active "O"level)This signal is generated in each cycle. It may b:: :.:sed as a clock output.External data memory or external program memory is addressed upon thefalling edge. Forthe external ROM, this signal is used to latch the bus portdata upon the ALE signal rise-up after the execution of the OUll BUS, Ainstruction.PSEN Output A signal to fetch an instruction from external program memoryProgram(Active "0" level)Store EnableRESET Output (RESET) input initialize the processor. (Active "O"level)Used to terminate the power-down mode.SS Output A program is executed step by step. This pin can also be used to control(Single Step)internal osci lIation when the power-down mode is reset.(Active"O"level)EA Input When held at high level, all instructions are fetched from external memory.(External Access)(Active "I "level)PROG Output This output strobes the MSM82C43RS 1/0 expander.(Expander Strobe)263

• MSM80C3S/48, 80C39/49, 80C40/50 .------....,..----.;...------­PIN DESCRIPTION (CONT.)Designation Input/Output FunctionXTAL 1 Input One side of the crystal input for the internal oscillator. An external source can(Crystal 1)also be input.XTAL2 Output Other side of Crystal input for internal oscillator.(Crystal 2)VCC - Power supply terminalVOO - Standby control input. Normally, "1" level. When set to "O"level,oscillation is stopped and processor goes into sta.ndby mode.VSS - GNONote: The required RESET pulse duration is at least two machine cycles under the condition that the power supplyand the oscillator have been stabilized.264

----------~---_e. MSM80C3S/48, 80C39/49, 80C40/S0 •ADDED FUNCTIONS OF MSM80C48, MSM80C49 AND MSM80C50The MSM80C48, MSM80C49 andMSM80C50 basically incorporate the capabilitiesof Intel's 8048, 8049, and 8050 plus the followingnew functions:1. Power-Down Mode Enhancements1 .1 Power-down by software(1) Clock (See item 4, "Power-down mode", fordetails.)a. Crystal-controlled oscillator halt (HL TSinstruction)Power requirements can be minimized.b. Clock supply halt (HALT instruction)Restart is accomplished without oscillatorwait.(2) 1/0 ports (See Table 4-1 and 4-2 fordetails.)110 port floating instructionsPower consumption resulting from inputsloutputs can be minimized with FL T andFL TT instructions.Port floating is cancelled !!LexecutingFRES instruction, "0" level at INT pin or "0"level at RESET pin.(3) Six types of power-down can be done by acombination of HL TS/HAL T and FL T IFL TTinstructions.1.2 Power-down by hardware (See 4.3,Power-down mode by VDDpin utilizationfor details.)Crystal-controlled oscillators can be haltedby controlling the VDD terminal, thereby floatingall 1/0 ports for minimum power consumption.2. Additional Instructions (11)HLTSHALTFLTFLTTFRESMOVA, P1MOVA, P2MOVP1,@ R3MOVP1 P, @R3DEC @RrDJNZ @ R, addr3. Improved Uses of BUS Po - 7, P1 0 - 7,P20 - 7, and SS terminals3.1 BUSPo-7The MSM80C48, MSM80C49, andMSM80C50 remove the limitation on the use ofOUTL BUS, A instructions during the externalROM access mode by having an independentdata latch and external ROM mode addresslatch in BUS Po - 7.Consequently, there is no need to relocatebus port instructions when in the external ROMaccess mode.3.2 P1 0 - 7 and P20 - ?The MSM80C48, MSM80C49 andMSM80C50 are designed to minimize powerconsumption when P1 0 - 7 and P20 - 7 are usedas input/output ports, to maximize the performanceof CMOS.When these porfs are used as output ports,the acceleration circuit is actuated only whenoutput data changes from "0" to "1 ", thus speedingup the rise time of the output signals.When these ports are used as input ports,the internal pullup resistance becomes approximately9 kf! when input data is "1".The internal pullup resistance rises to ap':proximately 100 kf! when input data is "0".Thus, a high noise margin can be obtained byselecting the impedance and thus the outflow ofcurrent is minimized whenever these ports areused as output or input ports.3.3 Clock generation control via the SSterminalWhen the crystal-controlled oscillator ishalted in the HL TS or hardware power-downmode, the SS terminal is pulled down by a resistorof 20 - 50 kn, while its internal pullup resistorof 200 - 500 kn is isolated from VCC. Whenthe power-down mode is cancelled, the internalresistor of the SS terminal is changed from pulldownto pullup. Consequently, the CPU can behalted for any period of time until the crystalcontrolledoscillator resumes normal oscillationwhen a capacitor is connected to the SS terminal.4. Power-Down ModeThe MSM80C48, MSM80C49, andMSM80C50 power-down mode can be enabledin 2 different ways-through software by a combinationof clock control and port floatinginstructions, and through hardware by control oftheVDD pin.4.1 Software power-down modePower-down mode can be done by a combinationof the following instructions.(1 ) HALT (clock supply halt to control circuit)Instructioncode:I 0 0 0 0 I 0 0 0 1 IDescription: Although crystal-controlledoscillator operation is continued,the clock supply tothe CPU control circuit ishalted and CPU operationssuspended. When cancellingthis software mode, restart isaccom plished without oscillatorwait. Timing chartsare outlined in Figs. 4-1 and4-2.(2) HL TS (oscillation stop)Instructioncode:Description:rl-1~·-0--0--0--1-0--0--1--0~The oscillator operation ishalted and CPU operationssuspended. In cancellingthis power down mode, connectinga capacitor to the SSpin enables a reasonable265

• MSM80C35/48, 80C39/49, 80C40/50 .---r------~---~wait period to be. accomplishedbefore normal operationis resumed. [Except iTthe case of using the RESEpinJTiming charts are outlined inFigs. 4-3 and 4-4.(3) FL T (floating P1 0 - 7, P20 - 7, and SPo - 7)Instructioncode:101 000 1 0IDescription·~ Internal ROM External ROM modemodePI Floating FloatingP2FloatingP20 -- 3 operationP2. - 7IloatingBP Floating OperationDetails of IC pin status as a result of executingthe FLT instruction are shown in Table4-1.(4) FLTT (floating of alloutput pins)Instructioncode:Description·~ Internal ROM External ROM modemodeALE Floating OperationPSEN Floating OperationPROG Floating FloatingWR Floating FloatingRD Floating FloatingTOOUT Floating FloatingPI Floating FloatingP2FloatingP20 -- 3 operationP2. - 7 floatingBP Floating OperationXTAL Operation OperationDetails of IC pin status as a result of executingthe FLTT instruction are shown in Table4-2.Example 1:Example 2:Example 3:Power-down mode accomplishedby stopping oscillation.o Setting by execution ofHLTS [82HJ instruction.Power-down mode accomplishedby stopping the clocksupply to the CPU controlcircuit.o Setting by execution ofHALT [01 HJ instruction.Power-down mode by floatingof P1 0 - 7, P20 - 7 and SPo -7, and subsequent stopping ofCPU oscillation.o Setting by first executingthe FL T[A2 HJ instructionand then the HLTS[82HJ instruction.Example 4: Power-down mode by floatingP10 - 7, P20 - 7 and SPo - 7,and then stopping the clocksupply to the CPU control circuit.o Setting by first executingthe FL T[A2HJ instruction,and then the HALT[01 HJ instruction.Example 5: Power-down mode by floatingall output pins, followed bystopping oscillation.o Setting by first executingthe FLTT[C2HJ instructionfollowed by execution ofthe HLTS[82HJ instruction.Example 6: Power-down mode by floatingall output pins, followed bystopping of the clock supply tothe CPU control circuit.o Setting by first executingthe FL TT[C2HJ instruction,followed by execution ofthe HALT[01 HJ instruction.4.2 Cancellation of software power-downmodeThe power-down mode status outlinedabove in examples 1 to 6 can be cancelled byusing either the interrupt pin or the RESET pin.(1) Use of the INT pin during external interruptenabled mode (j.e. following execution ofEN I instruction).o The clock generator is activated and theCPU started J!Q.. when a "0" level is appliedto the INT pin. If this "0" level ismaintained until at least 2 ALE output'signals occur, an external interrupt isgenerated, and execution proceeds fromaddress 3. If, however, the power-downmode has been done during the interruptprocessing routine, execution isresumed just after the power-downinstruction.(2) Use of the INT pin during external interruptdisabled mode (j.e. following execution ofDIS I instruction or hardware reset)o The clock generator is activated and theCPU. started .!!Q.. when a "0" level is appliedto the INT pin. If this "0" level ismaintained until at least 2 ALE outputsignals occur, execution is resumed justafter the ~ower-down instruction.(3) Use of the R SET pino The clock generator is activated and theCPU started-':!.P....Y'Lhen a "0" level is appliedto the RESET pin. If this "0" level ismaintained until at least 2 ALE outputsignals occur, the CPU is reset and executionproceeds from address '0. In casecancellation is done in oscillation stopmode, the "0" level must be input to theRESET PIN uritil oscillation is stabilized.266

---------------e. MSM80C35/48, 80C39/49, 80C40/50 •Table 4-1Details of Pin Status Following Execut.ion of FLT InstructionPin No. Pin Name Internal ROM External ROM1P TO Active Active2P XTAL1 Active Active3P XTAL2 Active Active4P RESET Active Active5P SS 200 - 500 kO pullup 200 - 500 kO pullup6P INT Active Active7P EA Active Active8P RD Active Active9P PSEN Active Active10P WR Active Active11 P ALE Active Active12P DBO Floating Active13P DB1 Floating Active14P DB2 Floating Active15P DB3 Floating Active16P DB4 Floating Active17P DB5 Floating Active18P DB6 Floating Active19P DB7 Floating Active20P VSS o [V] o [V]21P P20 Floating Active22P P21 Floating Active23P P22 Floating AcUve24P P23 Floating .. Active25P PROG Active Active26P VDD "1 "level "1" level27P P10 Floating, Floating28P P11 Floating Floating29P P12 Floating Floating30P P13 Floating Floating31P P14 Floating Floating32P P15 Floating Floating33P P16 Floating Floating34P P17 Floating Floating35P P24 Floating Floating36P P25 Floating Floating37P P26 Floating Floating38P P27 Floating Floating39P T1 Active Active40P Vee +2 to +6 [V] +2 to +6 [V]Note: The FLT mode itself is reset by executing the FRES instruction, or supplying "O"level to INT or RESET pin.267

• MSM80C35/48, 80C39/49,80C40/50 .,---'--------------Table 4·2 Details of Pin Status Following Execution of FLTT Instruction.Pin No. Pin Name Internal ROM External ROM1P TO Floating if output enabled Floating if output enabled2P XTAL1 Active Active3P XTAL2 Active Active4P RESET Active ,Active5P ~ SS 200 to 500 kO pullup 200 to 500 kO~ pullup6P INT Active Active7P EA Active Active8P RD Floating Floating9P PSEN Floating Active10P .WR Floating Floating,11P ALE Floating , Active12P DBO Floating Active\ 13P DB1 Floating Active14P DB2 Floating Active15P DB3 Floating Active16P DB4 Floating Active17P DB5 Floating Active18P DB6 Floating Active19P DB7 Floating"Active20P VSS o [V) o [V)21P P20 Floating Active22P P21 Floating Active23P P22 Floating Active24P P23 Floating Active25P PROG Floating Floating26P VDD 11'1" level "1 "level27P P10 Floating, Floating28P P11 Floating Floating29P P12 Floating Floating30P P13 Floating Floating31P P14 Floating Floating32P P15 Floating Floating33P P16 Floating Floating34P P17 Floating . Floating35P P24 Floating Floating36P P25 Floating Floating37P P26 Floating Floating38P P27 Floating Floating39P T1 Active Active40P Vee +2.5to+6M +2.5 to +6 [V)-Note: The FLTT mode itself is reset by executing the, FRES instruction, or supplying "0" level to INT or RESET pin.268

----------------e. MSM80C35/48, 80C39/49, 80C40/50 •XTAL 1ALE• 1'T11T21T31 T41 I '1 I I IInnnnnnnnnnnnn nnnn n0'UUUpUUpUUpUU""UUU~~4 I' 'I1: : r-!1---!f1-1 ---+""1 ~ m': fTl.H-' : , I I I . I I I' II I Io I 1 I I L-r-I -+-1 -+---' I I:II : : IHALT EXECUTErl i ! ! I I I I. 'I : II: " : I I II I I I1 I I I I ( ': I ' ,CPU MODE -f----lRUN I STOP-{! I 'I RUNI : : IXTAL1 2 ~1_~I~~i -~I--~,~--~~I-~I,RUN-~--~:~I~I_~-+_~_,_~I_+-RESET II,' '",' IIIO'T--I""-~-------~--I--J.-.-"'I"-T--I-I I I I I I 1 I I, I I I RESET EXECUTE I: II I I I : : : : : I I: : : : I I I I , I: : : : :': : : I :* Cancellation Condition: Use RESET pin.Fig. 4-1HALT [01 H] Instruction Execution Timing ChartX'TAL1 1 UJL0 1 ' , I ,'I i ' , ,ALE 11::'1 (f I: : m: rtrlio I I I I I '+, -t--I-: -t-', I I i 4---t-I : : IHALT EXECUTEI-l I I : Ii: 'CPU MODE f----+RUI')I I STOP-fl I : I: IR~~ I IX'TAL 1 . 2 I : 1 I" 'IRUN--t----"'--!I'""II---+-.;_--i---i--i-I--ti-I I 1 I I " i I I I I11 I ,I I I I I IINT I I I I I II "I I IO+---,--r-t--------L.--t""-T---i--+--~"T--I...-T-,-I-~-r-I I I I I , I . , , I ,I I I I INTER~UPT EX~CUTE i I -iI I I I I I I I I II I I I I I I I I II I I I I I I I I II I I I I I, ,I,* Cancellatio~ Conditio'n: Use I NT pin. I I I ,I IX'TAL 1Fig.4-2 HALT [01 H] Instruction Execution Timing ChartI.:.T1 i T2 I T3 I1 nnnnnnnnnn~--+'I~"""O'~Uu",uu!luu!---f:I I IALE 1 I I I II""-+I---!I--I-o II I I. I : I0:.r I HLTS EXECUTE-' , : I ICPU MODE -r---jRU~---rSTOPf·t=' o:t'S~C:-'-";.,.t .. V-O~kI-E ..........;--+-~-+1 Ry~I-";-"---4--+----"'---+--1-X'TAL l' 2 -t----!RUN-+STOPfl-j----1 , !: IRUN-+--+-.L--+-~-+-I I I I RESET pin must bel I I II I I I held at "0" level I I' ,l' I I , until the oscillation I I :' IRESET I I I..L becomes norma!. I I I I IO~--r-t--I-""'--' , I -t--~I j--r-t--l--t-1 I I I J I' I ., I I I55 0 I I: I I I : I I I I I_! I " 1_ I I I' ,!' i ISS 200-500Kn , r 55 200- II IRESET EXECUTE I -,'PULLUP' '500Kn ,I ,I"'" ,55 20-50KO PULLDOWN PULLUP* Cancellation Condition: Use RESET pin.FIg. 4-3 HLTS [82H] Instruction Execution Timing Chart269

• MSM80C3S/48, 80C39/49, 80C40/S0 .,-,--------------X'T AL 1ALE;. . ,.' I . . IIT1'T21T31 T4 - IT51Tl'T2'T'T4'T51Tl'T2'T3'T4,T51IIII'!/~~.JUUl1UUl1UlflI--'JJUI I I I I " , I , , " ,,1 I I , 1m' I , I ,1 I I I II I i I' I , , I I , I I rTli iOl! '·1 I I.' I .1. ,1!l..L...-...i-: I 'HLTS EXECUTE-J , I,!: I I : I ,CPU MODE T--'lRUN----I-STOP{f I I, I IRUN I I I I IX'TAL 1· 2 HRU~--l-STOP/~OSC E'!,OKE ' RUN I I I I , I I I ,I " IWhen,,! 0.47 /.IF capacitor is-l 50- ~ , I I I !! !connected to the SS pin, GOms ' I I I50-60 ms wait WAIT : ' ,I II I I' I : ' II , I I I,' I I I1! I J I I I II I I ii' I' I ,I I IO~--T---~-t------· , ·-+--r-.J--.,--.l.--1"--~-I 'I' I' , , : -, I I I.ri i : ,I I: : : I: ::-! , 'I '_',' ,,!, I ' ,SS 200-500Kn ,. I SS 200-' ,.: INTERRUPT EXECUTE' i Ii PULLUP , I 500KnpULLUP '" I I I , ,SS 20-50Kn PULLDOWN* Canceilation Condition: Use INT pin.Fig.4-4 HLTS [82H] Instruction Execution Timing Chart4.3 Hardware power-down modeIn the MSM80C48, MSM80C49 andMSM80C50, forcing the level at the VDD pin [pin261 to a "0" during either external ROM or internalROM mode results in suspension of the oscillatorfunction and subsequent floating (highimpedance) of all the 1/0 pins except the RESET,SS and XTAL 1/2 pins. The CPU is therebystopped while maintaining internal status.Details of the IC pin status at this time are outlinedin Table 4-3.4.4 Cancellation of hardware power-downmode(1) Use of RESET pino The clock generator is activated and theCPU started up when a "1" level is appliedto t~ pin while a "0" level is input tothe RESET pin. If this "0" level is kept appliedto the RESET pin until oscillationbecome stable, the CPU will be reset andwill start executing froinaddress o. Thetiming chart IS outlined in Fig. 4-5.(2) Use of the INT pin during external interruptenabled status (I.e. following execl)tion ofEN I instruction)o The clock generator is activated and theCPU started up when a "1" level is appliedto the VDD pin while a "0" level is applied tothe INT pin.If this "0" level is maintained until at least 2ALE output signals occur, an external interruptis generated, and execution starts fromaddress 3. . .However, if the power-down mode is startedduring an interrupt processing routine, exe­~ution will be continued on the next instructionafter the present instruction. The timingchart is outlined in Fig. 4-6.(3) Use of the TNT pin during external interruptdisabled mode (I.e. following execution ofDIS I'instruction or hardware reset)o The clock generator is activated and theCPU started up when a "1" level is appliedto the VDD pin while a "0" level is applied tothe INT pin. If this "0" level is maintaineduntil at least 2 ALE output signals occur, ex­I\lcution is continued on the next instructionafter the present instruction. The timingchart is outlined in Fig. 4-6.(4) - Use of VDD pin onlyo The clock generator is activated and theCPU started up when a "1." level is appliedto the VDD pin while a "1" level.1§.. also appliedto both the RESET and INT pins. Inthis case, execution is resumed from thestopped position. The timing chart is outlinedin Fig. 4-7.270

----------------e. MSM80C35/48, 80C39/49, 80C40/50 •Table 4-3 Details of Pin Status during Hardware Power-Down ModePin No.Pin NameNormal OperationPower Down Mode(VDD = "1 " level)(VDD = "0" level)lP TO Active Floating if output enabled2P XTALl Active Active3P XTAL2 Active Active4P RESET Active Active5P SS 200 to 500 kO pullup 20 to 50 kO pulldown6P INT Active Active7P EA Active Active8P RD Active Floating9P PSEN ,Active FloatinglOP WR Active Floating11 P ALE Active Floating12P DBO Active Floating13P DBl Active Floating14P DB2 Active Floating15P DB3 Active Floating16P DB4 Active Floating17P DB5 Active Floating18P DB6 Active Floating19P DB7 Active Floating20P VSS o [V] o [V]21P P20 Active Floating22P P21 Active Floating23P P22 Active Floating24P P23 Active Floating25P PROG Active Floating26P VDD "1 "level "O"level27P Pl0 Active Floating28P Pll Active Floating29P P12 Active Floating30P P13 Active Floating31P P14 Active Floating32P P15 Active Floating33P P16 Active Floating34P P17 Active Floating35P P24 Active Floating36P P25 Active Floating37P P26 Active Floating38P P27 Active Floating39P Tl Active Active40P Vee +2 to +6 [V] +2 to +6 [V]271

eMSM80C3S/48, 80C39/49, 80C40/S0 e--------------DX'tal 1 ·2ALECPU MODEX'tal 1 ·2VDDI M1. or M2 M1: T1 i T2: T~i fI T4~ ~r----llillL1~:: I IFLOA~TING :O I I I I I I II , I ,I I~RUN-W...STOP~., I I II ' I I IOSC I ;, I ,-t-tRU~---t--l-STOP{!-tEV.OKk I RUN I II I I 1___ I I I 'I I II I I rt RESET pin must be held! : ! : l~~:;~~t:~~e~~~~~!~e: : : : III normal I I I . II I I I I Ir I I I I I Il' ~Ny)ll I ,I I Ii I I I Io ~9ffi2J?a I If __ L ___ "':--'--i-...j_J_LL_L~_+_+_~_L11 i I~~' I I I iii I I I I I II I : odr~ I I I I I, I r I I I I0-1.-"'1"-.,.- - I I I .,..--r--I.-"'1"--t--..,..-+-I I r' I I I I I I I I I I I I1 I I I I I I I I I I I I I Io I I I I RESET EXECUTE I I ISS 200-500KnSS 200-500Kn PULLUPPULLUPSS 20-50Kn PULLDOWN* Cancellation Condition: Use RESET pin.Fig.4-5 Hardware Power-Down Mode Timing ChartX'talALECPU MODEX'tal 1 ·2iT1 , T2 i ni II T4~~~JlL1: :: :FLOA~O~I.,----lRUN-i+STOPS+-1 ~:~--tl-+---r-;--i-+HRu~-{-I-STOP{1~e~K·;'\§"-tI-+-~-..l---+-When a 0.47 I'F ca~acitor is 50- r-:connected to the ss- pin, 60ms50-60 ms wait. WAITI II I I1 IJn ..... ~o ~~yl~1 I II I Io -1--"'1" -~--"'~...,,"""~---....;..-+---+-........--i.......J1..:.1_+......J~-;0-'SS 200-500Kn -t:=::;===1-PULLUPSS 20-50Kn PULLDOWN* Cancellation Condition: Use the I NT pin.500KO PULLUPFig.4-6 Hardware Power-Down Mode Timing Chart272

---------------e. MSM80C3S/48, 80C39/49, 80C40/S0 •X'talALEVDDI.1.: ,Tl: T2: T3: If T41 nnnnnnnnnn II 11/o IpUUrUU~UU~fI tjlJJf:1 I I I FLOATIN~0; i I rj\--If--( I+---T---ti; . I ICPU MODE i--1RU~~STOP~~S-rI~!--~~--T--;-1X'tall ·2 4--4RUN~STOP~OSCEVOKERUIN-;--4-~--4-~--;-I I I! I I I IWhen a 0.47 I'F c~citor is -150- I-- IIconnected to the ss- pin, 60 ms : I50-60 ms wait. WAIT f I : :I I 1 I I 1 I 1 1 I I : Iii : Iii i II i I1 I 1 1 1 I 1 I I 1 . I Io f2Q

....,.r:. ""H0L0000100012o 0 1 0300 1 14o 1 00501 016o 1 1 07o 1 1 181 00091 001A1 01 0B1 01 1C1 1 0001 1 01E1 1 1 0F11110o 0 0 0NOPXCHA@,ROXCHDA,@ROORLA,@I'!OANLA,@ROADDA,@ROADDCA,@ROMOVXA,@ROMOVX@RO,AMOV@RO,AMOV@RO#dataDEC@ROAddedXRLA,@RODJNZ@ROAddedMOVA,@RO1 2000 1 00 1 0HALTAddedOUTLBUSAINC@,RO INC@,Rl JBOaddrXCHA@,RlXCHDA,@RlORLA,@RlANLA,@RlADDA,@RlADDCA,@RlMOVXA,@RlMOVX@Rl,AMOV@Rl,AMOV@Rl,#dataDEC@RlAddedXRLA,@RlDJNZ@RlAddedMOVA,@RlJBl addrMOVA, TJB2addrMOVT,AJB3addrHLTSAddedJB4addrFLTAddedJB5addrJ86addrFRESAdded~MSM80C48/MSM80C49/MSM80C50 INSTRUCTION TABLE3 4 5 6 7 8 9 A B00 1 1 o 1 0 0 o 1 0 1 o 1 1 0 01 1 1 1 000 1 00 1 1 0 1 0 1 01 1MOVP1,@JB7 addrR3AddedADDA, JMP ENI DECA INS A, BUS INA,Pl INA,P2# dataADDCA, CALL DISI JTFaddr INCA INC.Rr# dataMOVA, JMP EN TCNTI JNTO addr CLRA XCHA,Rr# dataCALL DIS TCNTI JTO addr CPLA OUTLP1, OUTLP2,A AORLA, JMP STRTCNT JNTl addr SWAP A ORLA,Rr#dalaANLA, CALL STRTT JT1 addr DAA ANLA,Rr# dataMOVA,PlAddedJMPSTOPTCNTRRCAADDA,RrMOVA,P2Added CALL ENTOCLK JFl addr RRA ADDCA, RrORLBUS, ORLP1, ORLP2,RET JMP CLRFO JNl addr #.data # data # dataANLBUS, ANLP1, ANLP2,RETR CALL CLRFO JNZaddr CLRC # data # data # dataMOVPA.@A JMP CLRFl CPLC MOVRr,AMOVR,JMPP@A CALL CPLFl JFDaddr #dataFLTT MOVP1 P,@Added R3AddedXRLA,#dataMOVP3A,@AJMP SELRBO JZaddrCALLSELRBlMOVA,PSWDECRrMOVPSWA XRLA,RrJMP SELMBO .JNCaddr RLA DJNZRrCALLSELMBl JCaddr RLCA MDVA,RrC 01 1 00 1 1 0 1MOVDA,PpMOVDPp,AORLDPp,AANLDPp,AE F •1 1 1 0 11113:(I)3:g(,)...... c.n~gn(,)CO......~(1)on~......c.no•

--------------_e MSM80C35/48, 80C39/49, 80C40/50 eEXPLANATION OF INSTRUCTION SYMBOLSSymbols are listed below.A AccumulatorAC Auxiliary carryaddr 12-bit program memory address orBbits partBit indicator (b = 0 - 7)BSBUSCClKCNTDBank switchBUS PORTCarryClockCounter4-bit datadataDBFFO,F1Ia-bit numerical valueMemory data bank flip-flopFO flag and F1 flagInterruptPCPpPSWRrSPTTFTO, T1X#@(X)((X))Program counterPort indicator (p = 4 -7)Program status wordResister indicator (r = 0 - 7)Stack pointerTimerTimer flagTest pins TO and T1External RAMSymbol denoting immediate dataSymbol denoting indirect address'Denotes contents of XDenotes contents addressed by XTransferenceLIST OF INSTRUCTIONSMnemonicInstruction CodeD7 D. D. D. D, D,ADDA.Rr 0 1 1 0 1 r,ADDA,@Rr 0 1 1 0 0 0ADDA.#data0 0 0 0 0 0d7 d. d. d. d, d,ADDCA.Rr 0 1 1 1 1 r,ADDCA,@Rr 0 1 1 1 0 0ADDC A, #data0 0 0 1 0 0d7 d. d. d. d, d,ANLA.Rr 0 1 0 1 1ANLA.@Rr 0 1 0 1 0 0'" c::§0 1 0 1 0 00 ANLA, #datad7 d. d. d. d, d,~.S; ORLA,Rr 0 1 0 0 1 r,c:.2 ORLA,@Rr 0 1 0 0 0 0~"c.0 1 0 0 0 00 ORLA. #data d, d. d. d. d, d,.9 .,:; XRLA.Rr 1 1 0 1 1E"XRLA, @Rr 1 1 0 1 0 0"00« 1 1 0 1 0 0XRLA, #data d, d. d. d. d, d,INCA 0 0 0 1 0 1DEC A 0 0 0 0 0 1CLRA 0 0 1 0 0 1CPLA 0 0 1 1 0 1DAA 0 1 0 1 0 1"D, Dor, ro0 ro1 1d, dor, ro0 ro1 1d, dor, ro0 ro1 1d, do" ro0 ro1 1d, dor, ro0 ro1 1d, do1 11 11 11 11 1ClassificationHexadecimal68-6F 160-61 103Byte 2Byte Cycle278-7F 170-71 113Byte 2258-SF 150-51 153Byte 2248-4F 140-41 143Byte 22D8-DF 1DO-Dl 1D3Byte 2217 107 127 137 157 1Description1 (AC), (C). (A) - (A) + (Rr)1 (AC), (C), (A) - (A) + «Rr»2 (AC). (C). (A) -(A) + data1 (AC). (C). (A) - (A) + (Rr) + (C)1 (AC). (C). (A) - (A) + «Rr)) + (C)2 (AC). (C). (A) - (A) + data + (C)1 (A) - (A) AND (Rr)1 (A) - (A) AND ((Rr))2 (A) - (A) AND data1 (A) - (A) OR (Rr)1 (A) - (A) OR «Rr))2 (A) - (A) OR data1 (A) - (A) XOR (Rr)1 (A) -(A) XOR «Rr))2 (A) - (A) XOR data1 (A)-(A)+11 (A)-(A)-11 (A)-O1 (A)-(A)1Add 6 to bits 0 - 3 when contents ofaccumulator bits 0 - 3 exceed 9 orwhen auxiliary carry (AC) is 1. Thenadd 6 to bits 4 - 7 when the result ofadding the carry from the lower 0 - 3exceeds 9, or when carry (C) is 1.Set 1 in the carry flag if an overflowis generated in the end result, orwhenthe carry prior to adjustment is 1.275

• MSM80C35/48, 80C39/49, 80C40/50 .--------------LIST OF INSTRUCTIONS (CONT.)Hexa-decimalClasslficatlonMnemonicInstruction CodeDr D. D. D. D. D. 0, DoByte CycleDescriptionSWAP A 0 1 0 0 0 1 1 1 47 1 1 (A.~r) ::;(Ao-./'"CRLA 1 1 1 0 0 1 1 1 E7 1 1 q A, A. AS A. A3 A2 AI Aof-J~Rotata accumulator contents to the~left by 1 bit ..5CRLCA 1 1 1 1 0 1 1 1 F7 1 1L@-j A, A. As A. A3 A2 AI AoP~ ..Rotate accumulator contents withc.carrytothe left by 1 bit.0~ RRA 0 1 1 1 0 1 1 1 77 1 1 qA' A. As A. A3 A2 AI AoP:;ERotate accumulator contents to theright by 1 bit." u«RRCAl..@-I A, A. AtA. A3 A2 AI AoP0 1 1 0 0 1 1 1 67 1 1Rotate eccumulator contents withcarrytothe right by 1 bit.,INA,Pl 0 0 0 0 1 0 0 1 09 1 2 (A) -(P1)INA,P2 0 0 0 0 1 0 1 0 OA 1 2 (A) -(P2)OUTLP1,A 0 0 1 1 1 0 0 1 39 1 2 (Pl) -(A)OUTLP2,A 0 0 1 1 1 0 1 0 3A 1 2 (P2) -(A)ANL Pl, #dataANL P2, #data1 0 0 1 '1 0 0 1 99dr d. d. ·d. d. d. d, do Byte 21 0 0 1 1 0 1 0 9Adr d. d. d. do d, d, do Byte 22 2 (Pl) -(Pl)ANDdata2 2 (P2) - (P2) AND data1 0 0 0 1 0 0 1 S9ORL Pl, #data2 2 (Pll-(Pl)ORdataC'" dr d. d. d. d, d, d, do Byte 2~1 0 0 0 1 0 1 0 . SAORL P2, #datadr d. d. d. d, d, d, do Byte 22 2 (P2) - (P2) OR data~.5INSA,BUS 0 0 0 0 1 0 0 0 OS 1 2 (A) -(BUS)'5% OUTLBUS,A 0 0 0 0 0 0 1 0 02 1 2 (BUS) -(A)g" c. ANL BUS, #data.5ORL BUS, #data1 0 0 1 1 0 0 0 9Sdr d. d. d. do d. d, do Byte2 .1 0 0 0 1 0 0 0 SSdr d. d. d. do d. d, do Byta22 2 (BUS) - (BUS) AND data2 2 (BUS) - (BUS) OR data .MOVDA,Pp 0 0 0 0 1 1 p, Po OC-OF 1 2 (Ao-:o) -(Pp) p=4-7(A.-r)-OMOVDPp,A 0 0 1 1 1 1 p, Po 3C-3F 1 2 (Pp) -(Ao-:o) p=4-7ANLDPp,A 1 0 0 1 1 1 p, Po 9C-9F 1 2 (Pp) -(Pp) AND (Ao-:o) p=4-7ORLDPp,A 1 0 0 0 1 1 p, Po SC-SF 1 2 (Pp) -(Pp) OR (Ao-:o) p=4-7r, ro lS-lF 1 1 (Rr) -(Rr)+lS lS,§ INC@Rr 0 0 0 1 0 0 0 ro 10-11 1 1 «Rr)) -«Rr)) + 1leg1D &lo DECRr 1 1 0 0 1 r, r, ro CS-CF 1 1 (Rr) "-(Rr)-lIX: o.~DEC@Rr 1 1 0 0 0 0 0 ro CO-Cl 1 1 «Rr)) - «Rr)) - 1'" INCRr 0 0 0 1 1 "~g (PC.-,.,) -addrS-l0.c= JMPaddr alO a. a • 0 0 1 0 0 q,4-E4 2 2 (PCo-r) -addrO-7UU ar a. a. a. ao a, a, 80 Byte 2 (PCI1)-DBFcEl!",CD.S JMPP@A 1 0 1 1 0 0 1 1 B3 1 2 (PCo-r) -«A»276

--------------'. MSM80C35/48, 80C39/49, 80C40/50 •LIST OF INSTRUCTIONS (CONT.)ClassificationMnemonicInstruction CodeHexa-07 De Os D. 03 0, 0, DodecimalByte CycleDescripti9"DJNZ Rr. addr(Rr)1 1 1 0 1 r, r,-(Rr)-1ro E8-EF2 2 (PCO-7) -addrif(Rr) =0a7 ae as a. a3 a, a. aoByte 2 (PC) -(PC) + 2 if (Rr) =0DJNZ @Rr. addr«Rr)) -«Rr»-11 1 1 0 0 0 0 ro EO-E12 2 (PCO-7) -addrif «Rr» =0a7 ae as a. a3 a, a. ao Byte 2 (PC) -(PC) + 2 if «Rr» = 0JCaddr1 1 1 1 0 1 1 0 F6(PCO-7) -addr ifC=1a7 ae as a. a3 a, a. ao Byte 22 2 (PC) -(PC) +2 ifC =0JNCaddrJZaddr1 1 1 0 0 1 1 0 E6(PCO-7) -addr ifC=O87 ae as a. a3 a, a. ao Byte 22 2 (PC) -(PC) +2ifC=11 1 0 0 0 1 1 0 C6(PCO-7) -addr ifA=Oa7 ae as a. a3 a, a. ao Byte 22 2 (PC) -(PC) + 2 if A",O1 0 0 1 0 1 1 0JNZaddr96(PCO-7) -addr ifA",O2 2"' ea7 ae as a. a3 a, a, ao Byte 2 (PC) -(PC) +2 ifA=O.2'0 0 0 1 1 0 1 1 0 36 (PCO-7) -addr ifTO=1JTOaddr 2 2~ " a7 a. as a. a, a, a. ao Byte 2 (PC) -(PC) +2 ifTO=O.!:a0 0 1 0 0 1 1 0 26 (PCO-7) -addr ifTO=Oe JNTOaddra7 ae a5 a. a, a, a. ao Byte 22 2 (PC) -(PC) +2 ifTO=1:E00 1 0 1 0 1 1 0 56 (PCO-7) -addr ifT1 = 1e JT1 addra7 ae as a. a3 a, a. ao Byte 22 2ID(PC) -(PC)+2ifT1 =0JNT1 addrJFOaddrJF1 addr0 1 a 0 a 1 1 0 46(PCO-7) -addr ifT1 =0a7 ae as a. a3 a, a. ao Byte 22 2 (PC) -(PC)+ 2 ifT1 = 11 0 1 1 0 1 1 a B6(PCO-7) -addr ifFO=1a7 ae as a. a3 a, a. ao Byte 22 2(PC) -(PC) +2ifFO=O0 1 1 1 0 1 1 0 76(PCO-7) -addr ifF1 =1a7 a, as a. a3 a, a. ao Byte 22 2 (PC) -(PC)+2ifF1 =0(PCO-7)0 0 0 1 0 1 1 0 16-addr}JTFaddr 2 2 TF -0 ifTF=1a7 ae as a. a, a, a. ao Byte 2(PC) -(PC) +2ifTF=0JNI addrJBbaddr1 0 0 0 0 1 1 0 86(PCO-7) -addr if INT = 0a72 28, as a. a, a, a, ao Byte 2 (PC) -(PC) +2 if INT =1b, b. bo 1 0 0 1 0 12-F2(PCO-7) -addr ifBb=1a7 a, as a. a, a, a. ao Byte 22 2 (PC) -(PC)+2 if Bb =0«SP» -(PC) + 2. (PSW.--)(PCe-,-lO) -addr8-10CALLaddralO a. a. 1 0 1 0 0 14-F4 2 2 (PCo--) -addrO-7Q)", 87 ae as a. a, a, a. ao Byte 2 (PC ..) -DBFee~o(SP) -(SP)+1::::J+:00.6.5(SP) -(SP)-1,,", RET 1 0 0 0 0 0 1 1 83 1 2 (PC) -«SP»w.E(SP) -(SP)-1RETR 1 0 0 1 0 0 1 1 93 1 2 (PC) -«SP»(PSW'-7) -«SP» INT ENDCLRC 1 0 0 1 0 1 1 1 97 1 1 (C) -0e CPLC 1 0 1 0 0 1 1 1 A7 1 1 (C) -(C)0"':;gCLRFO 1 a 0 0 0 1 0 1 85 1 1 (FO) -08.~0'; CPLFO 1 0 0 1 0 1 0 1 95 1 1 (FO) -

• MSM80C35/48, 80C39/49, 80C40/50 ,••--------------LIST OF. INSTRUCTIONS (CONT.).,eMnemonicInstruction Code0, De O. O. D. D. D. DoMOVRr,A 1 0 1 0 1" "Byte Cyclero A8-AF 1 1 (Rr) -(AIMOV@Rr,A 1 0 1 0 0 0 0 ro AO-Al 1 1 ((Rr)) --(A)MOV Rr, #dataMOV @Rr, #data1 0 1 1 1 r.d, de d. d. d. d. d. " ro B8-SF. 2 2 (Rr)do Byte 2-dais1 0 1 1 0 0 0 ro BO-Bld, d. d. d. d3 d. d. do Byte 22 2 ((Rr)) -dataMOVA,PSW 1 1 0 0 0 1 1 1 C7 1 1 (AI --(PSW)MOVPSW;A 1 1 0 1 0 1 1 1 07 1 1 (PSW) -(AIDescription~ XCHA,Rr 0 0 1 0 1 r. r. ro 28-2F 1 1 (AI !:;(Rr)~.5 XCHA,@Rr 0 0 1 0 0 0 0 ro 20-21 1 1 (AI !:;I(Rr))-!l XCHOA,@Rr 0 0 1 1 0 0 0 ro 30-31 1 1 (Ao-.)!:;((Rro-.))ejg MOVXA,@Rr 1 0 0 0 0 0 0 ro 80-81 1 2 (A) -((Rr)) External RAMS..c MOVX@Rr,A 1 0 0 1 0 0 0 ro 90-91 1 2 ((Rr)) -(A) External RAMII>e~~MOVPA,@A 1 0 1 0 0 0 1 1 A3 1 2 (A) -((PCe-Io,A))MOVP3A,@A 1 1 1 0 0 0 1 1 E3 1 2 (A) --«PCOII, A))MOVPl P,@R3 1 1 0 0 0 0 1 1 C3 1 2 (PI) --«((PCo-,)-((R3)) IIMOV Pl,@R3 1 1 1 1 0 0 1 1 F3 1 2 (PI) -((R3))MOVA,Pl 0 1 1 0 0 0 1 1 63 1 1 (A) -(PI) Latch dataMOVA,P2 0 1 1 1 0 0 1 1 73 1 1 (A) --(P2) Latch dataEN TCNTI 0 0 1 0 0 1 0 1 25 1 1 TINT Enable FIF-lDIS TCNTI 0 0 1 1 0 1 0 1 35 1 1 TINT Enable F/F-oENI 0 0 0 0 0 1 0 1 05 1 1 EXINT Enable F/F-lOISI 0 0 0 1 0 1 0 1 15 1 1 EXINT Enable F/F-oSELRBO 1 1 0 0 0 1 0 1 C5 1 1 (BS) -0SELRBI 1 1 0 1 0 1 0 1 05 1 1 (Bs) -1SELMBO 1 1 1 0 0 1 0 1 E5 1 1 (OBF) -0.5 SELMBI 1 1 1 1 0 1 0 1 F5 1 1 (OBF) -1gea0SII>eliENTOCLK 0 1 1 1 0 1 0 1 75 1 1 TO -1/3XTAL 1FLT 1 0 1 0 0 0 1 0 A2 1 1 PI, P2, BUS FloatingFLIT 1 1 0 0 0 0 1 0 C2 1 1 CPU Output Signal FloatingFRES 1 1 1 0 0 .0 1 0 E2 1 1 FLT,FLITRESETHLT 0 0 0 0 0 0 0 1 01 1 1 CPU Control Clock StopHALTS 1 0 0 0 0 0 1 0 82 1 1 XTAL 1'2 StopMOVA,T 0 1 0 0 0 0 1 0 42 1 1 (A) -(T)MOVT,A 0 1 1 0 0 0 1 0 62 1 1 (T) --(A)8'5 STRTT 0 1 0 1 0 1 0 1 55 1 1 (T)~2-~-XTALHexa-decimalClasslfication,,-E~ STRTCNT 0 1 0 0 0 1 0 1 45 1 1 (T)j::'--T1ClockSTOP TCNT 0 1 1 0 0 1 0 1 65 1 1 (T) Count Stop","e ~" NOP' 0 0 0 0 0 0 0 0 00 \ 1 1 (PC) --(PC) + 15j~278

-----,..----------e MSM80C35/48, 80C39/49, 80C40/50 •ABSOLUTE MAXIMUM RATINGSParameter Symbol Conditions Limits UnitSupply Voltage VCC Ta=25°C -0.3 to 7 ·VInput Voltage VI Ta=25°C -0.3toVCC VStorage Temperature Tstg -55to+150 °cOPERATING RANGEParameter Symbol Conditions Limits UnitSupply Voltage VCC lose = DC-11 MHz' +2.5 to +6 VRAM Retention Voltage VCC +2 to +6 VAmbient Temperature TA -40 to +85 °cFan OutNMOSload 10TTL load 111 MHz version 01 MSM80C50 (6 MHz < XTAL1.2 < 11 MHz) is under development.279

• MSM80C3S/48, 80C39/49, 80C40/S0 .-..,...------------­DC ELECTRICAL CHARACTERISTICS(Vee = 5V±1 0%, Ta = -40 to +85°e)Parameter Symbol Conditions"L" Input Voltage"H" Input Voltage (1)"H" Input Voltage (2)VILVIHVIH"L" Output Voltage (3) VOL IOL=2mA"L" Output Voltage (4) VOL 10L =1.6mA"H" Output Voltage (3) VOH IOH=400/LA"H" Output Voltage (4) VOH IOH=50/LA"H" Output Voltage (3) VOH IOH=20/LA"H" Output Voltage (4) VOH 10H = 10/LAInput Leak Current IlL VSS'S. VIN'S. VCCOutput Leak Current (5) 10L VSS'S. VO'S. VCCRESET Pull up RR VIN~ VIH'S./Resistance VIN;;;VIL -SS Pull up Resistance RSS Oscillation(6) stop/oscillationP1, P2 Pull up Rp1, P2 VIN~VIH/ResistanceVIN;;;VILAt hardware powerdownVCC=2V(TA = +25°C) (7)Min. Typ. Max. Unit-0.3 0.8 V2.2 VCC V3.8 Vec V0.45 VMeas,uringCircuit0.45 V 12.4 V2.4 V4.2 V4.2 V±10 /LA 2±10 /LA 320/500 50/750 kO20/200 50/500 kO5/75 15/150 kO 31 10 /LA2At HL TS execution'VCC=2V(TA = +25°C) (7)Power Supply Current ICC At HALT (6 MHz)At HALT (11 MHz)Atexecution(6 MHz)At execution(11 MHz)1 10 /LA1.5 3 mA2.5 5 mA5 10 mA10 20 mA4Notes: (1) This does not apply to RESET, XTAL 1, XTAL2, and VDD.(2) RESET, XTAL 1, XTAL2, VDD(3) BUS, RD, WR, PSEN, ALE(4) Other outputs(5) High-impedance state(6) This operates as a pull-down resistor when the oscillation is stopped in the HLTS or hardware power-downmode and as a pull-up resistor in other states.(7) This does not contain flow out current from I/O Ports and Signal pins.280

--------------. MSM80C35/48, 80C39/49, 80C40/50 •AC CHARACTERISTICS(Vee = 5V±1 0%, TA = -40 o e to +85°e)LimitsParameter Symbol 11 MHz Clock Variable Clock (0 - 11 MHz) UnitMin. Max. Min. Max.CycleTime tCY 1.36 1.36 ,",SALE Pulse Width tLL 150 7/3OtCy-165 nsAddress Set up ALE tAL 70 2/15tCy-110 nsAddress Hold from ALE tLA 50 1/15tCy-40 nsBus Port Latch Data Setup tBL 110 5/30tCy-115 nsto ALEBus Port Latch Data Holdfrom ALEControl Pulse Width(PSEN, RD, and WR)tLB90 3/3OtCy-45 nstcc 300 6/15tCy-245 nsData Setup before WR tow 250 6/15tCy-295 nsData Hold after WR two 40 2/15tCy-140 nsData Hold after RD tDR 0 100 0 100 nsPSEN, RD to Data-in tRD 200 5/15tCy-250 nsAddress Setup to WR tAW 200 6/15tCy-345 nsAddress Setup to Data-in tAD 400 8/15tCy-325 nsAddress Float to RD, PSEN tAFC 0 0 nsPort Control Setup to PROG tcp 100 2/15tCy-80 nsPort Control Hold from PROG tpc 60 4/15tCy-300 nsPROG toP21nputVaiid tpR - 650 9/15tCy-165 nsOutput Data Setup top 200 6/15tCy-345 nsOutput Data Hold tpD 20 3/15tCy-250 nsInput Data Hold from PROG tpF 0 150 0 150 nsPROG Pulse Width tpp 700 10/15tCy-205 nsPort 21/0 Setup to ALE tpL 150 9/30tCy-255 nsPort 21/0 Hold from ALE tLP 20 3/30tCy-115 nsNote: Control output:Bus output:CL =80 pFCL = 150 pF [for 20 pF (tWO)]281

• MSM80C3S/48, 80C39/49, 80C40/S0 •• -------------­MSM80C49 OPERATION GUARANTEE RANGETa = -40 to +85°eI I·IIIIIII I I100 I I(jJ sec)Operation Guarantee Range1 .. 10 -1.5MHzEi=.."\,u>-\()-3MHz" ~\\ MSM80C40/50·I'..--' 6MHz1" " - 11 MHz2 3 4 5 6 (VISupplV Voltage (Veel·11 MHz version of MSM80C40/50 is underdevelopment282

----------------'. MSM80C35/48, 80C39/49, 80C40/50 •TIMING CHARTInstruction Fetch (from external program memory)~-------------tCY------------~ALEtAFCBUSRead (from external data memory)ALEt----tcc------tBUS283

• MSM80C35/48, 80C39/49, 80C40/50 ... --------------Write (to external memory)ALEJ..---tcc----IBUSII4 low-order bits InpuVoutput of port 2 when expanded I/O is used(in external program memory access mode)P26-3(OutputmodelPCHP20-3(Inputmode)PCH284

---------------e. MSM80C35/48, 80C39/49, 80C40/50 •MEASUREMENT CIRCUIT2~~VIHI-l-::J::JI>.(3) I>. l-~ ::J0VILGND=- =- =- J(1 )I-::JI-::JI>.1=~ ::J0-3 4Notes: (1) This is repeated for each specified input pin.(2) This is repeated for each specified output pin.(3) Input logic for setting the specified state.285

OKI 5en1iconductorMSM80C31 F/MSM80C51 FCMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLERGENERAL DESCRIPTIONThe OKI MSM80C31 F/MSM80C51 F microcontroller is a low power, high performance 8-bit singlecomponent device implemented in OKl'ssilicon gate complementary metalloxide semiconductorprocess technology. Integrated within the device is 4K bytes of mask programmable ROM(MSM80C51 F only), 128 bytes of data RAM, 32 I/O lines, two 16-bit timer/counters, a five-sourcetwo-level interrupt structure, a full duplex serial port, and an on chip oscillator and clock circuitry. Inaddition, the device has two software selectable modes for further power reduction - Idle and PowerDown. Idle mode freezes the CPU's instruction execution while maintaining RAM and allowing thetimers, serial port and interrupt system to continue functioning. Power Down mode saves the RAMcontents but freezes the oscillator causing all other device functions to be inoperative.FEATURES• Operating temperature: -40 - +85°C• Operating frequency: 0.5 - 16 MHz• CMOS technology, 2fLm Silicon gate• Minimum instruction cycle:1.0fLS (@ 12MHz, Vcc = 5V±20%)0.75fLS (@ 16MHz, Vcc = 5V±1.0%)• Low power consumption:Normal Operation 16 mA @ 5V, 12MHzIdle Mode3.7 mA @ 5V, 12MHzPower Down Mode 50fLA @ 2V• Instruction set includes 111 instructions• 8-bit CPU• On chip oscillator and clock circuitry• 32 Input/Output lines• 4069 x 8 bits on chip ROM (MSM80C51 F)• 128 x 8 bits on chip RAM• 64K address space for program memory• 64K address space for external data memory• Two 16-bit timer/counters• Five source two-priority level interruptstructure• Full duplex serial port• Boolean processor• CMOS and TTL compatible• CMOS ROM LESS development device(MSM80C31 F)DIFFERENCES BETWEEN MSM80C31 F/MSM80C51 F ANDMSM80C31lMSM80C51• Operating frequency. 0.5 -16 MHz ............. MSM80C31 F/MSM80C51 F0.5 -12 MHz ............. MSM80C31/MSM80C51• External clock inputterminalXTAL1 .................... MSM80C31F/MSM80C51FXTAL2 .................... MSM80C31/MSM80C51• Emulation modeOutput impedance of ALE and PSEN pins becomes about 20kfl while CPU is being reset inMSM80C31 F/MSM80C51 F.Any other functions and electrical characteristics of MSM80C31 F/MSM80C51 F except for the abovethree differences are the same as those of MSM80C31 /MSM80C51.286

P20 -POO -P27P07XTAL1 ---1--XTAL2ALEPffiiRESETr -"'-"-L..-_-_==~___-_~_-_-_-_~~:~.- ----------------CONTROL SIGNALS~ NI =iE SE9~ 0 ~M I ~i I n II ~ 14096 WORDQo I . I I I I I __.. I I I I _. I I C~II:~EA -I ~::l...II:Q.8 BITRIW SIGNALS~...J....,ll."CZ(')::::!oz)10r­mr­o(')ii"C:;Ci)::II)10s:::I\.l00-..JP30 -P37S~.!U~L~ _ ..JL _____________________ ~s::tns::CI)oo(0).....=!!CI)oo(II....."TI•;

• MSMSOC31F/SOC51F •• -----------------------------------------PIN CONFIGURATIONMSM80C51 F-XXRS/MSM80C31 FRS(Top View) 40-Lead Plastic DIPMSM80C51 F-XXGSK/MSM80C31 FGSK(Top View) 44-Lead Plastic Flat PackagePl.0Pl.tPl.2P1.3Pl.4Pl.SPl.&Pl.7RESETRXDIP3.0TXDIP3.1iN'i'O/P3 .2INTt/P3.3TO/P3.4Tl/P3.5WR1P3.6RO/P3.7XTAL2XTALIVSSveePO.O/ADOPO. l/AD 1PO.2/AD2PO.3/AD3PO.4/AD4PO.5/AD5PO.6/AD6PO.7/AD7EAALEPffiiP2.7/A15P2.&/A14P2.5/A13P2.4/A12P2.3/AllP2.2/Al0P2.1/A9P2.0/ABPl.5P1.6Pt.7RESETNCRXD/P3.0TXD/P3.1T;:;'i'O/P3.2tm1/P3.3TO/P3.4Tl/P3.5PO.4/AD4PO.5/AD5PO.6/AD6PO.7/AD7EAALEPSENNCP2.71AD15P2.6/AD14P2.5/AD13MSM80C51 F-XXJS/MSM80C31 FJS(Top View) 44 Lead Plastic Leaded Chip CarrierP1.5P1.6Pl.7:rJ:~]-9~RESET fei]P3.0/RXO tfJNC [~JP3.l/TXD r:f~P3.2/INTO E]P3.3/iNT1 l~]P3.4/TO I~]l~! L5J ~J l3J ~J Ll1 t~ ~~ t~ ~~ ~So~~coco0000"'01~~ P.04[58 PO.~[¥t PO.6[~ PO.7[~~ EA[q{ NCC:P: ALE[if PSEN[E P2.7[@ P2.6P3.5/T1 {fJ [~ P2.5..., .... ,.., ,., ,.., ,., ,., r, r, ,., r.,lH~ .1~ l2cr :111) 12~ ;2~ ~~ ?~ ?~ :2~ :2~288

-----------------------------------------eeMSMSOC31F/SOC51F ePIN DESCRIPTIONSDesignationVSSVCCPortaPort 1Port 2Port 3RESETALEPSENEAXTAL1XTAL2Ground potentialDescriptionSupply voltage during Normal, Idle and Power Down operationPort a is an 8-bit open drain bidirectional 1/0 port. It is also the multiplexedlow-order address and data bus during accesses to external memory.Port 1 is an 8-bit bidirectional 1/0 port with internal pullups. It can drive CMOSinputs without external pullups.Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. It receives thehigh-order address byte during accesses to external memory. It can driveCMOS inputs without external pullups.Port 3 is an 8-bit bidirectional 1/0 port with internal pullups. It also serves thefunctions of various special features, as shown below:Port Pin Alternate FucntionP3.0 RXD (serial input port)P3.1 TXD (serial output port)P3.2 INTO (external interrupt)P3.3 INT1 (external interrupt)P3.4 TO (Timer a external input)P3.5 T1 (Timer 1 external input)P3.6 WR (external data memory write strobe)P3.7 RD (external data memory read strobe)It can drive CMOS inputs without external pullups.Reset input pin. A reset is accomplished by holding the RESET pin high for atleast 1 fJ- second, even if the oscillator has been stopped. The CPU respondsby executing an internal reset. An internal pulldown resistor permits Power-Onreset using only a capacitor connected to VCC.This pin does not receive the power down voltage since the function has beentransferred to the VCC pin.Address Latch Enable output for latching the low byte of the address duringaccesses to external memory. For this purpose, ALE is activated twice everymachine cycle or at a constant rate of 116 the oscillator frequency, except. during an external memory access at which time one ALE pulse is skipped. Itcan drive CMOS inputs without an external pullup.Program Store Enable output is the read strobe to external Program Memory.PSEN is activated twice each machine cycle during fetches from externalProgram Memory. (However, when executing out of external Program Memory,two activations of PSEN are skipped during each access to external DataMemory.) PSEN is not activated during fetches from internal Program Memory.It can drive CMOS inputs without an external pullup.External Access input pin. When EA is held high, the CPU executes out ofinternal Program Memory (unless the Program Counter exceeds OFFFH).When EA is held low, the CPU executes only out of external Program Memory.EA must not be floated.Crystal 1 pin. It is an input to the inverting amplifier which forms the internaloscillator. It also receives the external clock signal when an external oscillatoris used. (External clock signal should be at 50% duty and C-MOS level).Crystal 2 pin. It is an output of the inverting amplifier that forms the internaloscillator.289

• MSMSOC31F/SOC51F •• ------------~----~--------------------ELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGS·ItemSupply VoltageVoltage from any Pin to VSSStorage TemperaturePower DissipationSymbolVCCVAPTSTGPOConditions Rating Units-0.5 to +7.0 V-0.5 to VCC +0.5 v.-55 to +150 °C1.0 WOPERATING RANGEItemSupply VoltageRAM Retention VoltageOperating TemperatureSymbolVCCVPDTOPConditions Rating lInits..fosc =0.5 -16 2.5 to +6.0 VMHzPower Down 2.0 to +6.0 V-40 to +85 °C'NOTlCE: Stresses at or above those listed under 'Absolute Maximum Ratings' may cause permanent damage tothe device. This is a stress rating only and functional operation of this device at these or any other conditionsabove those indicated in the operational sections of this specification is not implied. Exposure toabsolute maximum rating conditions may affect device reliability .•• DC and AC characteristics in the range of 12 MHz

-----------------------------------------e. MSMSOC31F/SOC51F •DC CHARACTERISTICS (CONT.)(TA = -40°C to +8S0; vcc = 4 to 6V: vss = OV)Item Symbol Condition Min. Typ. Max. UnitOutput High Voltage VOH1 10H =-40!-,A 0.9VCC - - VPort OOn External Bus Mode), (Note 2)ALE, PSEN10H = -1S0!-,A 0.7SVCC - - V10H = -400!-,A 2.4 - - VLogical 0 Input Current IlL Yin = O.4SV - - -200 !-,APorts 1,2,3Logical 1 To 0 Transition ITL Yin =2.0V - - -SOO !-,ACurrent-Ports 1,2,3Input Leakage Current III VSS

• MSMSOC31F/SOC51F •• ~------~-------------------------------NOTE2: Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the0.9 VCC specification when the address bits are stabilizing.NOTE3: ICC is measured with all output pins disconl)ected; XTAl1 driven with TClCH, TCHCl = 10 ns, Vil = VSS+ 0.5V, VIH = VCC -0,5V; EA = RESET = PORT 0 = VCC.ICC may be higher if a crystal oscillator is used.NOTE4: Idle ICC is measured with all output pins disconnected; XTAl1 driven with TClCH,TCHCl = 10 ns, Vil =VSS +0.5V, VIH =VCC -0.5V; EA =PORTO =VCC·ICC may be higher if a crystal oscillator is used.NOTES: Power Down IpO is measured with all output pins disconnected; EA = PORT 0 = VCC; XTAl2 N.C.; RESET=VSS·DatumEmittingPortsDegradedI/O LinesVOL(peak/max)AddressP2,POP1, P3 0.8VWrite DataPOP1.,P2,P3 0.8VCLOCK PARAMETERSItemOscillator PeriodHigh Timelow TimeRise TimeFall TimeSymbolTClClTCHCXTClCXTCLCHTCHClMin.Variable Clockfreq = 0.5 MHz to 16 MHzMax.62.5 -20 -20 -20- 20UnitnsnsnsnsnsEXTERNAL CLOCK DRIVEXTAL2EXTERNALOSCILLATOR'------I XTAL 1SIGNALvSSTClCHTCHCl'XTAL 1Input to the inverting oscillator amplifier and input to the internal clock generator circuits.'XTAl2Output from the inverting oscillator amplifier.292

-----------------------------------------e. MSMSOC31F/SOC51F •AC CHARACTERISTICS(Top = -40°C to 85°C; vcc = 4V to 6V; vss =OV; 0.5 to 12 MHz; Load Capacitance for Port 0, ALEand PSEN = 1 OOpF; Load Capacitance for all other outputs = 80 pF)EXTERNAL PROGRAM MEMORY CHARACTERISTICSItem Symbol Min. Typ. Max. UnitALE Pulse Width TLHLL 2TCLCL-40 - - nsAddress Valid to ALE Low TAVLL TCLCL-40 - - nsAddress Hold after ALE Low TLLAX TCLCL-35 - - nsALE Low to Valid Instr.ln TLLlV - - 4TCLCL-100 nsALE Low to PSEN Low TLLPL TCLCL-25 - - nsPSEN Pulse Width TPLPH 3TCLCL-35 - - nsPSEN Low to Valid Instr. In TPLIV - - 3TCLCL-105 nsInput Instr. Hold after PSEN TPXIX 0 - - nsInput Instr. Float after PSEN TPXIZ - - TCLCL-20 nsPSEN to Address Valid TPXAV TCLCL-8 - - nsAddress to Valid Instr. In TAVIV - - 5TCLCL-105 nsPSEN Low to Address Float TPLAZ - - 0 nsEXTERNAL DATA MEMORY CHARACTERISTICSItem Symbol Min. Typ. Max. UnitRD Pulse Width TRLRH 6TCLCL-100 - - nsWR Pulse Width TWLWH 6TCLCL-100 - - nsData Address Hold after ALE Low TLLAX TCLCL-35 - - nsRD Low to Valid Data In TRLDV - - 5TCLCL-165 nsData Hold after RD TRHDX 0 - - nsData Float after RD TRHDZ - - 2TCLCL-70 nsALE Low to Valid Data In TLLDV - - 8TCLCL-150 nsAddress to Valid Data In TAVDV - - 9TCLCL-165 nsALE Low to WR or RD Low TLLWL 3TCLCL-50 - 3TCLCL+50 nsAddress to WR or RD Low TAVWL 4TCLCL-130 - - nsData Valid to WR Transition TQVWX TCLCL-60 - - nsData Valid to WR High TQVWH 7TCLCL-150 - - nsData Hold after WR TWHQX TCLCL-50 - - nsRD Low to Address Float TRLAZ - - 0 nsRD or WR High to ALE High TWHLH TCLCL-40 - TCLCL+40 ns293

• MSM80C31F/80C51 F •• --------------------AC TIMING DIAGRAMSEXTERNAL PROGRAM MEMORY READ CYCLEALEPORTO AO-A7 INSTR INPORT2ADDRESS AS-A15EXTERNAL DATA MEMORY READ CYCLE~----------TLLDV---------~ITWHLH __ALE~---------4-TRLRH--------~~PORTOAD-A7TRLAZDATA INPORT 2ADDRESSOR SFR-P2ADDRESS AS-A15 OR SFR-P2EXTERNAL DATA MEMORY WRITE CYCCLEALETWHLH------~~--------~.TWLWH----------~PORTOPoRT 2ADDRESSOR SFR-P2DATA OUTTQVWH-ADDRESS AS-A 15 OR SFR-P2294

__________________________ ~ ____________ _e. MSM80C31F/SOC51F •AC TESTING INPUT/OUTPUT, FLOAT WAVEFORMSINPUT/OUTPUTFLOAT2.4 2.42.0 2.0 2.0TEST POINTS0.8 0.8 0.80.45 0.45FLOATAC inputs during testing are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Timing measurements aremade at 2.0V for a logic "1" and 0.6V for a logic "0". For timing purposes, the float state is defined as the pointat which a PO pin sinks 3.2 rnA or sources 400ILA at the voltage test levels.SERIAL PORT TIMINGI/O EXPANSION MODE(TA = -40°C to +S5°C; VCC = 4 to 6V; VSS = OV, 0.5 to 12 MHz; Load capacitance = SO pF)Symbol Parameter Min. Max. UnitsTXLXL Serial port clock cycle time 12TCLCL - p,sTQVXH Output data setup to clock rising edge 10TCLCL-133 - nsTXHQX Output data hold after clock rising edge 2TCLCL-117 - nsTXHDX Input data hold after clock rising edge 0 - nsTXHDV Clock rising edge to input data valid - 10TCLCL-133 nsSERIAL PORT (I/O EXPANSION MODE)MACHINE CYCLE I o 3 4 5 6 8I-TXLXL-I-----,CLOCKTQVXH 1-II-TXHQxlOUTPUTOATA----.L----JWRITE ~O SBUFTXHDV -1- I-TXHDXL----ltCLEAR R1295

~I'J (")coen •III6 iii:..» .en(I) (")iii:n ;III;icoi 0I (,)Z m...Ii)CYCLE"'1'1n:!!0 COSTEP % ::D 0»I:en 0...XTALl 1 :II U10 ..ALE 10PSEiii 10RD/WR 101PORT-O 0PORT-210CPU--PORT ~."PORT-CPU ~I ! I ! iii I : IInstruction dec~rding. I Instruction dB

----------~----------------------------_e. MSM80C31F/SOC51F •EXTERNAL PROGRAM MEMORY FETCH----------__ +----------MlorM2--------__ 4-____ _XTALIALEPORTOPORT2READ CYCLE 1 (MOVX A, @Rr)XTAL 1oALEo -i--i0-1--'"PORTOoPORT 2O--__ ~ _____ ~ ____________ ~ ______297

• MSM80C31F/80C51F •• ----------~------------------------~---READ CYCLE 2 (MOVX A, @DPTR)XTAL 10ALE0~0RD0-IIPORTO0PORT 20WRITE CYCLE 1 (MOVX, @Rr, A)XTAL 10ALE0PSEN0WR0-PORTO0PORT 20298

-----------------------------------------eeMSM80C31F/80C51F eWRITE CYCLE 2 (MOVX A, @DPTR, A)--!------Ml------I-------XTAL 10ALE0PSEN0WRo -PORTOPORT 200nPORT OPERATIONMlM2XTAL 1oALE0--1---10-1----11PORT 0,1,2,3,PIN DATACPU DATASAMPLED299

• MSMSOC31F/SOC51F •• -----------------------------------------INSTRUCTION SET DETAILSMnemonicInstruction CodeD7 D. D5 D. D3 D. D, DoHexadecimalByte CycleADDA,Rn 0 0 1 0 1 n. n, no 28-2F 1 1 (A) - (A) + (Rn)ExplanationADD A, direct 0 0 1 0 0 1 0 1 25 2 1 (A) - (A) + (direct)a7 a. as a. a3 a. a, ao Byte 2ADD A, @Ri 0 0 1 0 0 1 1 1 26-27 1 1 (A) - (A) + «Ri))ADDA,#data 0 0 1 0 0 1 0 0 24 2 1 (A) - (A) + #datad7 d. ds d. d3 d. d, do Byte 2ADDCA,Rn 0 0 1 1 1 n. n, nQ 38-3F 1 1 (A) - (A) + (C) + (Rn)ADDC A, direct 0 0 1 1 0 1 0 1 35 2 1 (A) - (A) + (C) + (direct)a7 a. as a. a3 a. a, ao Byte 2ADDCA,@Ri 0 0 1 1 0 1 1 1 36-37 1 1 (A) - (A) + (C) + «Ri»AD DC A, #data 0 0 1 1 0 1 0 0 34 2 1 (A) - (A) + (C) + #datad7 d. ds d. d3 d. d, do Byte 2SUBBA, Rn 1 0 0 1 1 n. n, no 98-9F 1 1 (A) - (A) - «C) + (Rn»)SUBB A, direct 1 0 0 1 0 1 0 1 95 2 1 (A) - (A) - «C) + (direct))a7 a. as a. a3 a. a, ao Byte 2SUBBA,@Ri 1 0 0 1 0 1 1 1 96-97 1 1 (A) - (A) - «C) + «Ril))tilc:0 SUBB A, #data 1 0 0 1 0 1 0 0 94 2 1 (A) -(A) -«C) +#data)~ d7 d. ds d. d3 d. d, do Byte 2Q)a.0 INCA 0 0 0 0 0 1 0 0 04 1 1 (A)-(A)+li "INCRn 0 0 0 0 1 n2 n, no 08-0F 1 1 (Rn) - (Rn) + 1E:5INC direct 0 0 0 0 0 1 0 1 05 2 1 (direct) - (direct) + 1~ a7 a. as a. a3 a2 a, ao Byte 2_ til c:

---------------------------------------e. MSMSOC31F/SOC51F •INSTRUCTION SET DETAILS (CONT.)MnemonicInstruction Code07 D. D. D. D. D. 0, DoHexadecimalByte CycleExplimationANLdirect, A 0 1 0 1 0 0 1 0 52 2 1 (direct) - (direct) AND (Ala7 ae a. a. a. a. a, ao Byte 2ANLdirect, 0 1 a 1 0 0 1 1 53 3 2 (direct) - (direct) AND #data#data a7 ae a. a. a. a. a, ao Byte 2d7 de d. d. d. d. d, do Byte 3ORLA,Rn 0 1 0 0 1 n. n, no 48-4F 1 1 (Al - (A) OR (Rn)ORL A, direct 0 1 a 0 0 1 0 1 45 2 1 (Al - (Al OR (direct)a7 ae a. a. a. a. a, ao Byte 2ORLA,@Ri 0 1 a a a 1 1 1 46-47 1 1 (Al - (Al OR «Ri))ORLA,#data a 1 a 0 0 1 0 0 44 2 1 (Al - (A) OR #datad7 de d. d. d. d. d, do Byte 2ORL direct, A 0 1 a a a 0 1 0 42 2 1 (direct) - (direct) OR (Ala7 ae a. a. a. a. a, ao Byte 2ORLdirect, a 1 a 0 a a 1 1 43 3 2 (direct) - (direct) OR #data#data a7 a. a. a. a. a. a, ao Byte 2d7 de d. d. d. d. d, do Byte 3XRLA,Rn 0 1 1 a 1 n. n, no 68-6F 1 1 (Al - (Al XOR (Rn)XRL A, direct a 1 1 a 0 1 0 1 65 2 1 (A) - (Al XOR (direct)a7 a. a. a. a. a. a, ao Byte 2XRLA,@Ri 0 1 1 0 0 1 1 1 66-67 1 1 (Al - (Al XOR «Ri))XRLA,#data 0 1 1 a 0 1 0 a 64 2 1 (Al - (Al XOR #datad7 de d. d. d. d. d, do Byte 2

• MSM80C31 F/80C51 F •• ------'------'-----------­INSTRUCTION SET DETAILS (CONT.)MnemonicInstruction Code07 D. D. D. D. 02 0, Do,HexadecimalByte CycleMOVA,Rn 1 1 1 0 1 n2 n, no E8-EF 1 1 (A)-(Rn)MOV A, direct 1 1 1 0 0 1 0 1 E5 2 1 (A) - (direct)a7 a8 a. a. a. a2 a, ao Byte 2MOVA,@Ri 1 1 1 0 0 1 1 1 E6-E7 1 1 (A)-((Ri»MOVA,#data 0 1 1 1 0 1 0 0 74 2 1 (A)-#datad7 d. d. d. d. d2 d, do Byte 2MOVRn,A 1 1 1 1 1 n2 h, no .F8-FF 1 1 (Rn)-(A)MOV Rn, direct 1 0 1 0 1 n2 n, no A8-AF 2 2 (Rn) - (direct)a7 a8 a. a. a. a2 a, ·ao Byte 2MOV Rn, #data 0 1 1 1 1 m n, no 78-7F 2 1 (Rn)-#datad7 d. d. d. d. d2 d, do Byte 2MOV direct, A 1 1 1 1 0 1 0 1 F5 2 1 (direct) - (A)a7 a. a. a. a. a2 a, ao Byte2 .MOV direct, Rn. 1 0 0 0 1 n2 n, no 88-8F 2 2 (direct) ;...... (Rn)'a7 a. a. a. a. a2 a, ao Byte 2ExplanationMOV direct 1, 1 0 0 0 0 1 0 1 85 3 2 (direct 1 ) - (direct 2)direct 2 a~ a~ a~ a~ a~ a~ a~ aK Byte 2at a~ aA al a! a~ a1 a& Byte 3MOV direct, @Ri 1~0 0 0 0 1 1 1 86-87 2 2 (direct) - ((Ri»a7 a. as a. a. a2 a, ao Byte 2'* c:~ MOVdlrect, 0 1 1 1 0 1 0 1 75 3 2 (direct) -#data#data a7 a. as a. a. a2 a, ao Byte 2~c d7 d. d. d. d. d2 d, do Byte 3MOV@Ri,A 1 1 1 1 0 1 1 . 1 F6-F7 1 1 ((Ri»-AMOV @Ri, direct 1 0 1 0 0 1 1 1 A6-A7 2 2 ((Ri» - (direct)a7 a. a. a. a. a2 a, ao Byte 2MOV @Ri, #data 0 1 1 1 0 1 1 1 76-77 2 1 ((Ri»-#datad7 d. d. d. d. d2 d, do Byte 2MOVDPTR, 1 0 0 1 0 0 0 0 90 3 2 (DPTR) - #data,.#data16 d,. d,. d,. d12 d11 dlO d. d. Byte 2d7 d. d. d4 d. d2 d, do Byte 3MOVCA,@A+ 1 0 0 1 0 0 1 1 93 1 2 (A) - ((A) + (DPTR»DPTRMOVC A, @A+PC 1 0 0 O. 0 0 1 1 83 1 2 (PC) - (PC) + 1 , (A) - ((A) + (PC»MOVXA,@Ri 1 1 1 0 0 0 1 1 E2-E3 1 2 (A) -«Ri» !:xternal RAMMOVX A, @DPTR 1 1 1 0 0 0 0 0 EO 1 2 (A) - «DPTR» External RAMMOVX@Ri,A . 1 1 1 1 0 0 1 1 F2-F3 1 2 «Ri»-(A) External RAMMOVX @DPTR, A 1 1 1 1 0 0 0 0 FO 1 2 ((DPTR» - (A) External RAMPUSH direct 1 1 0 0 0 0 0 0 CO 2 2 (SP)-(SP) +1a7 a. as a. a. a2 a, ao Byte 2 (($P» -(direct)POP direct 1 1 0 1 0 0 0 0 DO 2 2 (direct) - ((SP»a7 ae as a. a. a2 a, ao Byte 2 (SP) - (SP) - 1XCHA,Rn 1 1 0 0 1 n2 n, no C8-CF 1 1 (A):: (Rn)XCH A, direct 1 1 0 0 0 1 0 1 C5 2 1 (A) :: (direct). a7 a • a. a. a. a2 a, ao Byte 2302 .

________________________________________ -4. MSMSOC31F/SOC51F •INSTRUCTION SET DETAILS (CONT.)MnemonicInstruction Code07 De Os D. 03 D. 0, DoHexadecimalByte CycleExplanationlii XCHA,@Ri_c",'lii1 1 0 0 0 1 1 1 C6-C7 1 1 (A) = ((Ri))0'= XCHOA,@Ri 1 1 0 1 0 1 1 1 06-07 1 1 (A3-ol =((Ri3- ol)'" '"CLRC 1 1 0 0 0 0 1 1 C3 1 1 (C)-OCLRbit 1 1 0 0 0 0 1 0 C2 2 1 (bit)-Ob7 b6 bs b. b3 b. b, bo Byte 2SETBC 1 1 0 1 0 0 1 1 03 1 1 (C)-1SETBbit 1 1 0 1 0 0 1 0 02 2 1 (bit) -1cbr b. bs b. b3 b. b, bo Byte 20:; CPLC 1 0 1 1 0 0 1 1 B3 1 1 (C)-(C):;~'cE '"1 0 1 1 0 0 1 0b7 be bs ·b. b3 b. b, boB2Byte 2CPLbit 2 1 (bit) - (bit)Q):0 ANLC, bit 1 0 0 0 0 0 1 0 82 2 2 (C) - (C) AND (bit).!11 b7 be bs b. b3 b. b, bo Byte 2ffi>c: ANLC,Ibit 1 0 1 1 0 0 0 0 BO 2 2 (C) - (C) AND (bit)'"Q)b7 be b. b. b3 b. b, bo Byte 2"8m ORLC, bit 0 1 1 1 0 0 1 0 72 2 2 (C) - (C) OR (bit)b7 b. b. b. b3 b. b, bo Byte 2ORL C,Ibit 1 0 1 O· 0 0 0 0 AO 2 2 (C) - (C) OR (bit)b7 b. b. b. b3 b. b, bo Byte 2MOVC, bit 1 0 1 0 0 0 1 0 A2 2 1 (C) -(bit)b7 b. b. b. b3 b. b, bo Byte 2MOV bit, C 1 0 0 1 0 0 1 0 92 2 2 (bit)-(C)b7 b. b. b. b3 b. b, bo Byte 2ACALL addr 11 810 89 a. 1 0 0 0 1 Byte 1 2 2 (PC) - (PC) + 287 8s a. a. a3 a. a, ao Byte 2 (SP) - (SP) + 1((SP)) - (PC7 - 0)(SP) - (SP) + 1((SP)) -(PC,.-.)(PC) - page addressLCALLaddr 16 0 0 0 1 0 0 1 0 12 3 2 (PC) -815814 a'3 812 811 810 89 a. Byte 2 (SP) -(PC) + 3(SP) + 1- (PC7 - 0)(SP) - (SP) + 187 86 8s 84 83 82 a 1 ao Byte 3 ((SP))C> ((SP)) - (PC,.-.)(PC) -addr,.-o:c:(Jc RET 0 0 1 0 0 0 1 0 22 1 2 (PC,.-.) - ((SP))f!.c (SP) - (SP) - 1E (PC7 - ol- ((SP))~e(SP) - (SP) - 10.. RETI 0 0 1 1 0 0 1 0 32 1 2 (PC,.-.) -((SP))(SP) - (SP) - 1(PC7 - ol- ((SP))(SP) - (SP) - 1AJMP addr 11 810 89 a. 0 0 0 0 1 Byte 1 2 2 (PC) - (PC) + 2a7 a6 a. a. a3 a. a, ao Byte 2 (PC '0 - 0) - page addressLJMPaddr 16 0 0 0 0 0 0 1 0 02 3 2 (PC) -addr,.-o815814813812811 810 89 a. Byte 287 86 8s 84 83 82 8, ao Byte 3303

• MSM80C31 Ff80C51F •• -----------------------------------------INSTRUCTION SET DETAILS (CONT.)MnemonicInstruction Code07 D. Os D. Os 02 0, DoHexadecimalByte CycleExplanationSJMPrel 1 0 0 0 0 0 0 0 SO 2 2 (PC) - (PC) + 2r7 r. rs r. rs r2 r, ro Byte 2 (PC) - (PC) + reiJMP@A+DPTR 0 1 1 1 0 0 1 1 73 1 2 (PC) - (A) + (DPTR)JZ rei 0 1 1 0 0 0 0 0 60 2 2 (PC) - (PC) + 2r7 r. r. r. rs r2 r, ro Byte IF (A) = 0 THEN (PC) - (PC) + reiJNZrel 0 1 1 1 0 0 0 0 70 2 2 (PC) - (PC) + 2r7 r. rs r. rs r2 r, ro Byte 2 IF (A) ~ 0 THEN (PC) - (PC) + reiJCrel 0 1 0 0 0 0 0 0 40 2 2 (PC) - (PC) + 2r7 r. rs r. rs r2 r, ro Byte 2 IF (C) ~ 1 THEN (PC) - (PC) + reiJNCrel 0 1 0 1 0 0 0 0 50 2 2 (PC) - (PC) + 2r7 r. r. r. rs r2 r, ra Byte 2 IF (C) ,. 0 THEN (PC) - (PC) + reiJB bit, rei 0 0 1 0 0 0 0 0 20 3 2 (PC) - (PC) + 3b7 b. b. b. bs b2 b, bo Byte 2 IF (bit) = 1 THEN (PC) - (PC) + reir7 r. rs r. rs r2 r, ro Byte 3JNB bit, rei 0 0 1 1 0 0 0 0 30 3 2 (PC) - (PC) + 3b7 b. b. b. bs b2 b, bo Byte 2 IF (bit) = 0 THEN (PC) - (PC) + reir7 r. rs r. rs r2 r, ro Byte 3JBC bit, rei 0 0 0 1 0 0 0 0 10 3 2 (PC) - (PC) + 3b7 b. b5 b. bs b2 b, bo Byte 2 IF (bit) = 1 THEN (bit) -0r7 r. r. r. rs r2 r, ro Byte 3 (PC) - (PC) + reienc: CJNE A, direct, 1 0 1 1 0 1 0 1 B5 3 2 (PC) - (PC) + 3:.c0 rei a7 a. as a. as a2 a, ao Byte 2 IF (direct) < (A) THEN (PC) - (PC)c:~ r7 r. r. r. rs r2 r, ro Byte 3 +reland(C)-O.c IF (direct) > (A) THEN (PC) - (PC)E~en+ rei and (C)-lE! CJNE A, #data, 1 0 1 1 0 1 0 0 B4 3 2 (PC) - (PC) + 30..rei d7 d. ds d. ds d2 d, do Byte 2 IF #data < (A)r7 r. rs r. rs r2 r, ro Byte 3 THEN (PC) - (PC) + rei and(C)-OIF #data> (A) THEN (PC) - (PC) +rei and (C) -1CJNE Rn, #data, 1 0 1 1 1 n2 n, no BS-BF 3 2 (PC) - (PC) + 3rei d7 d. ds d. ds d2 d, do Byte 2 IF #data < (Rn) THEN (PC) - (PC)r7 r. rs r. rs r2 r, ro Byte 3 + rei and (C)-OIF #data> (Rn) THEN (PC) - (PC)+ rei and (C) -1CJNE@Ri, 1 0 1 1 0 1 1 1 B6-B7 3 2 (PC) - (PC) + 3#data,rel d7 d. d. d. ds d2 d, do Byte 2 IF #data < «Rill THEN (PC) -r7 r. rs r. rs r2 r, ro Byte 3 (PC) + rei and (C)-OIF #data> «Ril) THEN (PC) -(PC) + rei and (C) - 1DJNZRn, rei 1 1 0 1 1 n2 n, no OS-OF 2 2 (PC) - (PC) + 2r7 r. r. r. rs r2 r, ro Byte 2 (Rn) - (Rn) - 1IF (Rn) 'I' 0 THEN (PC) -(PC) + rei. DJNZ direct, rei 1 1 0 1 0 1 0 1 05 3 2 (PC) - (PC) + 3a7 a. as a. as a2 a, ao Byte 2 (direct) - (direct) - 1r7 r. rs r. rs r2 r, ro Byte 3 IF (direct) "F 0 THEN (PC) - (PC)+ reiNOP 0 0 0 0 0 0 0 0 00 1 1 (PC) - (PC) + 1304

--------------------..... MSM80C31 F/SOC51 F •NOTES ON THE INSTRUCTION SET AND THE ADDRESSING MODESRndirect@Ri#data#data 16addr 16addr 11reibit- Register R7 -RO of the currentlyselected Register Bank.- 8-bit internal data location's address.This could be an Internal Data RAMlocation (0 - 1 27) or a SFR [i.e., I/Oport, control register, status register,etc. (128 - 255)].- 8-bit internal data RAM location (0 -255) addressed indirectly throughregister R1 or RO.. - 8-bit constant included in instruction.- 16-bit constant included in instruction.- 16-bit destination address. Used byLCALL & LJMP. A branch can beanywhere within the 64K-byteProgram Memory address space.- 11 -bit destination address. Used byACALL & AJMP. The branch will bewithin the same 2K-byte page ofprogram memory as the first byte ofthe following instruction.- Signed (two's complement) 8-bit offsetbyte. Used by SJMP and all conditionaljumps. Range is -128 to +127 bytesrelative to first byte of the followinginstruction.- Direct Addressed bit in Internal DataRAM or Special Function Register.INSTRUCTIONS THAT AFFECT FLAG SETTINGS 1INSTRUCTION FLAG INSTRUCTION FLAGADDAD DCSUSSMULDIVDARRCRLCSETacC OVACx X XX X XX X X0 X0 XXXXICLRCCPLCANL C, bitANL C,IbitORL c, bitORL C, fbitMOV c, bitCJNEC OVAC0XXXXXXX1 Note that operations on SFR byte address 208 or bitaddresses 208-215 (i.e., the PSW or bits in the PSW) willalso affect flag settings.305

• MSM80C31 F/80C.51 F •• --------------------APPLICATION EXAMPLES1P1.0 2P1.1 3P1.2 4P1.38.2K~9L... ..... ..:.::.,~XTAL2 :~:: :MSM82C43::;V----,---.-..t~P1.6 8P1.7 I/OP2.0 t-;,:-__ 1;.;1,... P20· EXPANDERPi.1 1 P21RESETP2.2 P2210", MSM80C51 F P2.3 ,P23'--__..;;3;.;.1.., EAP2.4 iT.:---....P2.5 H'r-::'--'P2.6P2.71/0Pl.O (RXD)Pl.1 (TXDIP3.2 (INTO)P3.3(lNT1)P3.4 (TO)P3.5 (T1)Pl.6 (WR)P3.7 (RD) ALEPO.OPO.1P02PO.3PO.4PO.5PO.6PO.729The following software driver is required to interface to the 82C43Mixing Parallel Output, Input, andControl Strobes on Port 2.INPuT DATA FROM AN 82C43 110 EXPANDERCONNECT TO P23-P20P25 & P24 MIMIC CSt & PROGP27-P26 USED AS INPUTSPORT TO BE READ IN ACCIN82C43MOVMOVClRORlMOVSETBA, #110100008P2,A ;OUTPUT INSTRUCTION CODEP2.4 ;FAllING EDGE OF PROGP2,#OOOO1111B ;SET FOR INPUT. A,P2 ;READ INPUT DATAP2.4 ;RETURN PROG HIGHAddressInstructionP21 P20 Code P23 P22 Code0 0 Port 4 0 0 Read0 Port 5 0 Write0 Port 6 0 ORlDPort 7ANlD1/0 ExpanslonJUslng an 82C43306

-----------------------------------------4eMSM80C31F/SOC51F •APPLICATION EXAMPLES (CONT.)19~7 FI Cl-=;opf[" ]!8~XTAL28.2K*~tRESETEA1039P3.0 (RXD) PO.O11 38P3.1 (TXD) PO.11237P3.2 (INTO) PO.21336P3.3 (INn) PO.31435P3.4 (TO) PO.41534P3.5 (n) PO.5"o{ 1633P3.6 (WR) PO.617P3.7 (RD) ALE PO.732PSEN291107FI19XTAL 1 VeeVSS 1P1.02P1.1Jj.P1.23P1.34P1.456O::;opf!" ]l8~ XTAL2 P1.5P1.678.2 KP1.78cr21P2.022P2.1RESET23P2.2MSM80C51F 24P2.3P2.425 I/OP2.526P2.62731EA P2.7 281039P3.0 (RXD)po.o11P3.1 (TXD)38PO.112P3.2 (INTO)37PO.213P3.3 (INn)36PO.314P3.4 (TO) PO.435,~{ 15P3.5 (n) PO.53416P3.6 (WR) PO.63317P3.7 (RD) ALE PO.73229Multiple 80C51 F's Using Half-Duplex Serial Communication307

• MSMSOC31F/SOC51F .---------------------------------------•APPLICATION EXAMPLES (CONT.)191~rIE!;~1OP~ XTAL212K~E9RESET10., MSM80C51F+5V GND20w{31 Eli:10P3.0IRXDI11P3.1 1!l!QI12P3.2I1NTOI13P3.31iR'i'i114P3AITOIP3.5ITllP3.6Iiil1lP3.71ii1i1 ALEjiffij30 29PO.OPO.lPO.2PO.3POAPO.SPO.6PO.7393733121ADO14ADI1AD2AD316AD4ADS18AD61AD7101110iMiiiiWRALEMSM81C55plio :PBl 31~ 32PM 34=:3PB7 38TIMERINCAN BE SOI'PLIED BY SYSTEM RESET ..- ...."O':~-"ll""!3~-..OR PORT LINE OF 8OC51 ,.,TIMERAdding a Data Memory and 1/0 ExpanderI/O19XTAL2110MSM80C51FP3.0 IRXDIP3.1ITXDI.... - .... ----:'-;ff P3.21i1m11P3.31im'l1P3.4ITOIP3.5 I!!IP3.6!!!!!1P3.7 IRDI ALEMultiple Interrupt Sources308

-----------------------------------------eeMSMSOC31F/SOC51F eMSM80C31/MSM80C51 INSTRUCTION CODES~ 0 1 2 3 4 5 6 70000 0001 0010 0011 0100 0101 0110 0111AJMP LJMP0INCNOP address 11 address 16 RRA INCA INC@RO INC@Rl0000(Page 0)direct1 JBCbit,0001 rei2 JBbit,0010 rei3 JNBbit,0011 rei4 JCbit,0100 rei50101601107011181000ACALL LCALL ....DECaddress 11 address 16 RRCA DECA DEC@RO DEC@Rl(Page 0)directAJMPaddress 11 RET RLA(Page 1)ACALLaddress 11 RETI RLCA(Page 1)AJMPaddress 11(Page 2)ORLdirect, AORLdirect,#dataADD A, ADDA, ADDA, ADD A,#data direct @RO @RlADDCA, ADDCA, ADDCA, ADDCA,#data direct @RO @RlORLA, JII'" ORLA, ORLA, ORLA,#data direct @RO @RlACALLANLANLANLA, JII'" ANLA, ANLA, ANLA,JNCrel address 11 direct,direct, A(Page 2)#data direct @RO @Rl#data,.AJMP XRLXRLXRLA, XRLA, XRLA, XRLA,JZrel address 11direct,direct, A(Page#data direct @RO @Rl3)#dataACALLORLC, JMP JII'" MOVA,MOVJNZrel address 11 direct,(Pagebit @A+DPTR #data3)#dataMOV@RO, MOV@Rl,#data #dataAJMPMOV MOV MOVANLC, MOVCA,SJMPrel address 11DIVAB direct 1, direct, direct,bit @A+PC(Page 4) direct 2 @RO @Rl....9 MOVDPTR,1001 #data 16ACALLaddress 11(Page 4)AJMPA1010 ORLC/bit address 11(Page 5)B1011C PUSH1100 directD POP1101 directE MOVXA,1110 @DPTRMOVbit, MOVCA, JII'" SUBBA, SUBBA, SUBBA, SUBBA,C @A+DPTR #data direct @RO @RlMOVC, Jll"'MOV@RO, MOV@Rl,INC DPTR MULABbitdirect directACALL CJNEA, CJNEA, CJNE@RO, CJNE@Rl,ANLC/bit address 11 CPL bit CPLC #data, direc(, #data, #data,(Page 5) rei rei rei reiF MOVX1111 @DPTR,A....AJMP JII'"address 11 CLRbit CLRC SWAP A(Page 6)XCHA, XCHA, XCHA,direct @RO @RlACALL JII'" DJNZXCHDA, XCHDA,address 11 SETBbit SETBC DAA direct,(Page 6) rei @RO @RlAJMPaddress 11(page 7)ACALLaddress 11(page 7)MOVXA, MOVXA, MOVA, MOVA, MOVA,CLRA@RO @Rl direct @RO @RlJII'"MOVX MOVXMOV MOV MOVCPLA@RO,A @Rl,A direct, A @RO,A @Rl,A2 BYTE 3 BYTEMNEMONIC2 CYCLE 4 CYCLE309

• MSMSOC31F/SOC51F •• -----------------------------------------8 9 A B C D E F1000 1001 1010 1011 1100 1101 1110 1111INCRO INCRl INCR2 INCR3 INCR4 INCR5 INCR6 INCR7DECRO DECRl DECR2 DECR3 DECR4 DECR5 DECR6 DECR7ADDA,RO ADDA, Rl ADDA,R2 ADDA,R3 ADDA, R4 ADDA,R5 ADDA,R6 ADDA,R7ADDCA,RO ADDCA,Rl ADDCA,R2 ADDCA,R3 ADDCA,R4 ADDCA,R5 ADDCA,R6 ADDCA,R7ORLA,RO ORLA,Rl ORLA,R2 ORLA,R3 ORLA,R4 ORLA,R5 ORLA,R6 ORLA,R7ANLA,RO ANLA,Rl ANLA, R2 ANLA,R3 ANLA,R4 ANLA,R5 ANLA, R6 ANLA,R7XRLA,RO XRLA,Rl XRLA, R2 XRLA, R3 XRLA,R4 XRLA, R5 XRLA,R6 XRLA, R7MOVRO, MOVR1, MOVR2,I MOVR3, ,. MOVR4, MOVR5, MOVR6, MOVR7,#data #data #data #data #data #data #data #data,.MOV MOV MOV MOV MOV MOV MOV,.MOVdirect, direct, direct, direct, direct, direct, direct, direct,RO Rl R2 R3 R4 R5 R6 R7SUBBA, SUBBA, SUBBA, SUBBA, SUBBA, SUBBA, SUBBA, SUBBA,IRO Rl R2 R3 R4 R5 R6 R7,.MOVRO, MOVR1, MOVR2, MOVR3, MOVR4, MOVR5, MOVR6, MOVR7,direct direct direct direct direct direct direct directCJNERO, .... CJNE Rl, CJNER2, .... CJNER3, CJNE R4, .... CJNE R5, .... CJNER6, CJNER7, ....#data, #data, #dala, #data, #data, #data, #data, #data,rei rei rei rei rei rei rei reiIXCHA, XCHA, XCHA, XCHA, XCHA, XCHA, XCHA, XCHA,RO Rl R2 R3 R4 R5 R6 R7,. ,. ,. ,. ,.DJNZRO, DJNZR1, DJNZR2, DJNZR3, DJNZR4, DJNER5, DJNER6, DJNER7,rei rei rei rei rei rei rei reiMOVA,RO MOVA, Rl MOVA,R2 MOVA,R3 MOVA,R4 MOVA,R5 MOVA,H6 MOVA,R7MOVRO,A MOVR1,A MOVR2,A MOVR3,A MOVR4,A MOVR5,A MOVR6,A MOVR7,A310

OKI semiconductorMSM80C51 FVSM80C51 PIGGY BACKGENERAL DESCRIPTIONThe MSM80C51 FVS is a device whose built-in ROM is replaced by external EPROM using thepiggy-back method. External EPROM capacity is up to 4K bytes. It can be used for evaluation of programsfor MSM80C51 F.FUNCTIONAL BLOCK DIAGRAMP20 - P27r------------------ICONTROL SIGNALSP/W SIGNALSPOO-P07XTAL 1 ---i---IXTAL2 --T--IALE--+--IPSEN--T--IEARESET --T--L...:~~Pl0-P17I",P30- P37 ~ ______________--.-JI ~~====================~~L __________________________ ~INSTALLATION METHOD FOR EXTERNAL ROMRecommended EPROMS - 2764, 2732M80C51VSOKIJapan 5101Pin 1 For 80C51VS ROM SocketPin 1 For 2732Pin 1 For80C51VS ROM Socket311

OKI semiconductorMSM80C154/ MSM83C154CMOS 8-bit One-Chip MicrocontrollerGENERAL DESCRIPTIONThe MSM83C154/MSM80C154 is a high performance 8-bit one-chip microcontroller implementing largeintegration, high speed and low power consumption by 2 ,um silicon gate CMOS process technology.The MSM83C154 features 16K byte ROM, 256 byte RAM, 32 I/O ports, three 16-bit timer/counters,multifunctional serial port and clock generator. In addition, the MSM83C154 has three standby modesenabling further power reduction.The MSM80C154 is identical to the MSM83C154 except the omission of 16K byte ROM.FEATURES• Fully static circuit• On-chip program memory• On-chip data memory• External program memory address space• External data memory address space• I/O ports(Port 1,2,3, impedance programmable)• 16-bit timer/counters: 16K x 8 bit ROM (MSM83C154 only): 256 x 8 bit RAM: 64K bytes: 64K bytes(includes watch dog timer & 32 bit timer) : 3• Multifunctional serial port' I/O Expansion mode: UART mode (featuring error detection)6-source 2-priority levelinterrupt and multi-levelinterrupt available by programming IP and IE registers• Memory-mapped special function registers• Bit addressable data memory and SFRs• Minimum instruction cycle: 0.75 ,us @16 MHz operation• "Multiply" /"divide" instruction cycle• Standby functions: 3216 MHz version of MSM83C154 (12 MHz < XTAL1 .2.;; 16 MHz) is now under development.: 3,us @16 MHz operation: Idle mode (CPU halt): Power down mode (Oscillator stop)Activated by Software or Hardware; Providing ports withfloating or active statusThe software power down mode is terminated byinterrupt signal enabling excution from the interruptedaddress.• Lower power consumption achieved by 2 ,um silicon gate CMOS process• Upward compatible with MSM80C51/80C31• Packages : 40-pin DIP, 44-pin flat package and 44-pin PLCC312

P2.0P2.7R/WSIGNAL('):xl(')c:=iOJr-g" c»C)::D»~P1.0w-wP1.7P3.0P3.7TIMER/COUNTER 0 & 1•31:eniii:

• MSM80C154/83C154 .----------------~----PIN CONFIGURATIONMSM83C154-XX RS/MSM80C154RS(Top-View) 40 Lead Plastic DIPPl.o/T2P1.l/T2EXP3.3/INTlP3.4/TOP3.5/Tl/HPDIP3.6/WR 1P3.7/RDXTAL2XTALlVeePO.OPO.lPO.2PO.3.. PO.4EAALEPSENP2.7P2.l_ P2.0MSM83C154-XXGS/MSM80C154GS *1(Top-View) 44 Lead Plastic PackageP1.5P1.GP1.7RESETNCP3.0/RXDP3.l/TXDP3.2/iNTOP3.3/iNTlP3.4/TOP3.5/Tl/HPDI)(wt~~'~ ~ ~ ~ ~ ~ ~ ~ ~ ~PO.4PO.5PO.6PO.7EAALEl'SENNCP2.7P2.6P2.5oMSM83C154-XXJS/MSM80C154JS *1(Top-View) 44 Lead Plastic Leaded Chip CarrierPl.5 :7JPl.6 )~:Pl.7 JjRESET I.9JP3.0/RXD \:lJ)(w~ ~::':qu0:: a: z'6' '5' '4' '3 ' 'z' '1 ' \U'~:J '4

--------------------. MSM80C154/83C154 •PIN FUNCTIONS (CaNT.)Pin NameDescriptionP2.0 - P2.7 P2.0 to P2.7 are quasi-bidirectional I/O ports. They also output the higher 8-bitaddress when an external memory is accessed. They are pulled up internally whenused as input ports.P3.0 - P3.7 P3.0 to P3.7 are quasi-bidirectional I/O ports. They are pulled up internally whenused as input ports. They also have the following secondary functions:ALEPSENEARESET.P3_0 (RXD)Serial data input/output in the I/O expansion mode and serial data input in theUART mode when the serial port is used .• P3.1 (TXD)Synchronous clock output in the I/O expansion mode and serial data output inthe UART mode when the serial port is used .• P3.2 (INTO)Used as input pin for the external interrupt 0, and as count-up control pin for thetimer/counter O .• P3.3 (INT1)Used as input pin for the external interrupt 1, and as count-up control pin for thetimer /counter 1 .• P3.4 (TO)Used as external clock input pin for the timer/counter O .• P3.5 (Tl)Used as external clock input pin for the timer/counter 1 and power down modecontrol input pin .• P3.6 (WR)Output of the write strobe signal when data is written into external data memory .• P3.7 (RD)Output of the read strobe signal when data is read from external data memory.Address latch enable output for latching the lower 8-bit address during externalmemory access. Two ALE pulses are activated per machine cycle except duringexternal data memory access at which time one ALE pulse is skipped.Program store enable output which enable the external memory output to the busduring external program memory access. Two PSEN pulses are activated permachine cycle except during external data memory access at which two PSENpulses are skipped.------- -~-~--When EA is held at "H" level, the MSM83C154 executes instructiohs frominternal program memory at address OOOOH to 3FFFH, and executes instructionsfrom external program memory above address 3FFFH.When EA is held at "L" level, the MSM80C154/MSM83C154 executes instructionsfrom external program memory for all addresses ... -~,---If this pin remains "H" for at least 1 Jl second, the MSM80C154/MSM83C154 isreset. Since this pin is pulled down internally, a power-on reset is achieved bysimply connecting a capacitor between Vcc and this pin.XTAL1 Oscillator inverter input pin. External clock is input through XTAL1 pin ..---XTAL2 Oscillator inverter output pin.VCCVSSPower supply pin during both normal operation and standby operations_--f---GND pin.315

• MSM80C154/83C154 .--------------------DATA MEMORY AND SPECIAL FUNCTION REGISTERLAYOUT DIAGRAMr-oFFHOF8H IOCON~r---'OFOH B --.. ~OEOH ACC -+--< f-ODOH PSW ..- f-OCDH TH2 f-OCCH TL2 f--OCBH RCAP2H--f-OCAH RCAP2L--f-OC8H T2CON ---., f-OB8H IP --., f-OBOH P3 ..- ~::2:

~----------------------. MSM80C154/83C154 •DETAILED DIAGRAM OF DATA MEMORY (RAM)OFFH2557FH1272FH7F7E70 7C 787A 79 78 472EH77 7675 74 7372 71 70 4620H6F6E60 6C 686A 69 68 452CH67 6665 64 6362 61 60 4428H2AH29H28H27H26H25H5F 5E57 564F 4E47 463F 3E37 362F 2E50 5C 5855 54 5340 4C 4845 44 4330 3C 3835 34 3320 2C 285A 59 58 4352 51 50 424A 49 48 4142 41 40 403A 39 38 3932 31 30 382A 29 28 37(!)(!) ZZ Ci5 (!)Ci5Ul ZUl Ww a: Ci5Ula: 0 w0 0 a:0 « 0« w 0I-t:«aJ >- l-aJ e..>l- I- we..>e..> a:w wa: a: 00 0~II24H27 2625 24 2322 21 20 3623H1F1E10 1C 181A 19 18 3522H17 1615 14 1312 11 10 3421HOFOE00 OC 08OA 09 08 3320H1FH18H17H10HOFH08H07HOOH07 0605 04 038ank 38ank 28ank 18ank 002 01 00 323124231615870(!)ZCi5Ulwa:00«a:wI- Ul(!)wa:317

• MSM80C154/83C154 .--------------------DETAILED DIAGRAM OF,SPECIAL FUNCTION REGISTERSSpecialDirectFunctionByte. RegisterAddress Bit Address Symbol(MSB)(LSB)WOT T32 SE RR IZC P3HZ P2HZ P1 HZ ALFOF8H FF FE FO FC FB1 FA 1 F9 F8 10CONOFOH F7 F6 F5 F4 F31 F2 1F1 FO BOEOH E7 E6 E5 E4 E31 E2 E11EO ACCCY AC FO RS1 RSO OV F1 POOOH 07 06 05 04 03 02 01 DO PSWOCOH Not Bit Addressable TH2OCCH Not Bit Addressable TL2UOCBH Not Bit Addressable RCAP2HOCAH Not Bit Addressable RCAP2LTF2 EXF2 RCLK TCLKEXEN2 TR2 C/T2 CP/RL2OC8H 1 CF 1 CE 1 CO 1 CC 1 CB 1 CA 1 C9 1 C81T2CONPCT PT2 PS PTl PX1 PTO PXOOB8H BFI - BO BC BB I BA IB9I B8 I ·IPOBOH B7I B6 I B5 I B4 I B3 I B2 I B1 I BO I P3EA ET2 ES ET1 EX1 ETO EXOOA8H I AI' 1 - 1 AD 1 AC 1 AB 1 AA IA9 1 A8 IEOAOH 1 A7 1 A6 1 A51 A4 1 A3 1 A2 1 A1 1 AOI P299H Not Bit AddressableI SBUF98HSMO SM1 SM2 REN TB8 RB8 TI RII 9F I 9E1 90 I 9C 1'19B 1 9A 1 99 1 98 SCON90H I 97 1 96 1 95 1 94 I 93 1 92 1 91 1 90 P1318

--------------------. MSM80C154/83C154 •DirectByteAddressBit AddressSpecialFunctionRegisterSymbol(MSB)(LSB)8DH8CH8BH8AH89HNot Bit AddressableNot Bit AddressableNot Bit AddressableNot Bit AddressableNot Bit AddressableTH1THOTL1TLOTMOD88H87HTCONPCON83H82H81H80HNot Bit AddressableNot Bit AddressableNot Bit Addressable87 I 86 I 85 I 84 I 83 I 82 I 81 I 80DPHDPLSPPO319

• MSM80C154/83C154 .--------------------SPECIAL FUNCTION REGISTERSTimer mode register (TMOO)NAMEADDRESSMSB7 6._._-r-...TMOD 89H GATE c/f5 4 3M1 MO GATE2 1c/fM1LSBoMODBIT LOCATION FLAGFUNCTION-------4---------4- I ITMOD.OMO M1 : MO : Timer/counter 0 mode setting- - - - - -,- - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --o : 0 : 8-bit timer /counter with 5-bit prescalar.- - - - - - t - - - - J- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --TMOD.1TMOD.2M1CITo : 1 I 16-bit timer/counter.___ - - - - - - - - _1- ____________________________________ _1 : 0 : 8-bit timer/counter with 8-bit auto reloading.---1- --:- -; - -i- Ti~~;/;o~~;;rO ;e~;~;ed -i~;O-TLO-(8~bi;) ;i;;'~;/- ---I: : counter and THO (8-bit) timer/counter. TFO is set: : by T LO carry, and TF 1 is set by THO carry.Timer/counter 0 count clock designation control bit.XTAL1 ·2 divided by 12 clocks. is the input applied to timer/countero when cif = "0".The external clock applied to the TO pin is the input applied totimer/counter 0 when c/f = "1 ".TMOD.3 GATE When this bit is "0", the TRO bit of TCON (timer control register) isused to control the start and stop of timer /counter 0 counting.If this bit is "1", ti mer/counter 0 starts counting when boththe TRO bit of TCON and INTO pin input signal are "1", and stopscounting when either is changed to "0".-------------4---------4--TMOD.4MO M1 : MO : Timer/counter 1 mode setting.o : 0 : 8-bit timer/counter with 5-bit prescalar. .- - - - - - - - - - - - 1- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --~ ~ -_~ ~ -r~~ ~ ~ I ~1~~~i~- :i_~~!~~~~u~~ir~ ~ ~~_-_-_-_-_-~~ _- ~_-_~~~ ~ ~ -_-_~-_~-------------+----------1 1 : 0 : 8-bit timer/counter with 8-bit auto reloading.------1-- ___ 1_- ____ _,--------- _________________ _TMOD.5M11 : 1 : Timer/counter 1 operation stopped.ITMOD.6 CITTMOD.7GATETimer/counter 1 count clock designation control bit.XTAL 1 ·2 divided by 12 clocks is the input applied to timer/counter1 when cif = "0".The external clock applied to the T1 pin is the input applied totimer/counter 1 when cif = "1 ".When this bit is "0", the TR1 bit of TCON is used to controlthe start and stop of timer/counter 1 counting.If this bit is "1", timer/counter 1 starts counting when boththe TR1 bit of TCON and INT1 pin input signal are "1 ", and stopscounting when either is changed to "0".320

---------------------. MSM80C154/83C154 •Power control register (peON)NAMEADDRESSMSBLSB7 6 5 4 3 2 1 0PCON 87H SMOD HPD RPO - GF1 GFO PD IDLBIT LOCATION FLAG FUNCTIONPCON.O IDL IDLE mode set when this bit is set to "1". CPU operations arestopped when I DLE mode is set, but XTAL 1 -2, timer /counters 0, "and2, the interrupt circuits, and serial port remain active. IDLE modeis cancelled when the CPU is reset or when an interrupt is generated.PCON.1 PD PD mode set when this bit is set to "1". CPU operations and XT ALl' 2are stopped when PD mode is set. PD mode is cancelled when the CPUis reset or when an interrupt is generated.PCON.2 GFO General purpose bit.Testing this flag when IDLE mode is cancelled by an interrupt showswhether the interrupt is a normal interrupt or an I DLE mode releaseinterrupt.PCON.3 GF1 General purpose bit.Testing this flag when PD mode is cancelled by an interrupt showswhether the interrupt is a normal interrupt or a PD mode releaseinterrupt.PCON.4 - Reserved bit. The output data is "1" if the bit is read.PCON.5 RPD Bit used to specify cancellation of CPU power down mode IIDLE orPD) by interrupt signal.Power down mode cannot be cancelled by interrupt signal if interruptis not enabled by IE !interrupt enable register) when this bit is "0".If the interrupt flag is set to "1" by an interrupt request signal whenthis bit is "1" leven if interrupt is disabled), the program is executedfrom the next address of the power down mode setting instruction.The flag is reset to "0" by software.PCON.6 HPD The hard power down setting mode is enabled when this bit is set to"1 ".If the level of the power failure detect signal applied to the HPDI pinIpin 3.5) is changed from "1" to "0" when this bit is "1", XTAL 1 -2oscillation is stopped and the system is put into hard power downmode. HPD mode is cancelled when the CPU is reset.PCON.7 SMOD When the timer/counter 1 carry signal is used as a clock in mode 1,2 or 3 of the serial port, this bit has the following functions.The serial port operation clock is reduced by 1/2 when the bit is"0" for delayed processing. And when the bit is "1", the serial portoperation clock is normal for faster processing.321

• MSM80C154/83C154 .--------------~------Timer control register (TCON)NAMEADDRESSMSBLSB7 6 5 4 3 2 1 0TCON 88H TFl TRl TFO TRO IEl ITl lEO ITOBIT LOCATION FLAG FUNCTIONTCON.O ITO External interrupt 0 signal used in level detect mode when this bit is"0". and in trigger detect mode when "1".TCON.l lEO Interrupt request flag for external interrupt O.Bit is reset automatically when interrupt is serviced.Bit can be set and reset by software when ITO = "1".TCON.2 ITl External interrupt 1 signal used .in level detect mode when this bit is"0". and in trigger detect mode when "1".TCON.3 IEl Interrupt request flag for external interrupt 1.Bit is reset automatically when interrupt is serviced.Bit can be set and reset by software when ITl = "1 ".TCON.4 TRO Counting start and stop control bit for timer/counter O.Timer /counter 0 starts counting when this bit is "1". and stopscounting when "0".TCON.5 TFO Interrupt request flag for timer interrupt O.Bit is reset automatically when interrupt is serviced.Bit is set to "1" when carry signal is generated from timer/counter O.TCON.6 TRl Counting start and stop control bit for timer/counter 1.Timer/counter 1 starts counting when this bit is "1 .... and stopscounting when "0".TCON.7 TFl Interrupt request flag for timer interrupt 1.Bit is reset automatically when interrupt is serviced.Bit is set to "1" when carry signal is generated from timer/counter 1.322

--------------------. MSM80C154/83C154 •Serial port control register (SCON)NAMEADDRESSMSBLSB7 6 5 4 3 2 . 1 0SCON 98H SMO SM1 SM2 REN TB8 RB8 TI RI--BIT LOCATION FLAG FUNCTIONSCON.O RI "End of serial port reception" interrupt request flag.This flag must be reset by software during interrupt service routine.This flag is set after the eighth bit of data has been received when inmode 0, or by the STOP bit when in any other mode. In mode 2or 3, however, R I is not set if the R B8 data is "0" with SM2 = "1".RI is set in mode 1 if STOP bit is received when SM2 = "1 ".SCON.1 TI "End of serial port transmission" interrupt request flag. This flagmust be reset by software during interrupt service routine.This flag is set after the eighth bit of data has been sent when inmode 0, or after the last bit of data has been sent when in any othermode.SCON.2 RB8 The ninth bit of data received in mode 2 or 3 is passed to RB8.The STOP bit is applied to RB8 if SM2 = "0" when in mode 1.RB8 can not be used in mode O.--SCON.3 TB8 The TB8 data is sent as the ninth data bit when in mode 2 or 3.Any desired data can be set in TB8 by software.-SCON.4 REN Reception enable control bitNo reception when RE N = "0".Reception enabled when REN = "1 ".SCON.5 SM2 If the ninth bit of received data is "0" with SM2 = "1" in mode 2 or3, the "end of reception" signal is not set in the RI flag.Nor is the "end of reception" signal set in the RI flag if the STOPbit is not "1" when SM2 = "1" in mode 1.I J-- JISCON.6 SM1 SMO SM1 'MODE:----------- ,,0 J 0 0 J 8-bit shift register I/O_____ .J _________________________________--------- ------- - - - - ---- ---------------------------0JJ1 1JJ8-bit UART variable baud rate--------- -- - -,- -------------- --- -------- - --- ----JSCON.7 SMO 1JI 0 2 9-bit UART 1/32 XTAL 1, 1/64 XTAL 1JJ- - - - - _1- , ___________________________________________( : baud rateI:1 :1 ,J 3 , 9-bit UART variable baud rate323

• MSM80C154/83C154 .--------------------Interrupt enable register (IE)NAMEADDRESSMSBLSB7 6 5 4 3 2,0IE OA8H EA - ET2 ES ET' EX' ETO EXOBIT LOCATION FLAG FUNCTIONIE.O EXO Interrupt control bit for external interrupt O.Interrupt disabled when bit is "0".Interrupt enabled when bit is ",".IE.' ETO I Interrupt control bit for timer interrupt O.Interrupt disabled when bit is "0".Interrupt enabled when bit is "'''.IE.2 EX' Interrupt control bit for external interrupt 1.Interrupt disabled when bit is "0".Interrupt enablea when bit is "'''.IE.3 ETl Interrupt control bit for timer interrupt ,.Interrupt disabled when bit is "0".I nterrupt enabled when bit is ",".lEA ES Interrupt control bit for serial port.Interrupt disabled when bit is "0".Interrupt enabled when bit is "'''.IE.5 ET2~Interrupt control bit for timer interrupt 2.Interrupt disabled when bit is "0".Interrupt enabled when bit is "'''.-IE.6 - Reserved bit. The output data is "'" if the bit is read.IE.7 EA Overall interrupt control bit.All interrupts are disabled when bit is "0".All interrupts are controlled by IE.O thru IE.5 when bit is ",".324

-------------'---------. MSM80C154/83C154 •I nterrupt priority register (I P)NAMEADDRESSMSBLSB7 6 5 4 3 2 1 0IP OB8H PCT - PT2 PS PTl PXl PTO PXOBIT LOCATION FLAG FUNCTIONIP.O PXO Interrupt priority bit for external interrupt O.Priority is assigned when bit is "1 ".IP.l PTO Interrupt priority bit for timer interrupt O.Priority is assigned when bit is "1 ".IP.2 PXl Interrupt priority bit for external interrupt 1.Priority is assigned when bit is "1".IP.3 PTl Interrupt priority bit for timer interrupt 1.Priority is assigned when bit is "1".IP.4 PS Interrupt priority bit for serial port.Priority is assigned when bit is "1".IP.5 PT2 Interrupt priority bit for timer interrupt 2.Priority is assigned when bit is "1".IP.6 - Reserved bit. The output data is "'" if the bit is read.IP.7 PCT Priority interrupt circuit control bit.The priority register contents are valid and priority assignedinterrupts can be processed when this bit is "0". When the bit is"1", the priority interrupt circuit is stopped, and interrupts can onlybe controlled by the interrupt enable register (IE).325

eMSM80C154/83C154 e------------------__Program status word register (PSW)NAMEADDRESSMSBLSB7 6 5 4 3 2,0PSW ODOH CY AC FO RS' RSO OV F' PBIT LOCATION FLAG FUNCTIONPSW.O P Accumulator (ACC) parity indicator."'" when the "'" bit number in the accumulator is an odd number,and "0" when an even number.PSW.' F' User flag which may be set to "0" or "'" as desired by the user.PSW.2 OV Overflow flag which is set if the carry C6 from bit 6 of the ALU orCY is "'" as a result of an arithmetic operation. The flag is alsoset to "'" if the resultant product 'of executing a,multiplicationinstruction (MUL AB) is greater than OFFH, but is reset to "0"if the product is less than or equal to OFFH.PSW.3 RSO RAM register bank switchRS' RSO BANK RAM ADDRESS0 0 0 OOH - 07H,0 2 'OH-'7HPSW.4 RS' 0 , ,OSH -OFH, , 3, 'SH -'FHPSW.5 FO User flag which may be set to "0" or "'" as desired by the user.PSW.6 AC Auxiliary carry flag.This flag is.set to "'" if a carry C 3 is generated from bit 3 of theALU as a result of executing an arithmetic operation instruction.In all other cases, the flag is reset to "0".PSW.7 CY Main carry flag.This flag is set to "'" if a carry C 7 is generated from bit 7 ofthe ALU as result of executing an arithmetic operation instruction.If a carry C 7 is not generated, the flag is reset to "0".326

--------------------. MSM80C154/83C154 •I/O control register (lOCON)NAMEADDRESS.. _-----------M~=f 6 ~5 .I,;c= 3 J:,:~ 11laCON OF8H '-~~T --:;:-;; SERRI~C ~i P2~~P1HZ ALFBIT LOCATION FLAG FUNCTIONIOCON.O ALF If CPU power down mode (PD, HPD) is activated with this bit set to"1 ", the outputs from ports 0,1,2, and 3 are switched to floatingstatus.When this bit is "0", ports 0, 1,2, and 3 are in output mode ...IOCON.1 P1 HZ_.Port 1 becomes a high impedance input port when this bit is "1 ",-_..IOCON.2 P2HZ Port 2 becomes a high impedance input port when this bit is "1 ".-IOCON.3 P3HZ Port 3 becomes a high impedance input port when this bit is "1".IaCONA IZC The 10 kohm pull-up resistance for ports 1,2, and 3 i.s switched offwhen this bit is "1 ", leaving only the 100 kohm pull-up resistance.IOCON.5 SERR Serial port reception error flag.This flag is set to "1" if an overrun or framing error is generatedwhen data is received at a serial port.The flag is reset by software.IOCON.6 T32 Timer/counters 0 and 1 are connected serially to form a 32-bittimer/counter when this bit is set to "1 ",TF1 of TCON is set if a carry is generated in the 32·bit timer/counter.IOCON,7 WDT Watchdog timer mode is set when this bit is set to "1 ", And if TF1is set to "1" after watchdog timer mode has been set, the CPU isreset and the program is executed from address O.LSB0327

eMSM80C154/83C154 e -----.,----------------Timer 2 control register (T2CON)MSB7 6 5 4 3 2 1 0NAME ADDRESSI I LSBT2CON OC8H TF2 I EXF21 RCLK I TCLK EXEN21 TR2 I C/T2 I CP/RL2BIT LOCATION FLAG FUNCTIONT2CON.0 CP/RL2 Capture mode is set when TCLK + RCLK = "0" and CP/RL2 = "1 ".16-bit auto reload mode is set when TCLK + RCLK = "0" and.CP/RL2 = "0".CP/R L2 is ignored when TCLK + RCLK = "1 ".T2CON.1 C/T2 Timer/counter 2 count clock designation control bit.The internal clocks (XTAL 1 ·2 -;- 12, XTAL 1 ·2 -;- 2) are used whenthis bit is "0", and the external clock applied to the T2 pin is passedto timer/counter 2 when the bit is "1 ".T2CON.2 TR2 Timer/counter 2 counting start and stop control bit.Timer/counter 2 commences counting when this bit is "1" and stopscounting when "0".T2CON.3 EXEN2 T2EX timer/counter 2 external control signal control bit.Input of the T2EX signal is disabled when this bit is "0", andenabled when "1".T2CON.4 TC.LK Serial port transmit circuit drive clock control bit.:Timer/counter 2 is switched to baud rate generator mode when thisbit is "1 ", and the timer/counter 2 carry signal becomes the serialIport transmit clock.Note, however, that the serial ports can only use the timer/counter 2carry signal in serial port modes 1 and 3.T2CON.5 RCLK Serial port receive circuit drive clock control bit.Timer/counter 2 is switched to baud rate generator mode when thisbit is "1 ", and the timer/counter 2 carry signal becomes the serialport receive clock.Note, however, that the serial ports can only use the timer/counter 2carry signal in serial port modes 1 and 3.T2CON.6 EXF2 Timer/counter 2 external flag.This bit is set to "1" when the T2EX timer/counter 2 externalcontrol signal level is changed from "1" to "0" while EXEN2 = "1".This flag serves as the timer interrupt 2 request signal. If an interruptis generated, EXF2 must be reset to ;'0" bY,software.--T2CON.7 TF2 Timer/counter 2 carry flag.This bit is set to "1" by a carry signal when timer/counter 2 is in16-bit auto reload mode or in capture mode.This flag serves as the timer interrupt 2 request signal. If an interruptis generated, TF2 must be reset to "0" by software.328

--------------------. MSM80C154/83C154 •LIST OF INSTRUCTIONSLIST OF INSTRUCTION SYMBOLSAABACBCDPTRPCRrSPANDORXOR+x/(X)((X))#@; Accumulator; Register pair; Auxiliary carry flag; Arithmetic operation register; Carry flag; Data pointer; Program counter; Register indicator (r ; 0 - 7); Stack poi nter; Logical product: Logical sum: Exclusive OR: Addition: Subtraction: MultiplicationDivisionDenotes the contents of XDenotes the contents of address determined by the contents of XDenotes the immediate dataDenotes the indirect addressEqualityNon equality: Substitution: Substitution: Negation: Smaller than ; Larger thanbit address : RAM and the special function register bit specifier address (bo - b,)code address: Absolute address (Ao - A, s)data Immediate data (10 - I,)relative offset: Relative jump address offset value (Ro - R,)direct address: RAM and the special function register byte specifier address (a o - a,)329

e MSM80C154/83C154 e-------------------'--MSM80C154/MSM83C154 INSTRUCTION TABLE~0 1 2 3 4 5 6 70000 0001 0010 0011 0100 0101 0110 0111II"'" AJMP0LJMPINCNOP address 11RR A INCAINC @RO INC@Rl0000address 16direct(Page 0).......ACALL1 JBC bit, LCALL DECi address 11 dd 16 . RRC A DEC A DEC @RO DEC @Rl0001 rei.... (PageO) .:.. ress idirect2 JB bit, I AJMP IADD A, ADDA, ADDA, ADDA,RET RLA0010 rei i address 11 l I#data direct @RO @Rl...(Page 1) !3 JNB bit,0011 reiACALL I,..address 11(Page 1)III..RETIRLC AADDC A, AD DC A, ADDC A, ADDC A,I #data direct @RO @Rl4 JC bit, ' AJMP ,.. ORL I ORL "'II'" ORL A ORLA, ORLA, ORLA,0100 rei lddress 11 d· t A I direct, #d t '(Page 2) , Irec, ... #data a aIdirect @RO @Rlr ACAL~ I ANL "'II'"II"'"50101 ~ (Page 2) I direct, A l #data I #data direct @RO @RlJNC rei I address 11 , ANL i direct, i ANL A, ANLA, ANLA, ANLA,60110 address 11 I d· t A direct, I #d t 'I (Page 3) i Irec, #data. a 'l. direct @RO @RlJZ reir AJMP r XRL I XRL T XRLA XRLA, XRLA, XRLA,""~" tACALLr" . rMOV,..7JNZ rei 'address 11. ORL C, JMP MOV A, MOV @RO, MOV @Rl,direct,0111 , (Page 3) ~ bit :'A+DPTR I #data ...#data #data #datar8 I AJMP ANL C MOVC A I I MOV MOV MOVSJMP rei address 11 b·t' I @A+PC' I DIV AB ,direct 1, direct, direct,1000 ~ (Page 4).... I l "! I ...' direct 2 @RO @RlI MOV ACALL r; . I r. SUBB A, SUBB A, SUBB A,1~01 IDPTR address 11 I MOV bit, MOVC A, ! SUBB A,#data 16 l(page 4) lilt.. C ~A+DPTR #data direct @RO @Rlr AJMPII"'"AMOV C, INCMOV @RO, MOV @Rl,ORA L C, bit: address 11MUL AB1010 bit DPTR direct directB1011l (Page 5)... ... ... ....r ,..ACALL i CJNE A, CJNE A, CJNE @RO~ CJNE @Rl,,(Page 5)~ rei rei lit.. rei rei...ANLC,bit I address 11 i CPL bit CPL C I #data, I direct, #data, #data,II"'"AJMPC PUSHXCH A, XCH A, XCH A,address 11 CLR bit CLR C1100 directI SWAP A direct @RO @Rl(Page 6) -r--~-~- --~~--ACALLDJNZD POPXCHD A, XCH A,address 11 I SETB bit SETB C DAA direct,1101 direct(a) RO @Rl(Page 6)III.. rei_.f---"-~.-II"'"E MOVX A, AJMP MOVX A MOVX A,MOVA, MOVA, MOVA,CLR A1110 @DPTR address 11 (al RO ' (a) Rl direct @RO @Rl(Page 7)... --ACALLF MOVXMOVX MOVXaddressMOV MOV MOV11CPL A1111 @DPTR,A (wRO, A (a' Rl, A direct, A @RO,A @Rl,A~~ag: 7)- ...~ "~--~ ----~ "-~~- '-----2 BYTE 3 BYTEMNEMONIC2 CYCLE 4 CYCLE330

--------------------. MSM80C154/83C154 •~--r------,------'---------I""'H L 8 9 AIH ~ 1000 1001 1010o0000INC ROINC RlINC R2.__.._-_.._- _. __.._- .-,----,----,--------,BC o EF1011 1100 1101 1110 1111INC R3INC R4INC R5INC R6INC R710001DEC RODEC RlDEC R2DEC R3DEC R4DEC R5DEC R6DEC R720010ADD A,ROADDA,RlADD A,R2ADD A,R3ADDA,R4ADD A,R5ADD A,R6ADD A,R73 AD DC A, ADDC A, AD DC A, ADDC A, AD DC A, AD DC A, ADDC A, ADDC A,0011 RO Rl R2 R3 R4 R5 R6 R74 DRL A, ORL A, ORL A, ORL A, ORL A, II ORL A, ORL A, ORL A,0100 RO Rl R2 R3 R4 R5 i R6 i R750101ANL A, ANL A,RO RlANL A,R76011070111XRL A, XRL A,RO Rl"MOV RO,,.#dataMOV Rl,#dataXRLA, XRL A, XRL A, I XRL A,I, XRLA,R2 R3 R4 I R5 R6IMOV R2, "MOV R3, ! MOV R4, r MOV R5, r MOV R6,#data #data #data: #data I #dataXRL A,R7MOV R7,#data'"MOV8 d'1000 Irect,.... RO9 SUBB A,1001 ROMOV MOV" MOVdirect, direct, direct,Rl R2.... R3SUBB A, SUBB A, SUBB A,Rl R2 R3MOV r MOV r MOV MOVdirect, I direct I direct, direct,R4 ~ R5 '. ~ R6 R7SUBB A, • SUBB A, I SUBB A, SUBB A,R4 R5 R6 R7-A "MOV RO, I""MOV Rl, MOV R2, "MOV R3'I MOV R4, rMOV R5, MOV R6, MOV R7,1010 direct direct : direct direct direct:. direct direct directB1011.... .................CJNE RO~ CJNE Rl, CJNE R2, CJNE R31 CJNE R41 CJNE R5, CJNE R6~ CJNE R7;#data, #data, #data, #data, i #data, . #data, #data, #data,.... rei .. rei rei.... rei ~ ; rei ... rei .... rei reiC XCH A, XCH A, XCH A, XCH A, I: XCH A, I XCH A, XCH A, XCH A,1100 RO Rl R2 R3 R~R5 R6 R7~--_,,~---~---__ ~----~,.r---~,,~o DJNZ RO DJNZ Rl DJNZ R2, DJNZ R3, DJNZ R4'I DJNE R5, DJNE R6, DJNE R7,1101 rei rei rei rei rei rei rei rei.... .... ........ ....E MOV A, 'MOV A, MOV A, MOV A, MOV. A, MOV A, MOV A, MOV A,1110RO Rl R2 R3 R4 R5 R6 R7F MOV RO, MOV Rl, MOV R2, MOV R3, . MOV R4, MOV R5, MOV R6, MOV R7,1111 A A A A A A A A331

• MSM80C154/83C154 .---------------------INSTRUCTION SET DETAILS.. I nstruction Codea.> Mnemonic Bytes Cycles Descriptiont- 0 7 D. Os D. D. 0, 0,00ADDA, Rr 0 0 1 0 1 r, r, ro 1 1 (AC), (OV), (C), (A) - (A)+(RrlADD A, direct 0 0 1 0 0 1 0 1 2 1 (AC), (OV), (Cl, (A) - (A)+(directa7 a. as a. a3 a, a, aoaddress)ADD A,@Rr 0 0 1 0 0 1 1 ro 1 1 (AC), (OV), (C), (A) - (A)+((Rrl)ADD A, #data 0 0 1 O. 0 1 0 0 2 1 (AC), (OV), (C), (A) - (A)+#data17 I. Is I. 13 I, I, 10ADDC A, Rr 0 0 1 1 1 r. r, ro 1 1 (AC), (OVI. (C), (A) - (A)+(C)+(RrlDADDC A, direct 0 0 1 1 0 1 0 1 2 1 (AC), (OV), (C), (A) - (A)+(C)+(directa7 a. as a. a3 a. a, aoaddress)..ADDCA,@Rr 0 0 1 1 0 1 1 ro 1 1 (AC), (OV), (Cl, (A) - (A)+(C)+«Rrl)c:0ADDC A, #data 0 0 1 1 0 1 0 0 2 1 (AC), (OV), (Cl, (A) +- (A)+(C)+#data'£:lI, I. Is I. I. I. I, 10~.!: SUBB A, Rr 1 0 0 1 1 r. r, ro 1 1 (AC), (OV), (C), (A)

--------------------. MSM80C154/83C154 •INSTRUCTION SET DETAILS (CaNT.).. I nstruction Codec.Mnemonic Bytes Cycles>DescriptionI- D, D. Ds D. D3 D. D, D.I:0';;'" tD~8",2RR A 0 0 0 0 0 0 1 1 1 1 Accumulator@]C:I-I-I-I-I-I-I;j0 0.. ::l RRC A 0 0 0 1 0 0 1 1 1 1 Accumulator-'Ii '" ....::l I:E'-::lUU«f"H:1-1-1-1-1-1-1;1SWAP A 1 1 0 0 0 1 0 0 1 1 (A. - ,) ... (A. - 3)INC A 0 0 0 0 0 1 0 0 1 1 (A) +- (A)+lINC Rr 0 0 0 0 1 r. r, r. 1 1 (Rd +- (Rd+lINC direct 0 0 0 0 0 1 0 1 2 1 (direct address) +- (direct address)+la, a. as a. a3 a. a, a.I:..E INC @Rr 0 0 0 0 0 1 1 r. 1 1 ((Rd) +- ((Rd)+le&!..INC DPTR 1 0 1 0 0 0 1 1 1 2 (DPTR) +- (DPTR)+l~I:.. DEC A 0 0 0 1 0 1 0 0 1 1 (A) +- (A)-lEe ,DEC Rr 0 0 0 1 1 r, r,ur. 1 1 (Rd +- (Rd-lI:- DEC direct 0 0 0 1 0 1 0 1 2 1 (direct address) +- (direct address)-la, a. as a_ a3 a. a, a.DEC @Rr 0 0 0 1 0 1 1 r. 1 1 ((Rd) +- ((Rr))-lANL A,Rr 0 1 0 1 1 r. r, r. 1I1 (A) +- (A) AND (RdIANL A, direct 0 1 0 1 0 1 0 1 2I 1 (A) +- (A) AND (direct address)a7 a. as a. a3 a. a, a.ANL A,@Rr 0 1 0 1 0 1 1 r. 1 I 1 (A) +- (A) AND ((Rd)IIIANL A, #data 0 1 0 1 0 1 0 0 2 , 1 (A)

• MSM80C154/83C154 .---------------------,----INSTF)UCTION SET DETAILS (CONT.)., I nstruction Codec.> Mnemonic Bytes Cycles Description-I-0, D. 0, 0_ D. O2 0 1 DoORL direct, A 0 1 0 0 0 0 1 0 2 1 (direct address) +- (direct address) ORa, a. a, a_ a. a. al ao (A)ORL direct, 0 1 0 0 0 0 1 1 3 2 (direct address) +- (direct , address) OR#data a, a. as a. a. a. al ao #data'" e:I, I. I, I. I. I. II 10.gu XRL A, Rr 0 1 1 0 1 r. rl ro 1 1 (A) +- (A) XOR (Rd21;;XRL A, direct 0 1 1 0 0 1 0 1 2 1 (A) +- (A) XOR (direct address).!:e: a, a. a, a. a. a. al ao.;:; 0~XRL A,@Rr 0 1 1 0 0 1 1 ro 1 1 (A) +- (A) XOR ((R'd)Q)c.0 XRL A, #data 0 1 1 0 0 1 0 0c;; I, I. I, I. I. I. II 102 1 (A) +- (A) XOR #data.~Cl0 XRL direct, A 0 1 1 0 0 0 1 0 2 1 (direct address) +- (direct address)...Ja, a. a, a_ a. a. al ao XOR(A)XRL direct, 0 1 1 0 0 0 1 1 3 2 (direct address) +- (direct address) XOR#data a, a. a, a. a. a. al ao #dataI, I. 15 I_ I. I. II 10'" MOV A, #data 0 1 1 1 0 1 0 0 2 1 (A) +- #datae:0I, I. I, I_ I. I. II 10.;:;u2 MOV Rr, #data {) 1 1 1 1 r. rl ro 2 1 (Rd +- #data1;; I, I. I, I_ I. I. II 10e:Cle: MOV direct, 0 1 1 1 0 1 0 1 3 2 (direct address) +- #data'E #data a, a. a, a. a. a. al aolIA I; I. I, I. I. I. II 10l!l'tl '" MOV @Rr, #data 0 1 1 1 0 1 1 ro 2 1 (Rd) +- #data., I, I. I, I_ I • I. II 10.... S!a! MOV DPTR, 1 0 0 1 0 0 0 0 3 2 (DPTR) +- #data 16E #data 16 II; h_ II. III 111 110 I. I.E I, I. I, I. I. I. II 10-eLR e 1 1 0 0 0 0 1 1 1 1 (e) ..... 0'" e:.;:; 0uSETB e 1 1 0 1 0 0 1 1 1 1 (e) +- 1ePL e 1 0 1 1 0 0 1 1 1 1 (C) +- (e)2 ANL C, bit 1 0 0 0 0 0 1 0 2 21;; b, b. b, b_ b. b. bl bo.!:(e) +- (e) AND (bit address)e:ANL e.lbit 1 0 1 1 0 0 0 0 2 2 (e) +- (e) AND (bit address).gb, b. b, b. b. b. b l bo~Q)c. ORL C, bit 0 1 1 1 0 0 1 0 2 2 (e) ..... (e) OR (bit address)0Clb, b. b, b. b. b. b l bo~_.-~. ORL e.lbit 1 0 1 00 0 0 0b, b. b,- b. b. b. bl bo2 2 (e) +- (e) OR (bit address)'"U -MOV C, bit 1 0 1 0 0 0 1 0 2 1 (C) +- (bit address)b, b. b, b_ b. b. bl bo

----------------------. MSM80C154/83C154 •INSTRUCTION SET DETAILS (CONT.)., I nstruction Code0.> Mnemonic Bytes Cycles Descriptiont- D, D. D, D. D3 D2 D, DoMOV bit, C 1 0 0 1 0 0 1 0 2 2 (bit address) +- (C)1:>, b. b, b. b 3 b2 b, boSETS bit 1 1 0 1 0 0 1 0 2 1 (bit address) +- 1c: on b7 b. b, b. b3 b2 b, boo c:',fj 0"'.- ~ ... CLR bit 1 1 0 0 0 0 1 0 2 1 (bit address) +-.,U0c.:::>b 7 b. b, b. b3 b2 b, b o.~ ~CPL bit 1 0 1 1 0 0 1 0 2 1 (bit address) +- (bit address)aJ .-b7 b. b, b. b3 b 2 b, boMOV A,Rr 1 1 1 0 1 r2 r, ro 1 1 (A) +- (RrlMOV A, direct 1 1 1 0 0 1 0 1 2 1 (A) +- (direct address)a7 a. a, a. a3 a2 a, aoMOV A,@Rr 1 1 1 0 0 1 1 ro 1 1 (A) +- ((Rrl)on MOV Rr, A 1 1 1 1 1 r 2 r, r 0 1 1 I(Rrl +- (A)c:.;; 0MOV Rr,direct 1u0 1 0 1 r 2 r, ro 2 2 (Rrl +- (direct address):::> a7 a. a, a. a3 a2 a, ao~.!: MOV direct, A 1 1 1 1 0 1 0 1 2 1 (direct address) +- (A)~.,a7 a. a, a • a3 a2 a, ao't;c:-----~ MOV direct, Rr 1 0_ 0 0 1 r2 r, ro 2 2 (direct address) +- (Rr)a7 a. a, a. a3 a2 a, ao...~'"0 MOV direct, 1 0 0 0 0 1 1 ro 2 2 (direct address) +- ((Rrl)@Rr a7 a. a, a. a3 a2 a, ao., on"oc:MOV @Rr,A 1 1 1 1 0 1 1 ro 1 1 ((Rrl) +- (A)MOV @Rr, 1 0 1 0 0 1 1 ro 2 2 ((Rrl) +- (d irect address))direct a7 a. as a. a3 a2 a, aoMOVCA, 1 0 0 1 0 0 1 1 1 2 (A) +- ((A)+(DPTR))8.2 @A+DPTRc:ot;,;; '" :::>MOVC A,@A+PC 1 0 0 0 0 0 1 1 1 2 (PC) +- (PC) + 1§ ~ (A) +- ((A) + (PC))u·-., XCH A, Rr 1 1 0 0 1 r2 r, ro 1 1 (A) "" (Rr)Olonc: c:XCH A, direct 1 1 0 0 0 1 0 1 2 1 (A) "" (direct address).

eMSM80C154/83C154e----------------------------------------INSTRUCTION SET DETAILS (CONT.)., I nstruction CodeCo> Mnemonic Bytes Cycles DescriptionI- D, D. Ds D, D3 D2 D, DoPUSH direct 1 1 0 0 0 0 0 0 2 2 (SP)

-~------------------. MSM80C154/83C154 •INSTRUCTION SET DETAILS (CONT.)MnemonicI nstruction Code1-------------JBvtes ev ei•0, D. 0, D. D. D. 0 , D.DescriptionCJNE Rr. #data. 1 0 1 1 1 r2 rl ro 3 2 (PC) +- (PC)+3rei I, I. I, I. I. I. II 10IF ((Rr)) *#dataR,R.R,R.R.R.R,R.THEN(PC) +- (PC)+relative offsetIF ((Rr)) < #dataTHEN(C) +- 1ELSE(C) +-0CJNE @Rr.#data. rei1 0 1 1 0 1 1 r. 3I, I. I, I. I. I. I, I.R, R. R, R. R. R. RI R.2 (PC) +- (PC)+3IF ((Rr))*#dataTHEN(PC) +- (PC)+relative offsetIF ((RrI) < #dataTHEN(C) +- 1ELSE(C) +-0en

• MSM80C154/83C154 .--------------------INSTRUCTION SET DETAilS (CONT.)., Instruction Codec. Mnemonic Bytes Cycle>DescriptionI- 0, D. 05 D. 0 3 D. 0, D~..c: JBC bit, reI 0 0 0 1 0 0 0 0 3 2 (PC) +- (PC)+3..cOu·- b, b. bs b. b 3 b. b, bo IF (bit address) = 1. c tJ 'ca:::J ' R,R.RsR4 R3 R• R I Ro THEN'- '-eDt;(bit address) +- 0.!: (PC) +- (PC)+relative offset~ MOVX A,@Rr 1 1 1 0 0 0 1 fo 1 2 (A) +- ((Rr)) EXTERNAL RAM0 ..E c:MOVXA,@DPTR 1 1 1 0 0 0 0 0 1 2 (A) +- ((DPTR)) EXTERNAL RAME'~-:::Jca '-Et; MOVX@Rr,A 1 1 1 1 0 0 1 ro 1 2 (Rr) +- (A) EXTERNAL RAM.....,-c:x MOVX@DPTR,A 1 1 1 1 0 0 0 0 1 2 ((DPTP)) +- (A) EXTERNAL RAMw..c: NOP 0 0 0 0 0 0 0 0 1 1 (PC) +- (PC)+1Q)";:;'- 0..cu... :::J0'- t:.!:338

-------------------. MSM80C154/83C154 •ELECTRICAL CHARACTERISTICSAbsolute Maximum RatingsParameterSymbolConditionsRatingUnitSupply voltageVeeTa = 25 DC-0.5 -7VInput voltageStorage temperatureVITstgTa = 25 DC-0.5 - Vee + 0.5-55 - + 150VDCOperational RangeParameterSymbolConditionsRatingUnitSupply voltage Vee *1 fosc = DC-16 MHzMemory hold voltageAmbient temperatureVeeTa2.5 - 62-6-40-+85*1: 2.5 V .;; Vee < 4 V DC characteristics will be specified elsewhere.16 MHz version of MSM83C154 (12 MHz < XTAL 1·2.;; 16 MHz) is being developed.DC Characteristics(VCC =5V±10%, Ta =-40to +85 D C)Parameter Symbol Conditions Min. TVp. Max. UnitVVDCMeas·uringcircuitInput Low Voltage VIL -0.5 0.2 VCC-O.1 VInput High Voltage VIH Except XTALl and 0.2 VCC +0.9 VCC + 0.5 VRESET. Input High Voltage VIHI XT AL 1 and RESET' 0.7 VCC VCC + 0.5 VOutput Low Voltage VOL IOL = 1.6mA 0.45 V(PORT 1,2,3)Output Low Voltage Vall IOL =3.2 mA 0.45 V(PORT 0, ALE, PSEN)Output High Voltage VOH IOH =-60jJA 2.4 V(PORT 1, 2, 3) VCC = 5 V ± 10%1IOH = -30/JA 0.75 VCC VIOH = -10jJA 0.9 VCC VOutput High Voltage VOHI IOH = -400jJA 2.4 V(PORT 0, ALE, PSEN) VCC=5V± 10%IOH=-150/JA 0.75 VCC VIOH= -40/JA 0.9 VCC VLogical 0 Input Current IlL VI=0.45V -10 -200 jJA(PORT 1,2, 3)Logical 1 to 0 Transition ITL VI=2.0V -500 jJACurrent (PORT 1,2,3)Input Leakage Current III VSS

• MSM80C154/83C154 .--------------------Maximum Power Supply CurrentNormal Operation ICC (mAlMaximum Power Supply CurrentIdle Mode ICC (mAlVee 4V 5VFreq0.5 MHz 1.6 2.23.5 MHz 4.3 5.78MHz 8.3 1 112 MHz 12 166V37.51 420Vee 4V 5VFreq0.5 MHz 0.6 0.93.5 MHz 1.1 1.68 MHz 1.8 2.712 MHz 2.5 3.76V1.22.23.75*1: 2.5 V';; Vec< 4 V De characteristics will be specified elsewhere.Maximum Power Supply CurrentNormal Operation ICC (mAlMaximum Power Supply CurrentIdle Mode ICC (mAlVee 4.5 V 5VFreq.1.2 MHz 2.0 2.38MHz 10 1112 MHz 14 1616 MHz 18 205.5 V2.612.51823Vee 4.5 V 5VFreq.1.2 MHz 1.4 1.58 MHz 2.3 2.712 MHz 3.0 3.716 MHz 4.0 5.05.5 V1.63.25.06.00Measuring Circuits+VeeVIH MI-'I-' ::l~ ::l0 II..1=~2 ::lVIL 02I-'::l1=::l0~-=- - -=-"::""-=- -=- -= -=34VIH I-' I-'::l ::lII..1=~ ::lVIL0Vss~-=- =1VIHVILI-'I-'::l::lII..1=~ ::l0Vss=~Note 1. Repeated for specified input pins.2. Repeated for specified output pins.3. Input logic for specified status.340

--------------------. MSM80C154/83C154 •External Program Memory Access AC Characteristics(VCC = 5 V ± 20%, VSS= 0 V, XTAL1·2 = 12 MHz, Ta = -40°Cto 85°CVCC = 5 V ± 10%, VSS = 0 V, 12 MHz < XTAL1·2 .;;16 MHz, Ta = _40°C to 85°CPORT 0, ALE, and PSEN connected with 100 pF load, other connected with 80 pF load)Parameter Symbol 16 MHz clockRatingsVariable clock fromDC to 16 MHzMin. Max. Min. Max.XTAL 1 ·2 Oscillator Peripd tCLCL 62.5 62.5 nsALE Pulse Width tLHLL 85 2tCLCL-40 nsAddress Valid to ALE Low tAVLL 18.5 1tCLCL-44 nsAddress Hold After ALE tLLAX 27.5 1tCLCL-35 nsLowALE Low to Valid Instr In tLLlV 150 4tCLCL-100 nsALE Low to PSEN Low tLLPL 32.5 1tCLCL-30 nsPSEN Pulse Width tPLPH 152.5 3tCLCL-35 nsPSEN Low to Valid Instr tPLIV 82.5 3tCLCL-105 nsInInput Instr Hold After tpXIX 0 0 nsPSENInput Instr Float After tPXIZ 42.5 1tCLCL-20 nsf:iSENPSEN to Address Valid tPXAV 42.5 1tCLCL-20 nsAddress to Valid Instr In tAVIV 207.5 5tCLCL·105 nsAddress Float to PSEN tAZPL 0 0 nsLowUnitExternal program memory read cycle341

• MSM80C154/83C154 .-----...,----------------External Program Memory Access AC Characteristics(Vcc = 5 V ± 20%, VSS = 0 V, XTAl1·2 = 12 MHz, Ta = -40°C to 85°CVCC=5V±10%, VSS=OV, 12MHz

--------------------. MSM80C154/83C154 •External data memory read cycleExternal data memory write cycletWHLHALEc.j.,--- tWLWH1---+--- tOVWHtOVWxPORTODATA IACC)AS - A15 PCH P2.0 - P2.7 DATA or AS - A15 DPH AS - A15 PCH343

• MSM80C154/83C154 • --------------.,-------Serial Port (1/0 Extension Mode) AC CharacteristicsvCC = 5 V ±20%, vss = 0 V, XTAL1'2 = 12 MHz, Ta = -40°C to 85°CVCC = 5 V ±10%, Vss =0 V, 12 MHz < XTAL1·2';; 16 MHz, Ta = -40°Cto 85°CParameter Symbol Min. Max. UnitSerial Port Clock Cycle Time tXLXL 12tCLCL nsOutput Data Setup to Clock Rising Edge tQVXH 10tCLCL-133 nsOutput Data Hold After Clock Rising Edge tXHQX 2tCLCL-75 nsInput Data Hold After Clock Rising Edge tXHDX 0 nsClock Rising Edge to Input Data Valid tXHDV 10tCLCL-133 nsMACHINE CYCLEALESHIFT CLOCKrtOVXH~rtXHOX IOUTPUT DATA \ X~-----vX~-_-_-_-_~~X~r:::::JX~r~~~-_-J~Xr~-_-_-_-_~~xC:::::)X::::::J/r---~tXHDV~ ~ rtXHDXINPUT DATA AI. AL AL ALI AI. AL ALI AI.344

---------------------. MSM80C154/83C154 •=x.,...,...-------...., ,..----AC Characteristics Measuring Conditions1. Input/output signalVOHVOH VIH VvllHLVTEST POINT -/\.VOL _ VIL '-----VOL2. Floating* The input signals in AC test mode are either VOH (logic ",")or VOL (logic "0") input signals where logic "'" correspondsto a CPU output signal waveform measuring point in excess ofVIH. and logic "0" to a point below VIL.VOH-----.I-',VIH/VOL ___ J,'-VILFloating* The port 0 floating interval is measured from the time theport 0 pin voltage drops below VIH after sinking to GND at2.4 mA when switching to floating status from a "'" output.and from the time the port 0 pin voltage exceeds VIL afterconnecting to a 400 p.A source when switching to floatingstatus from a "0" output.XTAL 1 External Clock Input Waveform ConditionsParameter Symbol Min.asci lIator F req. ,/tCLCL DCHigh Time tCHCX 20Low Time tCLCX 20Rise TimetCLCHFall TimetCHCLMax.'62020UnitsMHznsnsnsnsEXTERNAL CLOCK DRIVE WAVEFORMNCXTAL2EXTERNALOSCILLATOR-------------------;XTALlSIGNALVSS345

OKI serniconc:t..-ctorMSM85C154VSM83C154 PIGGY BACKGENERAL DESCRIPTIONThe MSM85C154 is a device whose built-in ROM is replaced by external EPROM using the piggybackmethod. External EPROM capacity is up to 16K bytes. It can be used for evaluation of programsfor MSM83C154.INSTALLATION METHOD FOR EXTERNAL ROM* The MSM85C154VS pin layout of bottom side is the same as the pinlayout for MSM83C154-XX RS.346

PROGRAM DEVELOPMENTSUPPORT SYSTEMS

EASE40 PROGRAM DEVELOPMENT SUPPORT SYSTEMfor theOLMS40 Series 4-Bit, 1-Chip MicrocontrollerEASE40 PROGRAM DEVELOPMENT SUPPORT SYSTEMThe OKI EASE40 Program Development Support System designed for use with the CMOS 4-bit,1-chip microcontrolier OLMS40 Series consists of the MPB400 (evaluation board) and theMPB400DS (key & display board), plus a number of EASE40 microcontroller interface boards. Thesecomponents can also be connected by MUL TlBUS interface or serial I/O interface to the "80 series"of development tools or serial I/O terminal units for even more efficient program development.• Since the MPB400 includes a MUL TIBUS interface, it can be connected online to "80 series" developmentsystems equipped with an existing MUL TIBUS interface to enabie direct use of the system console andI/O units.• With an MPB401 connected to the MPB400, online connections are also possible to serialinterface systems (such as the if800 personal computer).• A floppy disk based assembler/debugger is available for use in online type systems. (CP/M"",ISIS-II base)Note.: (CP/M® is the registered trademark of Digital Research Inc. (USA).ISIS-II and MUL TIBUS are registered trademarks of Intel Corp (USA).o349

• EASE40 .---------------------------SYSTEM CONFIGURATION[1] SERIAL INTERFACE TYPESoeNlMPB401il80D OKI personalcomputerNote: 1. Where "80 series" developmentsystems other than the if800 areused, the system must be capableof using CP/M.2. The MPB401 is connecteddirectlytothe MPB400 via asocket.[2] BUS INTERFACE TYPESMPB400DSeN1MPB400CN2FEATURESThe serial interface type employs serial interfaceequipped development tools available on themarket or personal computers, together with theMPB400 board and MPB401.HOST COMPUTER REQUIREMENTS1. CP/M-80 version 2.0 or 2.2 must be operable asthe operating system.2. The host computer memory capacity must be largeenough to operate at least 52K bytes of CP/M.3. Interface must be RS232C, TTL, or 20 mA currentloop.4. The RS232C serial port must be accessiblewhen the CP/M system calls function No.6(direct console 110), on condition that alogical device CON: is assigned to a physicaldevice TTY.Oki personal computers if800 model 20 andmodel 30 are standard host computers whichsatisfy these requirements.FEATURESBus interface types employ MUL TlBUS equippeddevelopment tools available on the market, e.g.,the MPB400, and MPB400DS. Use of an FDDunit (floppy disk drive) which the developmentsystem has as standard equipment, enablesdisk base editing, assembling, and debugging.When debugging especially, a disk based"debugger" enables loading, excuting andcorrecting of users' application programs from adevelopment system console.MUl TIBUS equipped "80series" development system(Intel: MD5 SystemDSCe System)Note: For Bus interface types, anonline/offline switch located onMPB400DS is set to "online"position.HOST COMPUTER REQUIREMENTS1. Intel 8080A microprocessor or equivalent processoris used as the CPU.2. Intel MUL TIBUS or equivalent bus system isused.3. ISIS-II or CP/M-80 msut be !operable as theoperating system.4. 00 is not used as the 8080A (or equivalent)microprocessor I/O address.350

-----------------------------------------------------. EASE40 •[3] FIELD DEBUGGING TYPESUser's applicationcircuitFEATURESField de,bugging types are used for final field evaluationof application circuits and programs after programdebugging with serial interface or bus interface typeshas been completed. The small and compact MPB202board used for this purpose is equipped with a socketfor program EPROMs.MPB202[4] OLMS40 SERIES EVALUATIONUser's applicationcircuitFEATURESThe dedicated boards indicated in the diagramare required for a program evaluation of theOLMS421 or OLMS422 microcontrolier.Dedicated boardMPB421 (for OLMS421)orMPB422 (for OLMS422)MPB400orMPB202351

• EASE40 .,-----------------------------------------------------ASSEMBLERASM40 is a floppy disk based high-performance assembler which operates under CP/M and ISIS-II.This assembler is used to translate source files generated on disk by using an editor (available on the market),thereby generating object files (Intel HEX format), assembly list files and symbol files in the specifieddevices.LIST OF PSEUDO-INSTRUCTIONSFEATURES1. Free descriptive format source files2; Enables description of up to nine typesarithmetic expressions in the source programoperand field3. Symbol file generation capacity4. Six types of pseudo-instructions available5. A type setting pseudO-instruction enables checkingthe limitation of basic instruction sets for eachOLMS40 microcontroller.PseudoinstructionEQUORGENDNSEFunctionAssignment of operand value to name.1 •Setting of program start addressIndication of end of programSetting of 0 in the 4 lower order bits ofthe assembler location counter, andaddition of 16. The NOP instruction isassigned to blank areas where nomachine language instruction has beenassigned.TYPIndication of the OLMS40 series typeIJ352

-----------------------------------------------------'. EASE40 •DEBUGGERThe EASE40 debugger can be used for effective debugging in both serial interface and bus interfacetype systems.FEATURESEXAMPLE OF USE OF COMMANDSLOAD~H~B:TEST.HEX1. Simple input format for debugging commandsentered from the console of the connectedLIST~:Fl:LIST1.001development tool (personal computer)DEFINE~.STARTalAC2. Efficient loading/saving and display/change of REMOVE~.JOBI •. END2object codesURAM~O~TO~lFF3. Real"time execution and step executionPC=7894. Display/change of microcontroller contentsURAM6100=4S649A125. Use of assembler symbols permitted (only inbus interface types)GO~URAM~FRO~\A12 3~T I LL~PC=7 A4~'r.t 0GO~TILL~PF='STEP~FROM~500"'COUNT~30VERIFY~O~A:SAMPL2.0DJ~UROM~400~TO~7FFSAVE~:Fl:JOB1.002~O~TO~7FFCommand nameLOADLISTDEFINEREMOVEDisplayChangeESETEXITGOSTEP@VERIFYSAVECommand input formatLOAD [6. H/O] 6. Path name [6. EXT]LIST 6. Pathname/OFFDEFINE 6. Symbol ± exprREMOVE 6. Symbol [, Symbol, ..... ]/SYMBOLSKeyword [6. address]Keyword = data'refKeyword 6. addr = [, data, data ..... , data]RESETEXITGO [6. URAM/UROM] [6. FROM 6. addr·exp][6. TILL 6. PC = 1 addr·exp [6. & n]] [6. ASM]GO [6. URAM/UROM] [6. FROMoaddr·exp][6. TILL 6. Port·exp = data·exp] [6. ASM]STEP [6. URM/UROM] [6. FROM 6. addr·exp][6. COUNT 6.n][ 6.ASM]@VERIFY [6. H/O] 6. Pathname [6. EXT] [6. URAM/UROM] [address]SAVE [6. H/O] 6. Path name [6. URAM/UROM] [address]o6. ..... Space, [ ... ] ..... May be omitted, I ..... Slash denoting "or".353

e EASE40ee---------------------------------------------------DEBUGGER COMMAND SAMPLESIIDB400« DB400 »OLMS40 SERIES ON LINE DEBUGGERVERS 1 . 3*LOAD A:SAMPLl.HEX*IB« INITIAL BUFFER »F E D C B A 9 8 7 6 5 4 3 20: 0 0 0 0 0 0 0 0 0 0 0 0 0 01 : 0 0 0 0 0 0 0 0 0 0 0 0 0 02 : 0 0 0 0 0 0 0 0 0 0 0 0 0 03 : 0 0 0 0 0 0 0 0 0 0, 0 0 0 04 : 0 0 0 0 0 0 0 o ,0 0 0 0 0 05 : 0 0 0 0 0 0 0 0 0 0 0 0 0 06 : 0 0 0 0 0 0 0 0 0 0 0 0 0 07 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0RW=O RX=O RY=O RZ=O XCH=O A=OACC=O CY=O DPH=O. D PL=O PP=OPF=O PG=O*GO URAM FROM 7A1 TILL PC=7CFMODE: I B TO FB Y/N/E ? YPC=07CF 74 PA=F PB=F PD=CPC=07CF 74 PA=F PB=F PD=O*GO FROM 7Al TILL PF=9MODE: I B TO FB Y/N/E ? NMODE=NON TO FBPC=07CF 74 PA=F PB=F PD=F*FB« FINAL BUFFER »F E D C B A 9 8 7 6 5 4 3 20: 0 0 0 0 0 0 0 0 0 0 0 01 : a a a 0 0 0 a a a 02 : 0 a 0 0 0 0 a a a a 0 03 : 0 a 0 0 a 0 0 0 0 0 a a 4 : 0 0 a a 0 0 0' 0 a a 0 5 : 0 0 a 0 0 a 0 0 6 : a a a a 0 0 0 a 0 a a a7 : 0 F * * 9 E 4 F a a 0 0 a 0RW=F RX=4 RY=E RZ=9 XCH=* A=*ACC=9 CY=l DPH=2 DPL=O PP=*PA=F PB=F PD=F PE=F PF=9 PG=OPK=B PH=2 CIN=O INT=l*STEP FROM 7A1 COUNT 6PC=O 7 A l' 37,0 0PC=0700 ACPC=0702 ADPC=0704 65PC=0705 26PC=0706 37A3*EXITPA=F PB=F PD=CPA=F PB=F PD=CPA=F PB=F PD=CPA=F PB=F PD=CPA=F PB=F PD=CPA=F PB=F PD=C1 00 00 00 00 00 00 00 00 0&2PE=5PE=5PE=F1 00 00 aa aa aa aa aa a0 0PE=OPE=OPE=OPE=OPE;'OPE=OPF=O PG=O PK=B PI=APF=O PG=O PK=B PI=APF=9 PG=O PK=B PI=APF=9 PG=O PK=B PI=APF=9 PG=O PK=B PI=APF=9 PG=O PK=B PI=APF=9 PG=O PK=B PI=APF=9 PG=O ·PK=B PI=APF=9 PG=O PK=B PI=A354

---------------------------------------------------eEASE40eSELECTION OF MICROCONTROLLER AND EVALUATION BOARDS/SOFTWAREDedicated boardEvaluation board~-- --~Serial interface type,...-----,MPB401~~----,MS47Dedicated hardwaresimulator___ ~ L ___ ~EVALUATION MICROCONTROLLERSOLMS40 MSM5840 MPB400 board accessoriesOLMS42 MSM5840 MPB400 board accessoriesOLMS421 MSM5840 MPB421 board accessoriesDOLMS422 MSM5840MPB422 board accessoriesSOFTWARESerial interface typeBus interface typeFD40S·CP/MFD40B·ISISPD40B·CP/MAssembler/(serial)debugger CP/M single side single density 8-inchTwo (serial) monitor software EPROMsAssembler/(bus) debugger ISIS-II single sided single density 8-inchTwo (bus) monitor software EPROMSsAssembler/(bus) debugger CP/M single sided single density 8-inchTwo (bus) monitor software EPROMS355

e EASE40 e-----------------------------------------------------MPB400 BoardThe MPB400 board is used for OLMS-40 Seriesmicrocontroiler program generation and evaluation.With the MSM8085A used for control purposes,several system configurations can be achieved incombination with other boards and software.Dimensions: 202 x 305 (mm)MPB401 BoardThe MPB401 board, used together with the MPB400board, consists of interface circuit with the developmentsystem and transfer speed converter unit.Dimensions: 105 x 205 (mm)80 x 115 (mm)DMPB202 BoardThe MPB202 board is equipped with an evaluationmicrocontroiler and 4K bytes of program EPROMsockets. This miniature size board is used effectivelyin mounting evaluations when built into applicationequipment for final testing of debugged programs.Dimensions: 95 x 120 (mm)356

-----------------------------------------------------e. EASE40 •MPB421The MPB421 board has been designed for OLMS-421microcontrolier program evaluation, and is used connectedto the MPB400. This board is equipped withLCD driver circuits and PLA EPROM sockets.Dimensions; 145 x 180 (mm)o357

EASE6400 PROGRAM DEVELOPMENT SUPPORT SYSTEMfor theOlMS-64 SERIES CMOS 4-Bit, 1-Chip MicrocontrollerEASE6400 PROGRAM DEVELOPMENT SUPPORTSYSTEMThe EASE6400 Program Development Support System has been specifically designed for·rapid andefficient program development of Oki's OlMS-64 series of CMOS 4-bit, 1-chip microcontroller.(Target chips: MSM6404, MSM6402, MSM6422, MSM6411, MSM6431, MSM6442 and MSM6408)DFEATURES1. In-circuit emulation when connected to anRS232C interface equipped a host computeror to an input/output device such as a CRTterminal and the EASE8 (option).3. Six types of break conditions (for interruptionof emulation) including execution addressand machine cycle counter.4. EPROM writer (for 2732,' 2732A, 2764) toenable programming, transfer, andverification of user program area contents.5. User program debugging operations directedby debug commands entered from the keyboardof the connected input/output device.6. Program evaluation by use of dedicated evaluationchip (MSM6400E), theret;>y enablingthe same operations to be executed as whenthe MSM6404 chip is used.7. Built-in system diagnostic program.HOST COMPUTER REQUIREMENTS1. Operating system is one of the follows.(1) CP/M®-80 (ver 2.0 or later)memory capacity of the host computermust be sufficient to run at least 52KCP/M.(2) MS-DOS® (ver 1.25, ver2.11)(3) PC-DOS® (ver 1.25, ver2.11)2. At least one RS232C communication port isimplemented.3. Data transfer is performed through RS2:32Ccommunication port using BDOS functioncall 6 on condition that console device isassigned to TTY:.358

--------------------------. EASE6400 •SYSTEM CONFIGURATIONThe EASE6400 Program Development SupportSystem consists of the EASE6400 Emulator (ahigh performance program emulator whichincludes the EASE Host Monitor, the EASE6400Evaluation, and the host computer) and theASM6404 Assembler. With the EASE6400Evaluation connected online to the hostcomputer equipped with an RS232C interface,the system covers all operations from assemblyof the source program through programevaluation and debugging.COMMUNICATION WITH HOSTCOMPUTERICs used• Communication interface MSM82C51A• Driver/receiver -SN75188N, SN75189NTransmission format• 110 to 9600 bps (switchable)• 8 bits, 2 stop bits, non-parity• 7 bits, 2 stop bits, even parity• 7 bits, 2 stop bits, odd parity (switchable)EASE6400Evaluation KitNote: CPIM is a registered trademark ofDigitalResearch Inc. (U.S.A.)• EASE• ASM6400:8I~IoEASE and ASM6404 for PC-DOS, MS-DOS areoptional softwares.D359

• EASE6400 • -------------------'--------'--ASM6400 ASSEMBLERThe ASM6400 is a floppy disk based high-performance assembler which operates on CP/M-80,MS-DOS, or PC-DOS.This assembler is used to translate source files generated on disk by using an editor (available on themarket), thereby generating object files (Intel HEX format), assemble list files, and cross-referencelist files in the specified devices.FEATURES1. Free descriptive format source files2. Capacity to describe up to ten types of operatorsin the source program operand column3. Ability to specify the number of charactersper line and the number of lines per page inassembly list files4. Cross-reference list file generation capacity5. 13 types of powerful pseudo-instructions available6. Object codes where internal page jump instructionsand all page jump instructions are assignedautomatically can be obtained by branch pseudoinstructions7. Control of assembly list file outputs by LISTor NLST pseudo-instructionLIST OF PSEUDO-INSTRUCTIONSPseudoinstructionTYPEQUSETORGENDBFUnctionSpecifies a type of target chipAssignment of operand value to name.Same as EQU pseudo-instruction, butwith redefinition capacitySetting of program start addressIndication of end of programAutomatic conversion to internal page orall page jump instruction after checkingbranch destinationDBDSNSEDATEPAGETITLLISTNLST8-bit data or ASCII character definitionReserves memory area for specifiednumber of bytesSetting of 0 in the 4 lower order bits ofthe assembler location counter, andaddition of 16. The NOP instruction isassigned to blank areas where nomachine language instruction has beenassigned.Insertion of date in assemble list titleExecution of assemble list page feedInsertion of assemble list titleDesignation of assemble list outputInhibition of assemble list output360

-------------------------. EASE6400 •EASE6400 EMULATORConsisting of a host computer and the EASE6400 Program Evaluation Kit, the EASE6400 Emulatorsupports a wide,range of development debugging operations efficiently and effectively. OLMS-64application programs can be debugged without user application circuits just as easily as completedsystems.a) User program executionFEATURES1. Real-time tracing function does not effectexecution timeThe EASE6400 Evaluation Kit incorporates arealtime trace area for 2048 machine cycles.When the tracing for a particular user programarea address has been set, the address,operation code, port, and probe status are tracedeach time the specified address is executed.2. Execution time measurementThe user program execution time can be measuredby using the cycle counter on theEASE6400 Evaluation Kit. (Max. 16,777,215 cycles)This counter can also be used as a pass counterto indicate the number of times a specified addressis executed. And emulation can bestopped after a specified address has been executeda specified number of times.3. Mass storageWith an 8192-bytes of static RAM area in theEASE6400 Evaluation Kit for use as a· userprogram area, there is no problem withinadequate memory area during debugging. And,needless to say, user programs can beloaded/saved from the host computer.Furthermore, with an EPROM writer included onthis board, the user program area contents canbe written into EPROMs,and the EPROMcontents can be read out.4. Ample break functionsThe emulator can suspend (break) program executionby any of the following six break conditions.a) Breakpoint breakBreak upon execution of specified address. (Anyaddress may be specified.)b) Extemal breakBreak by application of external break signal.c) Halt/stop instruction breakBreak by execution of HALT or STOP instruction.d) Trace buffer full breakBreak when overflow of trace area occurs.e) Cycle counter overflow breakBreak when overflow of cycle counter occurs.f) Probe match breakBreak when probe data matches set data.5. Extensive range of debugging commandsIn addition to display/updating of all register, port, andRAM contents, the following commands enableall debugging operations to be executedefficiently,Input format:STP number of instructions, start addressInput of this command results in the specifiednumber of instructions in the user program beingexecuted from the specified address (startaddress).Input format:G start address, break address (n)Input of this command results in the user programbeing executed from the specified address (startaddress). Emulation is subsequently stoppedwhen the specified address (break address) isexecuted n times.Note: Program execution is suspended temporarily eachtime the specified address is executed.Input format:G start address, break address RAM(address-n)Input of this command results in the user programbeing executed from the specified address (startaddress). Emulation is subsequently stopped ifthe contents of the specified RAM address are nwhen the specified address (break address) isexecuted. In this case, too, program execution issuspended temporarily whenever the specifiedaddress is executed.b) Use of floppy disksInput format:LOD filename .Input of this commartd enables the specifiedfile contents (user program) to be loaded intotheEASE6400 Evaluation Kit code memorywhich serves as the OLMS-64 masked ROMarea.Input format:SA V filename start address, end addressInput of this command enables the contents of thespecified range of code memory to be saved atthe specified filename.Input format:DIAG2Input of this command enables execution of commandswithin the specified file.This execution can be suspended temporarily byusing the PAUSE command.361IJ

• EASE6400 • ------------------------c) Instruction executed bit memoryThe EASE6400 Emulator includes an instructionexecuted bit memory which indicates which userprogram addresses have been executed. Programflow can be detennined by examination ofthe contents of this memory.6. Easy to remember command formatTheEASE6400Emuiator debugging commands. consistof command mnemonicS followed by parameters(address or mnemonic).Command mnemonic configurationa) First characterDenotes the function to be executed by theemulator.b) Second and following charactersName of function to be executed by theemulator- that is, MSM6400E evaluationchip or EASE6400 Evaluation Kit register,memory, or port name (abbreviation).Example:* 0 OM O,1F..JII \J I V Iab cdefa: denotes wait for command input from emulatorb: denotes display of contents of specified objectc: data memory (equivalent MSM6400E RAM area)designation .d: start address of contents to be displayede: end address of contents to be displayedf: carriage return denoting end of command input362

-------------------------. EASE6400 •EASE6400 EMULATOR MEMORY CONFIGURATIONThe EASE6400 emulator memory area,which can be used by the user, is outlined in the following diagram. Thesections enclosed in boxes represent the register and memory areas which can be accessed from the hostcomputer keyboard, and which can be displayed/updated by debugging command.CMCODEMEMORY8192x8DMDATAMEMORYPROGRAMCOUNTERACCUMULATOR13U c:=JSTACKPOINTERCARRYc:=J ~HLFLAGREGISTERREGISTERI FR41DPORTO PORT 1PORT 9~PORTAc::=JPORTB~PORT 2PORTCI ElFPORTDI IRQPORT 3414]I PO41I P141I P241I P341PORT 4DPROBECOMPAREREGISTER~PORT 5 PORT 6U r==JPROBEMASKEXECUTIONMODEREGISTER~ I EM 41PORT?DBREAKCONTROLREGISTERDPORT 8r=JBREAKSTATUSREGISTERI BS61IIBP TR IESOCETMIBFBTRACEMEMORYINITIALBUFFERFINALBUFFER8192 8192 8192x1 x1 x18192 8192x1 x1 2048x66 139x8 210x8CYCLE COUNTERt L CYCLE COUNTER ENABLE BIT MEMORYSYNC OUTPUT BIT MEMORYINSTRUCTION EXECUTED BIT MEMORYTRACE ENABLE BIT MEMORYBREAKPOINT BIT MEMORYTRACE POINTERTPBLKBLOCKMEMORY8192x1363

eEASE6400e-------------------------------------------------DMAJOR MEMORY OPERATIONS1. Code memoryThe code memory is an 8192 x 8-bit RAM areawhich corresponds to the OlMS-64 maskedROM area where user programs are stored.(The MSM6404 ROM capacity is 4000 bytes)2. Data memoryThe data memory is a 256 x 4-bit RAM area correspondingto the MSM6400E RAM area.3. Instruction executed bit memoryThis memory is an 8192 x 1-bit RAM area which hasaddresses identical to the code memory. When acode memory program is executed, the bits correspondingto the excuted addresses are set to "1". Theprogram flow can thus be determined by checking thecontents of this memory.4. Break point bit memoryThe break point bit memory is also an 8192 x 1-bitRAM area which has addresses identical to the codememory. If a particular bit in this memory is "1", programexecution is suspended immediately after thecode memory contents corresponding to that bit areexecuted.5. Trace enable bit memoryThe trace enable bit memory is another 8192 x 1-bitRAM area which has addresses identical to the codememory. If a particular bit in this memory is "1", port!register contents, etc., are stored in the tracememory when the code memory contentscorresponding to that bit are executed.6. Sync ouput bit memoryThe sync output bit memory IS another 8192 x 1-bitRAM area which has addresses identical to the codememory. When the code memory contents are executed,the corresponding bits in the sync outputmemory are checked, and if a "1" bit is found, an outputsync signal (active lOW) is passed to the probeterminal.7. Cycle counter enable bitThe cycle counter enable bit memory is also another8192 x 1-bit RAM area which has addresses identicalto the code memory. When the code memorycontents are executed, the corresponding bits in thecycle counter enable bit memory are checked,and if a "1" bit is found, the cycle counter iscounted up in step with that machine cycle.S. Probe comparison register/probe maskThe conditions for generating a break by input datafrom the probe (probe match break) can be changedby altering these two settings.9. Initlallflnal buffersThese two memories are 210 x 8-bit RAM areasused to store the initialized settings of the MSM6400Eevaluation chip or the MSM6400E status immediatelyafter a break when real-time emulation is executed.10. Trace memoryThe trace memory is a 2048 x 56-bit RAM area usedto store traced data.The trace instruction is given by the trace enable bit.364

---------------------------------------------------eEASE6400eLIST OF DEBUGGING COMMANDSLoad, save, and Verify CommandsLOD [dr ;] filename ~SAV [dr ;] filename [address, address] ~VER [dr ; ] filename [address, address] ~EPROM CommandsPPR address, address [, address] ~TPR address, address [, address] ~VPR address, address [, address] ~Commands Used to Display/Change Internal Status of Evac:hipPCSPACCYHLFRPO-P8P9PAPBPCPDMElDPCCPC address ~DSP~CSP data~DAC~CACdata~DCY~CCYdata~DHL~CHLdata~DFR~CFRdata~Load programs into code memorySave code memory programVerify file with code memoryProgram Code Memory into EPROMTransfer EPROM into Code MemoryVerify EPROM with Code MemoryDisplay Program CounterChange Program CounterDisplay Stack PointerChange Stack PointerDisplayAocChangeAccDisplay Carry FlagChange Carry FlagDisplay H-L RegistersChange H-L RegistersDisplay Flag RegisterChange Flag RegisterDPn~ (n = 0, 1, 2, 3, ... 8) Display Port nCPndata~ (n = 0, 1, 2, 3, ... 8) Change Port nDcMR~ Display Counter Mode Register (port 9)CCMRdata~Change Counter-Mode RegisterIIDSMR~ Display Shift Mode Register (portA)CSMRdata~ Change Shift Mode RegisterDCFR Display Control Flag Register (port B)* Change CFR command is not permittedDEIF ~ Display Enable Interrupt Flag (port C)CEIFdata ~Change Enable Interrupt FlagDIRQ Display Interr:upt Request Flag (port D)* Change IRQ command is not permittedDMEI~CMEldata~Display Master Enable Interrupt FlagChange Master Enable Interrupt FlagD~ Display all internal status~Data & Code Memory Display, Change, and Fill CommandsDDM address [, address] ~Display Data MemoryDM CDM address.-' data data ... ~ Change Data MemoryFDM address, address, data ~Fill Data MemoryDCM address [, address] ~Display Code MemoryCM CCM address ~ datadata ... ~ Change Code MemoryFCF address, address, data ~Fill Code Memory365

.EASE6400·----------------~-------------------------------Attribute Memory Display, Enable, and Reset CommandsDBP address [, address)';Display Break Point Bits MemoryBP EBP address [, address).; Enable Bteak Point MemoryRSP address [, address).;Reset Break Point Bits MemoryDTR address [, address)';Display Trace Enable Bits MemoryTR ETR address [, address)'; Enable Trace Enable Bits MemoryRTR address [, address)';Reset Trace Enable'Bits MemoryIEDIE address [, address)';RIE address [, address)';Display Instruction Executed Bits MemoryReset Instruction Executed Bits MemoryDCE address [, address)';Display Cycle Counter Enable Bits MemoryCE ECE adaress [, address)'; Enable Cycle Counter Enable Bits MemoryRCE address [, address) .JReset Cycle Counter Enable Bits MemoryDSO address [, address) .;Display Sync Out Enable Bits MemorySO ESO address [, address).; Enable Sync Out Enable Bits MemoryRSO address [, address)';Reset Sync Out Enable Bits MemoryTrace Memory Display CommandsTMDTMDTlOther Hardware Display and Change CommandsCCDCC';CCC number .;DBC';SBC [[±) mnemonic, ...)Display Trace MemoryDisplay Trace ListDisplay Cycle CounterChange Cycle CounterDisplay Break Condition RegisterSet Break Condition Registermnemonic means one of following key wordsI) BC here.BB ........ Break at Break PointXB ........ External BreakCO ........ Cycle Counter Over FlowTF ......... Trace Memory FullPM ........ Probe MatchHS ........ HAL T/STOP Instruction ExecutedBS DBS'; Display Break Status RegisterPMCRDPM';CPMdata';DCR';CCRdata';Display Probe Mask RegisterChange Probe Mask RegisterDisplay Probe Compare RegisterChange Probe Compare RegisterDEMDisplay Execution Mode RegisterCEM mode-ref .;Change Execution Mode Registermoc;te-ref means one of following keywordshere.'EM IF .......... IB TOFBIN ......... IB TO NONNN ........ NON TO NONNF ........ NONTOFBFF ......... FB TOFBDBl address [, address) .;Display Block MemoryBlK SPB address [, address)'; Set Block Memory into Program BlockSDB address [, address)';Set Block Memory into Data BlockBANK BANK 1 or2JSet Attribute Memory Bank Register366

-------------------------------------------------eEASE6400eInitial Buffer & Final BufferDIB,)DFB,)CI key-word data ,)Display Initial BufferDisplay Final BufferChange elements of Initial Bufferkey-word ... AC, HL, FA, SMR, CMR, MEl,ElF, CY, Pn (n=O, 1,3,4, ...,8)Change Initial Buffer Data MemoryIB CIDM address,) data data ... ,)FB CF key-word data ,) Change elements of Final Bufferkey-word ... AC, HL, FR, SMR, CMR, MEl,ElF, CY, Pn (n=O, 1, 3, 4, ...,8)CFDM address data data ... ,) Change Final Buffer Data MemoryFIDM address, address, data').FFDM address, address, data ,)Assemble & Disassemble CommandsASM address ,) mnemonic ... ,)DASM address [, address],)Emulation CommandsG [start-address] [, break-parameter, ......],)GD [start-address] [, break-parameter, ......],)STP [number] [, address],)Other CommandsFillnitial Buffer Data MemoryFill Final Buffer Data MemoryAssemble to Code MemoryDisassemble to ConsoleGo (Start Real Time Emulation)Go Direct (Start Real Time Emulation)break-parameter format is shown below1) address2) asddress (n)3) addres (n) & address (m)4) addres RAM (address - data)1 < n, m < 65535Start Step Execution@ [-n],)(n = 1, 2, ....., 9) Command - RepeatHELP,)Display Help File (EASE 64, HLPEXIT ,)Exit to CP/MRES')Reset EASE 6400 systemRESE,) Reset Eva - chip (MSM 6400E)SIO H or F ,)Set 1/0 ModeDEV,)CH2 port Output ControlST mnemonic ,)Family SetFDD [dr ... drl ,)Flopy Disk Unit SetDIR [dr:l,)Display file directoryo367

EASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEMfor theMSM6502 CMOS 4-Bit, 1-Chip MicrocontrollerEASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEMThe EASE6502 Program Development Support System has been specifically designed for rapid and efficientprogram development of Oki's MSM6502 CMOS 4-bit, 1-chip microcontroller.IIFEATURES1. Connecting the MPB6502 Evaluation Boardto a host computer or to an I/O terminal suchas a CRT terminal includes an RS232Cinterface circuit. All debugging operationscan be entered from the console keyboard.2. Executes user programs with the trace in realtime or in single step mode.3. Mass storage user program area (4K bytes).4. Six types of break conditions, includingexecution address and machine cyclecounter.5. EPROM programmer (for 2716, 2732, 2732A) toenable programming, transfer, and verifing withuser program area contents.6. The same operation as the MSM6502,because OKi designed the original evaluationchip (MSM6502E).7. Built-in system diagnostic program.HOST COMPUTER REQUIREMENTS1. Operating system is one of the follows.(1) CP/M®-80 (ver 2.0 or later)memory capacity of the host computermust be sufficient to run at least 52KCP/M.(2) MS-DOS'" (ver 1.25, ver2.11)(3) PC-DOS® (ver 1.25, ver2.11)2. At least one RS232C communication port isimplemented.3. Data transfer is performed through RS232Ccommunication port using BOOS functioncall 6 on condition that console device isassigned to TTY:.COMMUNICATION WITH HOSTCOMPUTERICs used• Communication interface MSM82C51A• Driver/receiver SN75188N, SN75189NTransmission format• 110 to 9600 bps (selectable)• 8 bits, 2 stop bits, non-parity7 tilts, 2 stop bits, even parity7 bits, 2 stop bits, odd parity (selectable)SYSTEM CONFIGURATIONThe EASE6502 Program Development SupportSystem consists of the EASE6502 Emulator (ahigh performance program emulator whichincludes the EASE65 Host Monitor, theMPB6502 Evaluation Board, and the hostcomputer) and the ASM6502 Assembler. Withthe MPB6502 Evaluation Board connectedonline to the host computer equipped with anRS232C interface, the system covers alloperations from assembly of the source program. through to program evaluation and debugging.MPB6502Evaluation BoardUser's applicationcircuit+5V +12V -12V(4.5A) (O.2A) (O.2A)• EASE65• ASM6502:8IC§JI~Note: CP/M is the registered trademark of Digital ResearchInc. (U.S.A.)EASE65 and ASM6502 for MS-DOS, PC-DOSare optional softwares.368

-------------------------------------------------..EASE6502.ASM6502 ASSEMBLERThe ASM6502 is a floppy disk based high-performance assembler.This assembler is used to translate source files generated on disk by using an editor (available on themarket), thereby generating object files (Intel HEX format), assembly list files, and cross-referencelist files on the specified devices.FEATURES1. Free descriptive format source files2. Capacity to describe up to ten types of arithmeticin the source program operand field3. Ability to specify the number of characters per lineand the number of lines per page in assemblylist files4. Cross-reference list file generation capacity5. 13 types of powerful pseudo-instructions available6. Object codes where all page jump instructions andinter-page jump instructions are assignedautomatically can be obtained by branch pseudoinstructions7. Control of assemble list file outputs by LIST orNLST pseudo-instructionLIST OF PSEUDO-INSTRUCTIONSPseudoinstructionEQUSETORGENDBFunctionAssign the operand value to the name.Same as EQU pseudo-instruction, butwith redefinition capacityDefine assembler location counter.Terminte assemblyAutomatic conversion to aU-page orinter-page jump instruction after checkingbranch destinationDBDSNSEDATEPAGETITLLISTNLST8-bit data or ASCII character stringdefinitionReserve n bytes area of uninitializedstorageSetting of 0 in the 4 lower order bits ofthe assembler location counter, andaddition of 16. The NOP instruction isasSigned to blank areas where nomachine language instruction has beenassigned.Insertion of date in assemble list titleExecute page ejectInsert assemble list titleTurn on assemble list outputTum off assemble list outputD369

• EASE6502 .--------------------------------~-------------EASE6502 EMULATORDConsisting of a host computer and the MPB650~ Program .Evaluat~o~ Board, the EAS.E6502 Emulatorsupports a wide range of development debugging opera~lon~ effl?le~tly .and effectl.vely. MSM6502application programs can be debugged without user application circuits Just as easily as completedsystems.FEATURES1. Real-time tracing' ~unction does not effectexecution timeThe MPB6502 Evaluation Board incorporates a realtimetrace area for 2048 machine cycles. When tracingfor a particular user program area address hasbeen set, the port, HL register, and MEl flag statusare traced each time the specified address is executed.2. Execution time measurementThe user program execution time can be measuredby using the cycle counter on the MPB6502 EvaluationBoard. (Max. 16,777,215 cycles)This counter can also be used as a pass counterto indicate the number of times a specifiedaddress is executed. Emulation can be stoppedafter a specified address has been executed aspecified number of times.3. Mass storage user program areaWith a 4096-byte static FjAM area in theMPB6502 Evaluation Board for use as a userprogram area, there is no problem withinadequate memory area during debugging. And,needless to say, user programs can beloaded/saved from the host computer.Furthermore, with an EPROM programmerincluded on this board, the user program areacontents can be written into EPROMs, and theEPROM contents can be read out.5. Extensive range of debugging commandsIn addition to display/updating of all register, port, andRAM contents, the following commands enable alldebugging operations to be executed efficiently.a) User program executionInput format:STP number of instructions~ start addressInput of this command results in the specifiednumber of instructions in the user program beingexecuted from the specified address (startaddress).And if the terminal to be used to display the contentshas been specified by SDF command at thistime, the display can be put into an easy to readformat.Input format:G start address, break address (n)Input of this command results in the user programbeing executed from the specified address (startaddress). Emulation is subsequently stoppedwhen the specified address (break address) isexecuted n times.Note: Program execution is suspended temporarily eachtime the specified address is executed.4. Ample break functionsThe emulator can suspend (break) program executionby any of the following six brteak conditions.a) Breakpoint breakBreak upon execution of specified address. (Anyaddress may be specified.)b) Extemal breakBreak by application of extemal break signal.c) Halt instruction break .Break by execution of HALT instruction.d) Trace buffer full breakBreak when overflow of trace area occurs.e) Cycle counter overflow breakBreak when overflow of cycle counter occurs.t) Probe match breakBreak when probe data matches set data.Input format:G start address, break address RAM(address-n)Input of this command'results in the user prog"~mbeing executed from the specified address (sta~.address). Emulation is subsequently stopped ifthe contents of the specified RAM address are nwhen the specified address (break address) isexecuted. In this case, too, program execution issuspended temporarily whenever the specifiedaddress is executed.370

________________________________________________ -4. EASE6502 •b) Use of floppy disksInput format:LaD filenameInput of this command enables the specified filecontents (user program) to be loaded into theMPB6502 Evaluation Board code memory whichserves as the MSM6502 masked ROM area.Input format:SAY filename start address, end addressInput of this command enables the contents of thespecified range of code memory to be saved atthe specified filename.Example:*DDM 0, 1 F .JII \j I V Iab c d e fa: denotes wait for command input from emulatorb: denotes display of contents of specified registter /memory/boardc: data memory (equivalent MSM6502 RAM area)designationd: start address of contents to be displayede: end address of contents to be displayedf: carriage retum denoting end of command inputInput format:DIAG filenameInput of this command enables execution of commandswithin the specified file automatically.This execution can be suspended temporarily byusing the PAUSE command.Input format:LIST filenameNLiSTIf the list command is entered, the emulator creatthe CP/M file and write into it the any characterswhich are output to the console till entering theNLST command.c) Instruction executed bit memoryThe EASE6502 Emulator includes aninstruction executed bit memory which indicateswhich user program addresses have been executed.Program flow can be known by examinationof the contents of this memory.6. Easy to remember command formatThe MPB6502 Emulator debugging commands consistof command mnemonics followed by parameters(address or mnemonic).Command mnemonic configurationa) First characterStand for the emulator function (display/update)b) Second and follOWing charactersRepresent one of the MPB6502 Evaluation Boardor the MSM6502E evaluation chip element (register,memory or port name).o371

.EASE6502, •• --------------------------------------~--~-----EASE6502EMULATOR MEMORY CONFIGURATIONThe EASE6502 emulator memory area which can be used by the user is outlined in the following diagram. Thesections enclosed in boxes represent the register and memory areas which can be accessed from the hostcomputer keyboard, and which can be displayed/updated by debugging command.INSTRUCTION EXECUTED BIT MEMORYTRACE ENABLE BIT MEMORYBREAKPOINT BIT MEMORYCYCLE COUNTER ENABLE BIT MEMORYVMVERIFYMEMORYCMCODEMEMORYBTl S CPRE 0 ETMTRACE MEMORY4096x84096x82048x66DMDATAMEMORY128x4SGSEGMENTDATAMEMORY208x84096x5TRACE POINTERI TP 111CYCLE COUNTERIcc 241DPROGRAMCOUNTER~PORTOE]CARRY~PROBECOMPAREREGISTERE]ACCUMULATOR~PORT 1~MEl FLAGEJPROBEMASK~HlREGISTERUPORT 2E]INDEXREGISTEREJEXTERNALPROBEE]STACKPOINTERE]PORT 3EJBREAKCONTROLREGISTERE]PORT 4EJEMULATIONMODEEJBREAKSTATUSREGISTER.~INSTRUCTIONDATAE]PORT 5~IBINITIALBUFFER139x8FBFINALBUFFER139x8BlKBLOCKMEMORY4096 x 1

---------------------------------------------------4. EASE6502 •MAJOR MEMORY OPERATIONS1. Code memoryThe code memory is an 4096 x 8·bit RAM areawhich corresponds to the MSM6502 masked ROMarea where user programs are stored.(The MSM6502 ROM capacity is 2000 bytes)2. Data memoryThe data memory is a 128 x 4-bit RAM area correspondingto the MSM6502 masked RAM area.3. Verify memoryThe verify memory is a RAM area with addressesidentical to the code memory. When a user programis loaded into the code memory identical contents arealso set in this memory.Comparrison of this memory with the code memoryenables the operator to determine what sections ofthe user program have been changed after loading.4. Instruction executed bit memoryThis memory is an 4096 x 1-bit RAM area which hasaddresses identical to the code memory. When acode memory program is executed, the bits correspondingto the executed addresses are set to "1".The program flow can thus be known by checking thecontents of this memory.5. Break point bit memoryThe break point bit memory is also an 4096 x 1-bitRAM area which has addresses identical to the codememory. If a particular bit in this memory is "1", programexecution is suspended immediately after thecode memory contents corresponding to that bit areexecuted.6. Trace enable bit memoryThe trace enable bit memory is another 4096 x 1-bitRAM area which has addresses identical to the codememory. If a particular bit in this memory is "1", port/register contents, etc., are stored in the tracememory when the code memory contents correspondingto that bit are executed.7. Sync ouput bit memoryThe sync output bit memory is another 4096 x 1-bitRAM area which has addresses identical to the codememory. When the code memory contents are executed,the corresponding bits in the sync outputmemory are checked, and if a "1" bit is found, an outputsync signal (active LOW) is passed to the probeterminal.8. Cycle counter enable bitThe cycle counter enable bit memory is also another4096 x 1-bit RAM area which has addresses identicalto the code memory. When the code memorycontents are executed, the corresponding bits in thecycle counter enable bit memory are checked, and ifa "1" bit is found, the cycle counter is counted up instep with that machine cycle.9. Probe comparl register/probe maskThe conditions for generating break by input datafrom the probe (probe match break) can be changedby altering these two settings.10. Segment data memoryThe segment data memory is a 208 x 8-bit RAMarea with coordinates 0 thru 7 on the vertical axis andA thru Z on the horizontal axis. This memory is usedto display the status of each bit of the MSM6502 RAMliquid crystal display area at the specified coordinateand by the specified character.Displaying the status of this memory provides animage of the liquid crystal display status.11. Initial/final buffersThese two memories are 139 x 8-bit RAM areasused to store the initialized settings of the MSM6502Eevaluation chip or the MSM6502E status immediatelyafter a break when real-time emulation is executed.12. Trace memoryThe trace memory is a 2048 x 66-bit RAM area usedto store traced data.The trace instruction is given by the trace enable bit.o373

• EASE6502 .-------------------------------------------------DEBUGGING COMMAND TABLEo23.Load, Save, and Verify Commands1. LOD [dr:] filename Load Program into Code Memory2. SA V [dr:] filename [address, address] Save Code Memory Program3. VER· [dr:] filename [adress, address] Verifty File with Code Memory4. LSG [dr:] filename [address, address] Load Segment data5. SSG [dr:] filename Save Segment data6. VCM address [, address] Verify Code Memory with Verify MemoryEPROM Commands1. PPR address, address [, address] Program Code Memory into EPROM2. TPR address, address Transfer EPROM into Code Memory3. VPR address, address [, address] Verify EPROM with Code MemoryDisplay Commands1. 0 All Register, Flag, Port2.DACAcc Register3.DHLHL Register4.DCYCarry Flag5. DSP Stack Pointer6. OLD LCD Driver ON/OFF status (Port 4-0 bit)7. DEI Enable Interupt Flag (MEl, TBC EI, ext. INT EI)8. DPn Port N (n=O, 1, 2, 3, 4)9. DPC Program Counter10. DCC Cycle Counter11. DCR Probe Compare Register12. DPM Probe Mask Register13. DBC Break Condition14. DBS Break Status15. DEM Emulation Mode16. DIB Initial buffer & Final buffer17. DFB Final buffer & In~ial buffer18. DSG Segment Data Status19. DBP address [, address] Break Point Bit Memory20. DCE address [, address] Cycle Counter Enable Bit Memory21. DSO address [, address] Sync Output Enable Bit Memory22. DIE address [, address] I nstruction Executed B~ MemoryDTR address [, address]Trace Enable Bit Memory24. DDM address [, address] Data Memory (M6502E Internal RAM)25. DCM address [, address] Code Memory26. DVM address [, address] Verify Memory27. DTM tp-address, line-number Trace Memory28. DTL -number, line-number Trace ListChange Commands1. CAC data Acc Register2. CHL data HL Register3. CCY Oorl Carry Flag"4. CSP data Stack Pointer5. CLD Oorl LCD Driver ON/OFF Status6. CEI [data] Enable Interrupt Flag7. CIR data Index Register8. CPn data Port n (n=O, 1,3,4,5)9. CPC address Program Counter10. CCC (+ or -) data Cycle Counter11. CCR data probe Compare Register12. CPM data Probe Mask Register13. CBZ Oorl Buzzer Output Select Hard or Soft14. CEM mode Emulation Mode*mode*IF IB to FBIN IB to NONNN NON to NONNF NON to FBFN FB to NON15. CI key-word data Initial Buffer16. CF key-word data Final Buffer17. CSG Segment data18. CCM address CooeMemory19. COm address Data Memory (M6502E Internal RAM)20. BANK 0 or 1 Attribute Memory Bank374

--------------------------------------~----------_e. EASE6502 •Enable Commands1. EBP2. ECEaddress I. address]address I. address]Break Point Bit MemoryCycle Counter Enable Bit Memory3. ESO4. ETRaddress I. address]address I. address]Sync Output Enable Bit MemoryTrace Enable Bit MemoryReset Commands1. RBP2. RCEaddress I. address]address I. address]Break Point Bit Memo~Cycle Counter Enable it Memory3. RIE address [. address] Instruction Executed Bit Memory4. RSO address I. address] Sync Output Enable Bit5. RTR6. RESaddress I. address]ETrace Enable MemoryM6502E Eva-chip7. RES MPB6502 BoardFill Commands1. FCM2. FDMaddress. address. dataaddress. address. dataCode MemoryData Memory3. FIDM4. FFDMaddress. address. dataaddress. address. dataInitial Data MemoryFinal Data MemoryEmulation Commands1. G 1st-address] I. break-parameter. ___ oj Begin Emulation2. GO 1st-address] I. break-parameter. ___ oj Begin EmulationIf the optional st-address is given. emulator will begin emulation from st-address. And if optional breakparameteris given. emulation will break on the first break-parameter to be satisfied.Break-parameter = break-address= break-address (pass count)= break-address (pass count) & break-address (pass count)= break-address RAM (RAM address-data)3. STP Inumber] I. st-address] Single StepOther Commands1. ASM address Assemble to Code Memory2.DASM address I. address] Disassemble to Console3. LIST Idr :] filename List Console Output into Disk File4. NLST End listing5. DBLK6. SPBaddress I. address]address I. address]Display Block MemorySet Program Block7. SOB8. SIOaddres I. address]ForHSet DB BlockSet Emulator to 110 terminal mode9. EXIT10. PAUSEReturn to CP/MStop Command File Execution11. DIAGI12. DIAG Idr:] filenameStart Sell Check P~ramExecute Command ile13. @ I-n] Repeat Command14. HELP15. SBCDisplay HELP File(+ or -) mnemonic I. (+ or -) mnemonic. __ ojSet/Reset Break Condition Register* mnemonic*BBBreak when Break Point ReachedXBExternal BreakCOBreak on Cycle Counter OverflowTFBreak when Trace Buffer FullPMBreak on Probe Match16. SDFHTBreak on HALT Instruction(+ or -) mnemonic I. (+ or -) mnemonic. __ ojSet/Reset Dump Format1. DEL2. CntrllCDelete the last character enteredReturn to CP/M3. CntrI/P4. Cntrl/QCopy all subsequent console output to the currently assigned list deviceContinue normal dispaly5. CntrllS6. CntrllRStop displayEchoe current input line7. ESC Abort any command inprogress8. @ I-n] Repeat the command.Note: The MSM6502 RAM area corresponds to the EASE6502 Emulator data memory. and the-mask ROM corresponds tothe code memory.o375

• EASE6502 .---------------------------------------------------SAMPLESA>EASE65« EAS£65 » PI" eli mIn a r y It 1 .0Sep.3.1983 OKI electric ind.co.,ltdNow, start up MPB6502 board.HARD WARE SELF CHECK[ NORMAL EN~ ]« MPB6502 EMULATOR PRELIMINARY 1t1.5 »COPYRIGHT OK! ELECTRIC IND. CO., LTD. 1984ACTIVE BREAK CONDITION ---> BREAK POINT BREAKHALT INSTRUCTION BREAKo** NOW DEVICE NO. = A,B **[ KEY IN OTHER DEVICE NO. ][PRESENTE~ ~EVICE NO."A:B:]'" DIAG INrTl* ; INITIALIZATION START'" FeM '"* LSG PIC.DATSGRAM SET-UP COMPLETED* LDO RAMSErLOAD COMPLETED NEXT ADDRESS=OOZO'" LIST CRT.Lsr'" ; NOW INITIALIZATION END AND LIST STARTDIAG COMHAND END* G DO, 1 FBAN K : 1 EXECUTION MO~E NON TO NON(RESET TRACE POINTER)EMULATION GO "'*PARAMETER=OOlF( 0)BREAKA~~RESS[BREAK PC"01F NEXT PC"O;OJ[NEXT TRACE POINTER"17]'" DDM 0,3LOC"03-00 5 5 5 2'" D TM 4,3LOC"012 82 LAIPORT (0-2) =FFOLO C = 0 13 B 4LMAPORT 10-2) =FFOl 0 C = 014 11 IN LPORT(0-2) =FFO* DIE 0,.2 0lOC"'OOO 1100 0000 0000 0000lO(:=020 o* D A S M 0,13lOC=OOO 5FlOC"OOI ~OLOC"002lOC=010 SAOOlOC"'012 82LOC"'013 B4* NLST* EXITA'~ IJCP 010Hl"'OO CY=OHL=OO C yo 0Hl=OO CY=O1 111 1111 1111 1101MEI;;OMEI"OMEl = 0XP=FFXP" FFXP=FFDB 00 00 00 00 00 00 00 00 00 00 00 00 00 00L H L I 00LAIL MATP"'4TP=5TP",376

---------------------------------------------------. EASE6502 •EASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEMfor the MSM6502 CMOS 4-BIT 1-CHIP MICROCONTROLLERCategory Model TitleHardware MPB6502 4-bit 1-chip microcontroller evaluation boardSoftwareEASE65ASM6502Floppy disk based host monitor*Floppy disk assembler*Manual TM-6502 EASE6502 Development Support System - User's ManualTCU-6502User application circuit connection cablesTCS-1 Host CP/M@ computer connecting cables (for if800 model 1 0/20/30)Accessories TCP-1 Power supply cables (+5V, 4.5A) (+12V, 0.2A) (-12V, 0.2A)TCX-1TCC-1• Available under following operating system• CP/M-80 (ver 2.0 or later)• MS-DOS (ver 1.25, ver 2.11)• PC-DOS (ver 1 .25, ver 2.11)External probe cablesBoard connecting cablesOPTIONSOption nameMPB6502 EVABoardRemarksA simplified evaluation board consisting of the MSM6502E plus EPROM sockets,and designed for the MSM6502. Programs are evaluated by inserting the EPROMwhere the user program is stored into an EPROM socket.Dimensions: 160 x 127 (mm)D377

EASE 80C49 PROGRAM DEVELOPMENT SUPPORT SYSTEMforMSM80C48RS/MSM80C49RS/MSM80C50RS CMOS 8-Bit MicrocontrollersEASE80C49 PROGRAM DEVELOPMENT SUPPORTSYSTEMThe EASE80C49 Program Developinent Support System has been specifically designed for rapid andefficient program development of Oki's MSM80C48RS, MSM80C49RS and MSM80C50RS CMOS8-bit, 1-chipmicrocontrollers.DFEATURES1. In-circuit emulation when connected to an RS232Cinterface equipment host computer or to aninput/output device such as a CRT terminal.2. 4K byte user program area available for codetransfer to/from floppy disk, collation/updating ofarea contents, and continuous/step execution.3. Eight types of break conditions (for interruptionof emulation) including execution address andmachine cycle counter.4. EPROM programmer (for 2716, 2732, 2732A) toenable writing, transfer, and comparison of userprogram area contents.5. User program debugging operations directed bydebug commands entered from the keyboard ofthe connected input/output device.6. Built-in system diagnostic program.HOST COMPUTER REQUIREMENTS1. Operating system is one of the follows.(1) CP/M""-80 (ver 2.0 or later)memory capacity of the host computermust be sufficient to run at least 52KCP/M.(2) MS-DOS® (ver 1.25, ver2.11)(3) PC-DOS® (ver 1 .25, ver2 .11)2. At least one RS232C communication port isimplemented.3. Data transfer is performed through RS232Ccommunication port using BDOS functioncall 6 on condition that console device isassigned to TTY:.MPB800 EVALUATION BOARD DATATRANSFER SYSTEMICs used• Communication interface MSM82C51A• Driver/receiverSN75188N,SN75189NTransmission format• 110 to 9600 bps (Switch able)• 8 bits, 2 stop bits, non-parity378SYSTEM CONFIGURATIONThe EASE80C49 Program Development SupportSystem consists of the EASE80C49 Emulator (a highperformance program emulator which includes theEASE49 Host Monitor, the MPB800 EvaluationBoard, and the host computer) and the ASM-49Assembler.With the MPB800 Evaluation Board connectedonline to the host CP/M computer (such as anif800) equippped with an RS232C interface, thesystem covers all operations from assembly ofthe source program through to programevaluation and debugging.MPBBOOEvaluation BoardNote:+5V +12V -12V(4.5A) (O.2A) (O.2A)• EASE49• ASM49:8I~IBCP/M is a registered trademark of DigitalResearch Inc. (U.S.A.)When the EASE80C49 is used on theMSM80C50, the MSM80C39 evaluation chipon the emulation board is to be replaced byMSM80C40.EASE49 and ASM-49 for PC-DOS, MS-DOS areoptional softwares.

--------------------------------------------------. EASE80C49 •ASM-49 CROSS-ASSEMBLERThe ASM-49 is a floppy disk based high-performance assembler.It translates source files generated on disk by using an editor, thereby generating object code files andassembly list files.LIST OF PSEUDO-INSTRUCTIONSFEATURESPseudo-instructionsFunction1. Free descriptive format source files2. 35 types of powerful pseudo-instructionsavailable for assembler control purposes3, Macro definition ability4. 11 types of pseudo-instructions to enableconditional assembly5. Assembly repetition processing (loop processing)6. Determination of variable values in thesource program by input from a consoleduring assembly, and linking to existingsource programs. (INPUT and LINK pseudoinstructions)7. Capacity to describe up to 13 types of operators inthe source program operand columnORG ExpressionDS ExpressionDW ExpressionDB ExpressionEQUSETIF ExpressionNIF ExpressionEND ExpressionMACROGOTOLabelREPT ExpressionREPNDLISTNOLSTTITLELocation counter value definedas nnn. (Expression=nnn)Reserves memory area for nnumber of bytes. The first andlast byte values may bechanged.Use ORG $+n to preventchange of values.(Expression = n)16-bit data definition8-bit data or ASCII characterstring definitionAssignment of operand valueto nameSame as EQU pseudoinstruction,but withredefinition capacityEvaluate expression value,and skip to next ENDIF, ENDor EDF (end of file) if result iszero. Assemble the nextinstruction if result is not zero.Evaluate expression value,and skip to next ENDIF, ENDor EDF (end of file) if result isnot zero.End of assemblyMacro definitionBranch the subsequentassembly to the destinationindicated in the labelDenotes repetition block.Assembly is executed thenumber of repetitions indicatedby the expression value.Definition of end of repetitionblockPass option invalidated, andoutput of full assembly listInhibition of assembly listoutputs apart from errormessagesAllocation of title at head ofassembly list pageD379

eEASE80C49 e----~------------------------------~----------EASE80C49 EMULATORConsisting of a host computer and the MPB800 Program Evaluation Board, the EASE80C49 Emulatorsupports a wide range of development debugging operations efficiently and effectively.MSM80C49RS and MSM80C50RS application programs can be debugged without user applicationcircuits just as easily as completed systems.DFEATURES1. Real-time tracing function does not effectexecution timeThe MPBBOO Evaluation Board incorporates areal-time trace area for 1024 machine cycles.When tracing for a particular user program areaaddress has been set, the port, program counter,and probe data status are traced each time thespecified address is executed.2. Execution time measurementThe user program execution time can be measuredby using the cycle counter on the MPB800 EvaluationBoard. (Max. 16,777, 215 cycles)This counter can also be used as a pass-Counterto indicate the number of times a specified addressis executed.3. 4096-byte user program areaA 4096-byte static RAM area in the MPB800Evaluation Board is used as a user program area,and user programs can be loaded/saved from thehost computer into this area. Furthermore,with an EPROM programmer included on thisboard the user program area contents can bewritten into EPROMs, and EPROM contentscan be read.4. Ample break functionsThe emulator can suspend (break) programexecution by any of the following eight breakconditions.a) BB (Breakpoint Break)Break upon execution of specified address.(Any address may be specified.)b) EB (External Break)Break by application of external break signal.c) CO (Cycle counter Overflow break)Break when overflow of cycle counter occurs.d) TF (Trace Full break). Break when 4097 tracings executed.e) PM (Probe Match break)Break when probe data matches set dataf) IF (Instruction Fetch)Break when machine code is fetched.g)MX (MovX)Break by MOVX instruction.h) ER (Error code)Break if incorrect machine code is fetched.5. Extensive range of debugging commandsIn addition to display/updating of all register, port,and RAM contents, the following commandsenable all debugging operations to be executedefficiently.a) User program executionInput format:. STP number of instructions, start addressInput of this command results in the specifiednumber of instructions in the user programbeing executed from the specified address(start address).Input format:G [. start address]Input of this command results in the user programbeing executed from the specified address(start address). If no start address is specified,'execution is started from the address indicatedby the program counter at that time.b) Use of floppy disksInput format:LOA filenameInput of this command enables the specified filecontents (user program) to be loaded into theMPBSOO Evaluation Board code memory whichserves as the MSM80C49RS/MSM80C50RS. masked ROM area.The same contents can also be loaded into theutility buffer by using the LOU command.Input format:SAV, start address, end address, filenameInput of this command enables the contents ofthe specified range of code memory to be savedat the specified filename.c) Instruction excuted bit memoryThe EASE80C49 Emulator includes an instructionexecuted bit memory which indicates whichuser program addresses have been executed.Program flow can be determined by examinationof the contents of this memory.380

------------------------------------------------eEASE80C49 e6. Easy to remember command formatThe MPB800 Emulator debugging commandsconsist of command mnemonics followed byparameters (address or mnemonic).Command mnemonic configurationa) First characterDenotes the function to be executed by theemulator.b) Second and following charactersName of function to be executed by theemulator-that is, MSM80C39 microcomputer orMPB800 Evaluation Board register, memory, orport name (abbreviation).Example:*DDM 0, 1F tII \j I V Iab cd e fa: denotes wait for command input from emulatorb: denotes display of contents of specified register!memory!boardc: data memory (equivalent MSM80C49RS!MSM80C50RS RAM area) designationd: start address of contents to be displayede: end address of contents to be displayedI : carriage return denoting end of command inputMAJOR MEMORY OPERATIONS1. Code memoryThe code memory is an 4096 x 8-bit RAM areawhich corresponds to the MSM80C49RS!MSM80C50RS program area (masked ROM)where user progrSlms are stored.2. Data memoryThe data memory is a 128 x 8-bit RAM areacorresponding to the data memory (RAM) on theMSM80C49RS chip. The data memory area forMSM80C50RS is 256 x 8-bits.3. Utility bufferThe utility buffer is a 4096 x 8-bit RAM area usedin temporary saving from the emulator when aload, save, or transfer command is entered.4. Break point bit memoryThe break point bit memory is also an 4096 x 1-bitRAM area which has addresses identical to thecode memory. II a particular bit in this memory is"1 ", program execution is suspended immediatelyafter the code memory contents corresponding tothat bit are executed.5. Trace enable bit memoryThe trace enable bit memory is another 4096 x 1-bitRAM area which has addresses identical to thecode memory. If a particular bit in this memory is"1 ", port and probe data is stored in the tracememory when the code memory contents correspondingto that bit are executed.6. Sync output bit memoryThe sync output bit memory is another 4096 x 1-bitRAM area which has addresses identical to thecode memory. When the code memory contentsare executed, the corresponding bits in the syncoutput memory are checked, and if a "1" bit isfound, an output sync signal (active LOW) ispassed to the probe terminal.7. Cycle counter enable bitThe cycle counter enable bit memory is alsoanother 4096 x'1-bit RAM area" which hasaddresses identical to the code memory. Whenthe code memory contents are executed, thecorresponding bits in the cycle counter enable bitmemory are checked, and il a "1" bit is lound, thecycle counter is counted up in step with thatmachine cycle.8. Probe comparison reglster!probe mask registerThe conditions for generating a break by inputdata from the probe (probe match break) can bechanged by altering these two settings.9. Trace memoryThe trace memory is a 1024 x 56-bit RAM areaused to store traced data.The trace instruction is given by the trace enablebit.II381

• EASE80C49 .,--------------------~--------------------------EASE80C49 EMULATOR MEMORY CONFIGURATIONThe EASE80C49 emulator which consists of a host CP/M'~ computer and the MPB800 Evaluation Board hasbeen designed for efficient debugging of MSM80C49RS and MSM80C50RS application programs.The various sections of the EASE80C49 Emulator which can be used are outlined in the following diagram.The sections enclosed in boxes represent the register and memory areas which can be accessed from thehost computer keyboard, and which can be displayed/update by emulator command.INSTRUCTION EXECUTED BIT MEMORYTRACE ENABLE BIT MEMORYBREAKPOINT BIT MEMORYSYNC OUTPUT BIT MEMORYCYCLE COUNTER ENABLE BIT MEMORYCMCODEMEMORY4Q96x8BTl SPRE 0"-\ 1/4096xlCEUBUTILITYBUFFER4096 x 8TMTRACEMOMORYTRACE POINTER1024x56DMDATAMEMORY12ax8I TP 10 1CYCLE COUNTER.I CC 24PROGRAM COUNTER ACCUMULATOR INSTRUCTION DATAPROGRAM STATUS WORDXMEXTERNALMEMORY256x8(Option)PROBE.COMPAREREGISTERPC 121 I AC 81 IDal PS 81PROBE;:.;MA;.;;S~K.:..---,I PR 81 I· PM 81BREAK CONTROLREGISTERI BC 81BREAK STATUSREGISTERI BS 81TIMERERROR CODETI al I EC 81EXTERNALINTERUPT VDD PROBEE] IVDll XPalTEST 0 TEST 1ITO 11 E]PORTO(Bus Port)I PO 81PORT 1 PORT 2PlP28181Emulator memory configuration382

----~------------------------------------------. EASE80C49 •EXECUTION EXAMPLEIn this sample program, 1 byte is read from port 1, and a parity check is executed on the first 7 bits. The MSB(most significant bit) is set to "1" if parity is odd parity, and reset to "0" if even parity. The result is then passedto port 2. Note that errors have been intentionally included in this program for demonstration purposes. Variousemulator commands are used to correct the errors.It is assumed that the program has already been assembled, and the object code has been stored in hexadecimalformat in a file called "PARITY. HEX" in drive A.Program listo 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0p 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 0o 0 0 Io 0 0 3o 0 0 5o 0 0 7o 0 0 9000 A000 C000 C000 C000 C000 E000 Fo 0 1 Io 0 I 2o 0 I 3o 0 I 5o 95 3 7 F140 CE 6 0 94 3 0 83 A040 ABA 0 89 7I 2 I 2A 77 7EA 0 F8 3o 0 I 60000 ERRORSSYMBOL TABLE* * * * * * * * * * * * * * * * * * * * * * * * * * * *This program reads a byte from Port I and checksbits 0 thru 6 for parity. If Parity is odd. thenbit 7 in the byte will be set and the result willbe output to Port 2. If the Parity is even. bit 7will be reset before the byte is output to Port 2.* * * * * * * * * * * * * * * * * * * * * * * * * * * *PARITYPAR IWAITPAR 0PAR 2PAR 3ORGINANLCALLJNCORLOUTLJMPMOVCLRJBCPLRRDJNZRETEND*************** MAIN PROGRAM ***************A. P IA, # 7FHPAR 0PAR IA, # 8HP2, AWAIT*************** SUBROUTINES ***************R 2, # 8C0, PAR 3CAR 2 , PAR 2; Input byte from PI; Mask out bit 7; Jump if even parity; Set bit 7; Output byte to P2; Set loop count; Initialize Carry Flag; Jump if bit 0 = I; Toggle Carry Flag; Loop 8 times and retPAR 0 0 0 0 C PARI o 0 0 9 PAR 2 o 0 0 F PAR 3 o 0 I 2o383

,·EASE80C49 .,------------------------------------~----------A>EASE49MPB80080C49 EMULATOR. VER 4.3COPYRIGHT J~E.1982.OKI SEMICONDUCTOR• F CM 0 F F F F F - Code memory is filled with FFH• LOA PAR ITY __ f Contents of the "PARITY. HeX" file are transferred to the code, memory* D CM 0 1 F ---- Code memory location contents from address OH thru 1 FH are displayed000=09 53 7F 14 OC E6 09 43 08 3A 04 OA BA 08 97 12010=12 A7 77 EA OF 83 FF FF FF FF FF FF FF FF FF FF·EBP A -----Break point at address AH is set to "1".• E BPI 7 F F F --- Break paint bits from address 17H thru FFFH are st to "1"• D B P 02 F --- The break point bit status from address OH thru 2FH is displayed00'0=0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0010=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1020= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1• C P 1 0 Port 1 is set to "0" (even parity)D• C P 2 0 ----- Port 2 is set to "0"·G 0 ------'-.' Start of emulation from address OHEMULATION BEOUN"PC=O OA TERMI NATED PO=FF PI=OO P2=00 TO=1 Tl=1 XP=FF AC=OO RO=R 1 =CA----. Port 2 is correct in respect to even parity• CP 11 ----- Port 1 is set to "1" (odd parity)• S DF -AL PIP 2 AC -- Dump format is changed• G 0 ------Start of emulation from address OHEMULATION BEGUNP C= 0 0 ATE RM IN ATE D P 1=01 P 2=09 AC=O 9- Port 2 is not correct in respect to odd parity* d P 1 3 Port 1 is set to "3" (even parity)*CP2 0 ----- Port 2 is set to "0"• G 0 ------Start of emulation from address OHEMULATION BEOUNPC=OOA TERMINAT• C P 1 4 ----- Port 1 is set to "4" (odd parity)• C P 2 0 Port 2 is set to "0"• GO' . Start of emulation from address OH384

------------------------------------------------eEASE80C4geEMULATIOM BEGUNPC=O OA T b:RMINATED Pl=04 P2=OC AC=OC - Port 2 is not correct in respect to odd parity·DTM - 1 0 . 1 0 --- Trace contents of the last ten cycles are displayedPC=015 RET PO=FF P1=04 P2=00 TO=1 T1=1 IN=lPC=005 JNC 09 PO=FF P1=04 P2=00 TO=1 Tl=l IN=lPOSSIBLE INTERRUPT ......... SEE APPENDIX3A.f08 PO=FF Pl=04 P2=00 TO=l Tl=lPC=007PC=009PC=OOA.EBP 5.CP2 0.G 0ORLOUTLJMPEMULATION BEGUNPC=007 TERMINATEDP2.A PO=FF P1=04 P2=OC TO=1 T1=1OOA PO=FF Pt=04 P2=OC TO=l Tl=lThe break point bit at address 5H is set to "1"Port 2 is set to "0"Start of emulation from address OHP1=04 ,P2=00 AC=04IN=lIN=1IN=1XP=FF TP=0058XP=FF TP=0060XP=FF TP=0062XP=FF TP=0064XP=FF TP=0066·STP 5Five steps (instructions) are executedPC=007 ORL A.f08 P1=04 P2=00 AC=OCPC=009 OUTL P2.A P1=04 P2=OC AC=OCPC=OOA JMP OOA P1=04 P2=OC AC=OCPC=OOA JMP OOA P1=04 P2=OC AC=OCPC=OOA JMP o OA P1=04 P2=OC AC=OC·DCM 0 F ----" Code memory location contents from address OH thru FH are displayed000=09 S3 '7F 14 OC E6 09 43 08 3A 04 OA BA 08 97 12• C CM 8 8 0 Gode memory location contents at address 8H are changed to "80H"• D CM 0 F Code memory location contents from address OH thru FH are displayed000=09 53 7F 14 OC E6 09 43 80 3A 04 OA BA 08 97 12• R BPSrhe break point bit at address 5H is set to "0" (reset)• C P 1 1 Port 1 is set to "1" (execution of odd parity again)·CP2 0·G 0EMULATION BEGUNPC=OOA TERMINATED P1=01 P2=81 AC=81-• C P 1 7 F Port 1 is set to "7F" (execution of odd parity again)·CP2 0·G 0EMULATION BEGUNPC=OOA TERMINATED P1=7F P2=FF AC=FF- Port 2 is correct in respect to odd parity• SAy 0 1 F PRTY 1- Program with file name of "PRTY1.HEX" is stored• FCM 0 FFF FF-- Code memory is filled with FFH• V PRO F F F 0 --EPROM is inserted into an EPROM socket and a blank check isexecuted• LOA P RTY 1 Program with file name of "PRTY.HEX" is transferred to code memory• P PRO 1 F 0 --- Transferred contents are written in the EPROM• V P R 0 1 F 0 --- EPROM contents are compared with code memory contents• t C -==--==- No error message (EPROM and code memory contents are identical)A> ------...: Return to CP/M(R) controlo385

eEASE80C49 .e------------------------------------------------LIST OF DeBUGGING COMMANDSo23.Characters which can be usedAaBbCcDdEeFfGgHhliJjKkLlMmNnOoPpQqRrSsTtUuVvWwXxYyZz 1234567890.,@+-Cnti/C Cnti/P Cl1t1/Q Cntl/R CntlfT Escape SpaceDisplay Commands1. DAC Display Accumulator2. DBP, 000 I,FFF] Display Breakpoint Bit(s) Status3. DBS Display Break Status4. DCC Display Cycle Counter5. DCE, 000 [,FFF] Display Cycle Counter Enable Bit(s) Status6. DCM, 000 I,FFF] Display Code Memory7. DDM, 00 [,7F] Display Data Memory8. DIE, 000 [,FFF] Display Instruction Executed Bit(s) Status9. DPO Display Port 0 (Bus Port)10. DP1 Display Port 111. DP2 Display Port 212. DPC Display Program Counter13. DPS Display Program Status Word, Test 0, Test 1 , Interrupt Pin14. DRG Display Registers RO thru R715. DSK Display Stack16. DSO, 000 [,FFF] Display Sync Output Bit Memory17. DTI Display Timer18. DTM, XXX, YYYY Move Trace Pointer (XXXX) and display Trace Memory (YYYY)19. DTP Display Trace Pointer20. DTR, 000 [,FFF] Display Trace Enable Bit(s) Status21. DVD Display Vdd Pin22. DXM, 00 [,FF] Display Extemal MemoryDXPDisplay Extemal Probe Byte, Probe Mask and Probe Compare ~egisterChange Commands1. CAC, FF Change Accumulator2. CCC, ZZZZZ77Z Change Cycle Counterr (Z77ZZZZZ is a positive or negative decimal number)3. CCM, FFF, FF Change Code Memory4. CDM, 7F, FF Change Data Memory5. CPO, FF Change Port 0 (Bus Port)6. CP1, FF Change Port 17. CP2, FF Change Port 28. CPC,FFF Change Program Counter9. CPM, BBBBBBBB Change Probe Mask (BBBBBBBB is a binary number)10. CPR, BBBBBBBB Change Probe Compare Register (BBBBBBBB is a binary number)11. CPS, FF Change Progr.am Status Word12. Cl\FF Change Timer13. CXM, FF, FF Change External MemoryFill Commands1. FCM, 000, FFF, FF Fill Code Memory2. FDM, 00, 7F, FF Fill Data Memory3. FXM, 00, FF, FF Fill External MemoryEnable C.ommands1. EBP, 000 [,FFF] Enable Breakpoint 6it(s)2. ECE, 000 [,FFF] Enable Cycle Counter Bit(s)3. ESO, 000 [,FFF] Enable Sync Output Bit(s)4. ETR, 000 [,FFF] Enable Trace Bit(s)386

--------------------------------------------------. EASE80C49 •Reset Commands1. RBP, 000 [,FFF] Reset Breakpoint Bit(s)2. RCE, 000 [,FFF] Reset Cycle Counter Enable Bit(s)3. RIE, 000 [,FFF] Reset Instruction Executed Bit(s)4. RSO, 000 [,FFF] Reset Sync Output Bit(s)5. RTR, 0000 [,FFF] Reset Trace Enable Bit(s)6. RES Reinitialize MPB800 SystemUtility & Disk Input/Output Commands1. CUB, FFF, FF Change Utility Buffer2. DUB, 000 [,FFF] Display Utility Buffer3. FUB, 000, FFF, FF Fill Utility Buffer4. TCM, 000, FFF Transfer Code Memory into Utility Buffer5. TUB, 000, FFF Transfer Utility Buffer into Code Memory6. TST Test7. LOA, filename Load Program into Code Memory8. LOU, Filename Load Program into Utility Buffer9. SAV, 000, FFF, filename Save Code Memory Program10. SVU, 000, FFF, filename Save Utility Buffer ProgramEPROM Writer Commands1. PPR, 000, FFF, FF Pogram Code Memory onto EPROM2. VPR, 000, FFF, FF Verify EPROM with Code Memory3. TPR, 000, FFF Transfer EPROM into Code MemoryEmulation Commands1. G[,HHH] Begin real time emulation. HHH is the start address (hex).2. STP [,EEEE][,HHH] Step emulation, where EEEE is the ,decimal number of instruction to execute,and HHH is the start address (hex).3. SBC, mnemonic Set/Reset Break Control Bit[,mnemonic]4. SDF, mnemonic Set/Reset Dump Format[,mnemonic]Command Line Editing & Keyboard Operation1. Rubout Delete the last character entered2. Cntl/C Return to CP/M3. Cntl/P Copy all subsequent console output to the currently assigned list device.Output is sent to both the list device untill the next Cnt/P is typed.4. CntllQ Continue normal display5. CntllR Echoe current input line6. CntllS Stop display7. Escape Abort any command inprogress8. @ Repeat last commando387

• EASE80C49 •EASE80C49 8-BIT 1-CHIP MICROCONTROLLERPROGRAM DEVELOPMENT SUPPORT SYSTEMCategory Model TitleHardware MPB800 8-bit 1-chip microcontroller evaluation boardSoftwareEASE-49ASM-49Floppy disk based emulator'Floppy disk based assembler'Manual TM-800 Program Development Support System-User's ManualAccessoriesTCU-800User application system connecting cablesTCS-B Host CP/M(R) computer connecting cables (for if800 model 20/30)TCP-8TCX-1Power supply cables (+5V,3.5A) (+ 12V, 0.2A) (-12V,0.2A)External probe emulation purposes• Available under following operating system• CP/M-80 (ver 2.0 or later)• MS-DOS (ver 1.25, ver 2.11)• PC-DOS (ver 1 .25, ver 2.11)D388

EASE80C51 mkll PROGRAM DEVELOPMENT SYSTEMforMSM83C154/80C51 CMOS 8-BIT, 1-CHIP MICROCONTROLLEREASE80C51mkil PROGRAM DEVELOPMENT SYSTEMThe EASE80C51 mkll Program Development System is a high-performance dedicated systemfeaturing Oki's exclusive technology, and which has been specifically designed for rapid and efficientprogram development of the Oki MSM83C154/80C51 8-bit single-chip microcontroller.SYSTEM CONFIGURATIONThe EASE80C51 mkll Program DevelopmentSystem consists of the EASE80C51 Emulator (ahigh performance program emulator which includesthe EASE Host Monitor, the EASE8051 m­kll Emulation Kit, and the host CP/M® orPC-DOS computer) and the ASM51 Assembler(a powerful assembler operated in CP/M® orPC-DOS. With the EASE80C51 mkll EmulationKit connected online to the host CP/M computer(such as the if800) equipped with an RS232Cinterface, the system covers all operations fromassembly of the source program through toprogram evaluation and debugging.HOST COMPUTER REQUIREMENTS1. Operating system is one of the follows.(1) CP/M@l_80 (ver 2.0 or later)memory capacity of the host computermust be sufficient to run at least 52KCP/M.(2) MS-DOS@ (ver 1.25, ver2.11)(3) PC-DOS"" (ver 1.25, ver2.11)2. At least one RS232C communication port isimplemented.3. Data transfer is performed through RS232Ccommunication port using BDOS functioncall 6 on condition that console device isassigned to TTY:.EMULATOR DATA TRANSFERICs used• Communication interface MSM82C51A• Driver/receiverSN75188N,SN75189NTransmission format• 300 to 19200 bps (Switchable)• 8 bits, 2 stop bits, non-parity• AsynchronousD389

• EASESOC5.1mkll .-------~----------------• EASE51• ASM51User'sapplicationcircuitUser cableUser'sapplicationcircuitUser cableHostcomputerRS232CEASE80C51 mkllEmulationKitTerminal Unit(CRT terminal etc.)RS232C

----------------------------------------~-----. EASE80C51mkll •ASM51 ASSEMBLERThe ASM51 is a floppy disk based high-performance assembler.This assembler is used to translate source files generated on disk by using an editor (available on the market),thereby generating object files (Intel HEX format), assemble list files, cross-reference list files, and symbol listfiles in the specified devices.OUTPUT FILES1. Object files (Intel HEX format)2. Assembly list files3. Cross-reference list files4. SymbOlic list filesFEATURES1. Free descriptive format source files2. Capacity to describe up to ten types of operatorsin the source program operand column3. Ability to specify the number of characters per lineand the number of lines per page in assemble listfiles4. 24 powerful pseudo-instructions5. Control of assemble list file outputs by LIST orNOLIST pseudO-instruction6. Output file and output device can be specifiedwhen the assembler is started.ASM51 ASSEMBLER FUNCTIONALBLOCK DIAGRAMSource fileASM51Assembly list files'------.. Symbol list files......... Cross~referencelist filesPART OF PSEUDO-INSTRUCTIONS LISTPseudo-instructionsEQUSETORGENDJMPCALLRADIXDBDWDSNSEDATEEJECTTITLELISTNOLISFunctionAssignment of operand valueto nameSame as EQU pseudoinstruction,but withredefinition capacitySetting of program startaddressIndication of end of programAutomatic change to relative,internal 2K page, or all pagesjump instruction after checkingbranch destinationAutomatic chang to relative,internal2K page, or all pagescall instruction after checkingbranch destinationRadix changed to 2, 8,10, or16 depending on value ofoperand8-bit data or ASCII characterdefinition16-bit data definitionReserves memory area forspecified number of bytesSetting of 0 in the 4 lowerorder bits of the assemblerlocation counter, and additionof 16. The NOP instruction isassigned to blank areaswhere no machine languageinstruction has been assigned.Insertion of date in assemblelist titleAssemble list page feedoperationInsertion of assemble list titleDesignation of assemble listoutputZuhibition of assemble listoutputo391

eEASE80C51mkil e---------------------------------------------EASE80C51mkil EMULATORConnected to the host computer via an RSS232C interface, the EASE80C51 mkll Emulator supports awide range of development debugging operations efficiently and effectively.MSM83C154/80C51 application programs can be debugged without user application circuits just aseasily as completed systems.oFEATURES1. Real-time emulation /Real-time emulation without insertion of a waitstate is possible because of the MSM83C154Eevachip.2. Execution time measurementThe user program execution time can be measuredwith the cycle counter in the Emulation Kit.(Max. 4,294,836,225 cycles)This cycle counter start/stop is effected accordingto the cycle counter start address/stop addressset by the command.3. Mass storage user program areaThis emulator provides a 64K-byte RAM area,(which is the entire address space ofMSM83C154/80C51l as the code memory(user program area). So, the largest program forMSM83C154/80C51 can be fully loaded in thisRAM area.It is also possible to assign 4K-byte units of programmemory area to the RAM area on the emulation kit orthe ROM on the u$Elr's application circuit by usingthe mapping command.This emulator further provides the EPROM programmerto enable the user program area contentsto be written to the EPROM or the EPROMcontents to be read.(EPROMs supported: Intel 2732, 2732A, 2764or 27128 or equivalent:)4. Ample break functionsThe emulator can suspend (break) program executionby any of the following break conditions.All conditions can be set and cancelled asdesired. .a) Breakpoint breakBr~ak upon execution of the address where abreak point has been set. (Any address to bespecified,)b) Address breakBreak execution of the address specifiedwhen the emulation command input was applied.It is also possible to specify a breakafter the specified address has been executedn times.c) Power down breakBreak occured when evachip going to thepower down mode ..d) Break by external forced bre.ak signalBreak by input of low level break signal fromoutside via the attached probe cable.e) Break by trace memory overflowBreak occurs when the trace memory is filledup with trace data.f) Break by cycle counter overflowg) Break by internal RAM/SFR area contentsBreak occurs when the contents of the specifiedRAM/SFR in the MSM83C154E matchedwith the specified contents the specifiednumber of times upon execution of the programat the specified address.5. Comprehensivli! real-time trace functionsThis emulator has the following two real timetrace areas not affecting the execution time.1. Trace memoryThis is the memory to trace (store) the status ofthe ports, carry flag and accumulator of theMSM83C154E when an instruction in the programmemory area is executed. (Up to 2048 machinecycles)Tracing is instructed in three ways as shownbelow.a) To start tracing each time the specified addressis executed.b) To start tracing upon execution of a specialinstruction (ACALL, AJMP, LCALL, LJMP,RET, RET!, PUSH or POP)c) To cause tracing by trace start/stop bit2. Flash trace memoryThe memory to trace status of the whole internalRAM or SFRarea in the MSM83C154E, whenthe instruction at the address specified by theemulator command (debug command) beingexecuted.The contents of the internal RAM or SFR areacan be stored up to 16 times in this memory.6. Easy-to-use emulator commandsThe emulator command (debug command) ofthis emulator consists of the command mnemonicand succeeding parameter(s) (address ormnemonic).Command mnemonic structurea) First letterRepresents the function to be performed bythe emulator.b) Second letter and onRepresent MSM83C154E evachip (or EA­SE80C51 mkll emulation kit) register, memory, orport name.392

---------------"'-----------. EASE80C51 mkll •Example:*DDM 01F..JI/\J I VIab cd e fa: Indication of waiting for command input fromemulatorb: Instruction of displaying contents of specifiedobjectc: Instruction of data memory (equivalent to internalRAM area in MSM83C154E)d: Start address 01 contents to be displayede: End address 01 contents to be displayedI: Carriage return indicating end 01 command inputThis emulator provides various emulator commandsnot only for display/modification of thecontents of each register and port of the specialevaluation chip MSM83C154E but also forefficient debugging operation.Input format:STP number-of-instructions start-addressInputting the above command causes the userprogram to be executed for as much as thespecified number of instructions from thespecified addresses (start address).It is possible to modify the display format to beeasier to read by specifying the object ofcontents display by the SSF command.Input format:G start-address, parameterParameter input format(1) Break-address, ... , break-address(2) Break-address (n)(3) Break-address RAM ram-address (byte-n)(4) Break-address sfr-mnemonic (byte-n)Inputting the command as shown in (1) causes theuser program to be executed from the specified address(start address), and breaks the program executionupon execution of any of the specified break addresses.Inputting the command as shown in (2) causes theuser program to be executed from the specified startaddress, and breaks the program execution when ithas passed the specified break address in times.Inputting the command, as shown in (3), causes theprogram to be executed from the specified address(start address). When the user program at thespecified break address is executed, the contents ofthe specified address (ram address) of the internalRAM in the MSM83C154E are compared withthe specified contents (byte) and the program executionis broken if they agree the specifiednumber of times (n).Inputting the command, as shown in (4), causes theuser program to be executed from the specified address(start address). When the user program at thespecified break address is executed, the contents ofthe specified SFR in the MSM83C154E arechecked. If the contents agree with the specifiedvalue (byte) the specified number of times (n),breaking occurs.Input format:(1) LOD filename(2) SAY filename start-address end-address(3) VER filename start-address end-addressInputting the command, as shown in (1), enables thecontents (user program) of the specified file onthe host computer to be loaded into the codememory on the EASE80C51 mkll emulation kitcorresponding to the program memory area(user program area) of the MSM83C154/80C51 .Inputting the command, as shown in (2), enables theblock of code in the specified range of the codememory to be saved using the specified file name.Inputting the command, as shown in (3), enables theblock of code in the specified file to be compared withthe block of code in the code memory.Input format:(1) DIAG filename(2) M(3) @Inputting the command, as shown in (1), enables thecommand in the specified file to be executed automatically.Use of the PAUSE command in combinationenables execution of the command in the file tobe suspended temporarily.Inputting the command, as shown in (2), enables thecommand line defined by the MAC command to beexecuted.Inputting the command, as shown in (3), enables thelast command to be executed again.Input format:(1) LIST filename(2) NLSTIf LIST command is entered, the emulator createthe CP/M file on the host computer and writesinto it any characters which are output to theconsole until entering the NLST command.Use of the above "DIAG" command in combinationenable the debugging work to be executed and storedin the file automatically.Input format:S tm-mnemonic data numberUsing the S command, you can search out the traceinformation in the trace memory.Where the "tm-mnemonic" is the element of thetrace information in the trace memory that youwish to search, and "data" is a value of thatelement. "number" is the time of an agreement.For example, Entering "S" PO 2 3", the emulatorsearches through the trace memory from the topand finds the pOSition where the trace PO data isequal to 2, three times, and displays the traceinformation at that position.393o

eEASE80C51mkll e------------------__ --------------------------DISK ACCESS COMMANDS1. LOD [dr:) filename Load Program into Code Memory2. SAV [dr:) filename [address adress) Save Code Memory Program3. VER [dr:) filename [address adress) Verify File with Code Memory4. DIAG [dr:) filename Execute command file5. LIST [dr:) filename List console Output into Disk file6. NLST End listing7. HELP Display HELP File8. FDD dr: ... dr: Set Disk DriveEPROM PROGRAMMER COMMANDS1. PPR address address [address) Program Code Memory into EPROM2. TPR address address [address) Transfer EPROM into Code Memory3. VPR address address [address) Verify EPROM with Code Memory4. TYPE mnemonic Set EPROM typeASSEMBLE COMMANDSI1. ASM address Assemble to Code Memory2. DASM address Disassemble to Console3. DBLK address [address) Display Block Memory4. SPB address [address) Set Program Block5. SDB address [address) Set Data BlockTRACE COMMANDSD1. DTM-numbernumber Display Trace Memory2. DFTM number number Display Flash Trace Memory3. DTG Display Trigger Mode4. DFA Display Flash Trace address5. S mnemonic data number Search Trace Memory data6. SFF mnemon ic Set Flash Trace Display format ,7. STG mnemonic Set Trigger Mode8. SFA address [... address) Set Flash Trace address9. RFA address [... address) Reset Flash Trace address10. RTG ResetTrigger ModeEMULATION COMMANDS1. STP number [number)2. G[st-address) [,break-parameter). If the optional st-address if given, emulator will begin emulation from st-address.And if optional break-parameter is given.emulation will break on the first break-parameter to be satisfied.break-parameter = break-address, ..... , break-address (max. 10)break-address (pass count)break-address RAM ram-address (byte-pass count)break-address sfr-mnemonic (byte-pass count)3. SSF (+/-) mnemonic [...(+/-) mnemonic)Set STP Command Display formatDISPLAY COMMANDS1. D Display Register Flag Port2. Dsfr-mnemonic Display sfr-mnemonicoata3. DSFR mnemonic [... mnemonic) Display mnemonic data4. DPC Display Program Counter5. DREG Display all Register Bank6. OSBUF Display receiver data394

------------------------------------------------e EASE80C51mkil eCHANGE COMMANDS.1. Csfr-mnemonic data Change sfr-mnemonic2. CSFR [mnemonic..,mnemonic! ChangeSFR3. CPCdata Change Program Counter4. CREGdata Change Register bank5. CSBUFdata Change Transmitter dataCODE MEMORY & DATA MEMORY COMMANDS1. DCM address [address! Display Code Memory2. DDM address [address! Display Data Memory3. DXDM address [address! Display External Data Memory4. CCMaddress Change Code Memory5. COM address Change Data Memory6. CXDM address Change External Data Memory7. FCM address address byte Fill Code Memory with byte8. FDM address address byte Fill Data Memory with byte9. FXDM address address byte Fill External Data Memory with byteATTRIBUTE MEMORY COMMANDS1. DBP address [address! Display Break Point Bit Memory2. DTR address [address! Display Trace Enable Bit Memory3. DSO address [address! Display Sync Output Enable Bit Memory4. DIE address [address! Display Instruction Executed Bit Memory5. EBP address ... address Enable Brak Point Bit6. ETR address ... address Enable Trace Enable Bit7. ESO address ... address Enable Sync Output Enable Bit8. FPB address address byte Fill Break Point Bit Memory with byte9. FTR address address byte Fill Trace Enable Bit Memory with byte10. FSO address address byte Fill Sync Output Enable Bit Memory with byte11. RBF\address ... address Reset Break Point Bit12. RTR'address ... address Reset Trace Enable Bit13. RSO address ... address Reset Sync Output Enable Bit14. RIE Reset Instruction Executed Bit MemoryBUFFER MEMORY COMMANDSD1. DBUF Display Buffer Memory2. TBUF Transfer Data Memory & SFR Data into Buffer Memory3. LBUF Load Buffer Memory into Data Memory & SFRCYCLE COUNTER COMMANDS1. DCC Display Cycle Counter2. CCCdata Change Cycle Counter3. TIME data Set 1 cycle timeBREAK CONDITION & STATUS COMMANDS1. DBC Display Break Condition2. DBS Display Break Status3. SBC (+/-) mnemonic .. (+/-) mnemonic Set BreakOTHER COMMANDS1. RES EASE80C51 mKIl System initialization2. RESE MSM83C154E Evachip reset3. SIOForH Set Emulator to I/O terminal mode4. PAUSE Stop command file execution and wait key-in5. EXIT Return Host computer's OS6. DIR[dr:! Display file directory7. MAP [address! Mapping8. MAC Define command execution9. M Execute Defined command10. @ Repeat front com mand11. M80C51 Set Emulatortothe MSM80C51 checking mode12. M83C154 Set Emulatortothe MSM83C154 checking mode395

• EASE80C51 mkll .------------------------EASE80C51mkil PROGRAM DEVELOPMENT SUPPORT SYSTEMfor the MSM83C154/80C51 CMOS 8-BIT 1-CHIP MICROCONTROLLERClockMode switchr----,select switchReset SWit\ \AC powerconnectorCrystal oscillatorconnectorProbe cableconnectorEPROM programmerUser cableconnectorRS232Cconnector300 (W) x 105 (D) x 210 (H) mmCategory Model name Component nameoHardware EASE80C51 mkll Emulation kit for MSM83C154/80C51Emulation kitSoftware EASE Host monitor for floppy disk based (Note 2)ASM 51 Assembler for floppy disk based (Note 2)Manuals TM-80C51 EASE80C51 mkll Emulator User's ManualAM-80C51ASM51 Assembler User's ManualAccesories TCU-80C51 User application circuit connection cableTCS-n Host computer connection cable (3) (Note 3)TCP-2AC power supply cableTCX-2Em ulation probe cableNote 1. Refer to the ASM51 Assembler User's Manual for assembler details.Note 2. PCDOS 51 /4 floppy disk, PC format, double-side double-density (8 sectors x 40 tracks x 2)PC DOS stands for IBM personal computer DOS.CP/M-80 8-inch floppy disk, IBM3? 40 soft-sectored format, single-side single-density.CP/M-80 is the registered trademark of Digital Research Co.Note 3. Two cables are used for connecting the if800 or equivalent computer to the EASE80C51 mkllEmulation Kit-one to the CH1 port, and the other to the CH2 port. (Model name, TCS-2)The third cable is for connection of an IBM PC or equivalent computer to the EASE80C51 mkllEmulation Kit. This calbe is connected to the CH1 port. (Model name, TSC-3).396

--------------------------------~-----------. EASE80C51mkll •OPTIONAL SOFTWARENameOSCP/M-BO MS-DOS PC-DOS VMS UNIXSupplied softwarePASM 0 0 0· ·Pre-ProcessorMAC51 0 0 0 Macro-AssemblerRL51 0 0 0 Linker· ·LIB51 0 0 0 · ·LibrarianSID51 0 0 · ·Symbolic DebuggerOBJHEX. 0 0 · ·Object ConverterOPTIONAL HARDWARE• ·····Seing developedTypeEASEBRemarksHandy 1/0 terminalEASE8 can be used as a terminal unit for the EASE80C51 mkll Emulation Kit.(Convenient portable model)o397

MAC51 SUPPORT SOFTWARE PAC~GEfor theMSM80C51 CMOS 8-BIT MICROCONTROLLERIJFEATURES1. Symbolic relocatable assembly language programmingfor 80C51 1154 microcontrollers2. Produces Relocatable Object Code which islinkable to other 8051 Object Modules3. Encourages modular program design formaintainability and reliability4. Macro Assembler features conditional assemblyand macro capabilitiesMAC51 SUPPORT SOFTWARE PACKAGEThe following MAC51 programs are availableto develop user programs.PASM Pre-processorPASM is used to expand macro calls,conditional assembly statements, and INCLUDEstatements included in user generated sourceprograms, thereby generating expanded sourceprograms. A number of items of developmentinformation are inserted in these developedsource programs for MAC51 .MAC51 AssemblerMAC51 converts source programs intorelocatable codes to form relocatable object files(OBJ files). Print, symbol, cross reference, anderror files are generated as assemblyinformation.LIB51 LibrarianThe LlB51 program manages OBJ files foreach module. Files consisting of a number ofrelocatable object modules (OBJ modules)generated by LlB51 are called the object library.LlB51 handles object library generation, andOBJ module addition, deletion, and upgrading.RL51 LinkerRL51 links and relocates one or more OBJmodules to generate one absolute objectmodule. RL51 also generates a list fileconsisting of symbol table and link map as linkinformation. OBJ modules which serve as theRL51 input can be OBJ files generated byMAC51, and OBJ modules located within theobject library generated byLlB51.SID51 Symbolic debugger'SID51 is used when a symbol usingdebugger is selected. Absolute object files areconverted to Intellec HEX format files.Outline of Program DevelopmentThe procedures involved in the processingfrom source program generation through ROM .loading are described below in the sequenceindicated in Figure 1-1. For further details ofindividual utilities, refer to the respectivemanuals.398

----------------------------. MAC51 •1. Generation of MAC51 assembly languagesource program by the editor.Source programs can contain basic andpseudo instructions, and assembler control,macro call, conditional assembly, andINCLUDE statements.2. When macros are used, macro definitions aregenerated in macro library files (with MACextension) by the editor. Macro callstatements are described within sourceprograms.3. Where macro call, conditional assemblystatement, and INCLUDE statementdescriptions are included in a sourceprogram, there are expanded by PASM toform an expanded source program.4. Source programs or expanded sourceprograms are assembled by MAC51 to formrelocatable object files.5. A group of relocatable object files can bemanaged by LlB51 together in a relocatableobject library files (LIB extension). Whenrequired, object modules can be called fromthis object library by RL51.6. Relocatable object files are converted toabsolute object files by RL51. At this stage,one or more relocatable object files can belinked to relocatable object modules in thelibrary file.7. ABS modules are converted by SID51 orOBJHEX to Intellec HEX format files. WithEASE80C51 mkll, HEX file contents can bewritten into EPROM devices .o5.EASE80C51mkilFig. 1 -1 Program development flow399

Note: Product data and specification information herein are subject tochange without advance notice for the sake of technical improvements inperformance and reliability since OKI is permanently endeavoring to supplythe best products possible. The manufacturer does not assume responsibilityfor customer product designs and for the fitness to any particularapplication, nor for patent rights or other rights of third parties and infringementsthereof resulting from the use of his products. This publication doesnot commit immediate availability of the product(s) described by it. If indoubt, please . contact your nearest OKI representative. The informationfurnished by OKI is believed to be accurate and reliable. However, noresponsibility is assumed for inaccuracies that may not have been detectedprior to printing, and for those whi ch occur beyond our contro l. Thi s issuesubstitutes and supersedes all publications previously supplied by OKI forthe captioned product(s). This document may not, in wh ole or part, becopied, photocopied, reproduced, translated, or converted to any machinereadable form, without prior written consent from OK!.OKI Semiconductor650 North Mary Avenue, Sunnyvale, CA #94086, U.S.A.Q Tel: (408)720-1900 QFax : (408)720 -1918 0 Telex : 296687 OKI SNTAFOR FURTHER INFORMATION PLEASE CONTACT :OKI ELectric Industry Co., Ltd,Head Office Annex10·3, Shibaura, 4·chome,Minato ·k~ , Tokyo tOO, JapanTel : 3- 454-2tttFax : 3- 798- 7643Telex . J22627Electronic Devices GroupOverseas Marketing Dept.OKI Semiconductor650 North Mary Avenue,Sunnyvale, CA #94086, U.S.ATel : (408 ) 720- 1900Fax : (408) 720- 1918OKI Electric Europe GmbHNiederkasseler Lohweg 8,0 - 4000 Dusseldorf II ,Fed . Rep . of GermanyTel ' 0211 - 59550Telex : 296687 OKI SNTA Fax : 0211 - 591669Telex 858- 4312OKI Electronics (Hong Kong) Ltd.16th Floor, Fairmont House,8 Cotton Tree Drive, Hong KongTel 5- 263111Fax : 5- 200102Telex . 62459 OKIHK HXPrinted in USA