1.1.1. I2C Registers (Base Address Refers to the Register ... - RoBoard

NaBitAttributeme3 ARL R/WC2 SlaveSTP R/WC1 BBUSY RO0 MS_ RODescription1: Arbitration loss .Write 1 to this bit will clear to “0”1: Slave receive STOP conditionWrite 1 to this bit will clear to “0”The bus is considered to be busy after the Start condition and free again at a certaintime interval after the Stop condition.1 : Master mode (Default)0 : Slave modeRegister Offset:Register Name:Reset Value:BA + AhI2C1 My_Address Register00h7 6 5 4 3 2 1 0My Slave AddressRsvdNaBitAttributeme7-1 My_Addr R/WDescription7-bits slave address which is checked by internal slave module. If address is match itwill switch to slave mode. Processor can write proper value into this register to identifyitself0 Rsvd RO ReservedRegister Offset:Register Name:Reset Value:BA + BhI2C1 Transmit Address Register00h7 6 5 4 3 2 1 0TX Slave AddressR/WNaBitAttributeme7-0 TX_Addr R/WDescription8-bit address register for Master to start a transaction. Processor can write this registerto generate START + Slave Address + R/W on i2c bus. If Processor write a macrocodeinto this register, it will send out macrocode and switch to high-speed mode at propertiming.

Register Offset:Register Name:Reset Value:BA + ChI2C1 Transmit/Receive Data Register00h7 6 5 4 3 2 1 0DataBitNameAttributeDescription7-0 Data R/W8-bit data register for I 2 C-bus Tx/Rx operation. Processor can write this register totransmit DATA or read this register to receive dataRegister Offset:Register Name:Reset Value:BA + DhI2C1 Clock Frequency Control10ah7 6 5 4 3 2 1 0PreScale1BitNameAttributeDescriptionProcessor can write this register value from 0 to 255 to control the frequency of SCLH7-0 PreScale1 R/WAt high speed Mode, SCLH frequency = 33M÷(PreScale1),PS: If PreScale1 < 10, SCLH frequency = 33M÷10 = 3.3MhzRegister Offset:Register Name:Reset Value:BA + EhI2C1 Clock Frequency Control288h7 6 5 4 3 2 1 0FastPreScale2BitNameAttributeDescription7 Fast R/W 1: Fast mode , 0: Standard Mode6-0 PreScale2 R/WProcessor can write this register value from 0 to 255 to control the frequency of SCLAt F/S Mode, SCL frequency = 33M÷(PreScale1) ÷(PreScale2+1)

Register Offset:Register Name:Reset Value:BA + FhI2C1 Extra Control Register00h7 6 5 4 3 2 1 0I2c_RST TX_hit_RX RsvNaBitAttribute Descriptionme7 I2c_RST R/WWrite “1” will reset i2c controller except pre-scale registers (for keep the speedsetting). After reset, Controller will send out 10 dummy clocks to ensure no any slavedriving data because of incomplete operation of the Master (maybe other master),auto clear after reset complete.6 TX_hit_RX R/OIndicate the TX address is written but may not send out because the slave is drivingfirst bit of data on bus,After data in rx_buffer is read back by software , hardware will continue to read slaveand nak it at the end, then send re-start + address.5-0 Rsv RO Reserved