GPU Performance Analysis and Optimization - GPU Technology ...

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instructions / timeExecution diverges within a warp0 1 2 3 30 3132 33 34 35 62 63© 2012, NVIDIA102
Possible <strong>Performance</strong> Limiting Factors• Raw instruction throughput– Know the kernel instruction mix– fp32, fp64, int, mem, transcendentals, etc. have different throughputs• Refer to the CUDA Programming Guide / Best Practices Guide• Can examine assembly: use cuobjdump tool provided with CUDA toolkit– A lot of divergence can “waste” instructions• Instruction serialization– Occurs when threads in a warp issue the same instruction in sequence• As opposed to the entire warp issuing the instruction at once• Think of it as “replaying” the same instruction for different threads in a warp– Mostly:• Shared memory bank conflicts• Memory accesses that result in multiple transactions (scattered address patterns)103
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Goals of This Talk• Give insight
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Topics For Ninjas• Topics relevan
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EXPOSING SUFFICIENT PARALLELISM© 2
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Memory Parallelism• Achieved Kepl
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Occupancy• Occupancy: number of c
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Exposing Parallelism: Grid Configur
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Threadblock SizingToo fewthreadsper
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Case Study 1: Threadblock Sizing•
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Tail Effect• Tail underutilizes G
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Tail Effect: Large vs Small Threadb
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General Guidelines• Threadblock s
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Kepler Memory HierarchySM-0Register
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Blocking for L1, Read-only, L2 Cach
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Global Memory Operations• Memory
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Read-only Loads• Go through the r
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Read-only Loads• Go through the r
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Caching Load• Scenario:- Warp req
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Caching Load• Scenario:- All thre
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Memory Throughput Analysis• Two p
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Two Ways to Investigate Address Pat
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Pattern Category: Offset Access•
Page 52 and 53: Case Study 2: Offset Address Patter
Page 54 and 55: Case Study 2: Remedy• Looking at
Page 56 and 57: Pattern Category 2: Large Inter-thr
Page 58 and 59: Case Study 3: Diagnosis• Double-p
Page 60 and 61: Case Study 3: Result• Naïve impl
Page 62 and 63: Case Study 4: SoA vs AoS• Global
Page 64 and 65: Case Study 4: Cause• Array of Str
Page 66 and 67: Case Study 5: Assigning More Thread
Page 68 and 69: Case Study 5: Cause and Remedy• E
Page 70 and 71: Pattern Category 4: Irregular Addre
Page 72 and 73: Summary of Pattern Categories and t
Page 74 and 75: Having Sufficient Concurrent Access
Page 76 and 77: Optimizing Access Concurrency• Ha
Page 78 and 79: Summary: GMEM Optimization• Striv
Page 80 and 81: Shared Memory• On-chip (on each S
Page 82 and 83: Kepler 8-byte Bank Mode• Mapping
Page 84 and 85: Kepler 4-byte Bank Mode• To visua
Page 86 and 87: Case Study 6: Kepler 8-byte SMEM Ac
Page 88 and 89: SMEM Access ExamplesAddresses from
Page 94 and 95: Case Study 7: Matrix Transpose• S
Page 96 and 97: Summary: Shared Memory• Shared me
Page 98 and 99: Execution• Instructions are issue
Page 100 and 101: instructionsControl Flowif ( ... ){
Page 104 and 105: Instruction Throughput: Analysis•
Page 106 and 107: Instruction Throughput: Summary•
Page 108 and 109: Kepler Architecture Family• Two a
Page 110 and 111: Level of Parallelism• Parallelism
Page 112 and 113: Increased Shared Memory Bandwidth
Page 114 and 115: Case Study 8: More Registers Per Th
Page 116 and 117: In Conclusion• When programming a
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