KB3700

KB3700 Keyboard Controller Datasheet5 R/W Enable IRQ12 SIRQ4 R/W Enable IRQ1 SIRQ3 – 0 R/WSCI Serial IRQ channel0: no1:IRQ12:SMI#3:IRQ3…15:IRQ1592h93hLPCIBAHLPCIBALLPC Index IO Base Address7 – 0 R/WEC index mode IO port base address.The address should be 4 bytes align.FFh2ChFEhLPC FWH Configuration 094hLPCFWH7 – 6 R/WMemory Size (both for LPC Memory and FWH)00: 256KB01: 512KB10: 1MB11: 2MB0FEh95h96h97h98h99hLPCCFGLPCXBAHLPCXBALLPCEBAHLPCEBAL5 R/W Enable FWH memory cycle4 R/W Enable FWH IDSEL check3 – 0 R/W FWH IDLPC Configuration7 R/W Enable LPC memory write protection (including FWH)6 R/W Enable index IO port5 R/W Enable KBC IO port: 60h, 64h4 R/W Enable Extended IO port (IO write only)3 R/W Enable EC IO port2 R/W Enable LPC memory cycle (not including FWH)1 R/W Enable SIRQ fixed in continuous mode0 R/W Enable LPC CLKRUN#LPC Extended IO Base AddressOnly LPC byte write is supportedLPC EC IO Base AddressLPCEBAL bit 0 and bit 1 are not ignored for decodingAddress 2EF decoding and control in LPC(Internal Use Only)9Ah LPC_2EF B0h FEh80h00h80h00h62hFEhFEhFEhAddress 2EF decoding and control in LPC(NOTE: Internal Use Only)7~4 RSV9AhLPC_2EF3 R Decode IO(0x002F): 0:read_io_2f, 1:write_io_2f2 R/RWDecode IO(0x002F) r/w cycle, should cleared by FWWrite 1 to clear the value.1 R/W Enable interrupt of read/write_io(2f)0 R/W Enable decode read_io(2e), read/write_io(2f)9Bh7~0 RSVLPC_2F_DATA9Ch LPC_2F_DATA7~0 RO Read data for read_cycle_IO(2F)9DhLPC68CFGLPC 68/6Ch IO Configuration07 R/W Enable LPC I/F decode IO 68h, 6Ch6~2 RSVCopyright©2006, ENE Technology Inc. 23