SFF-8449 - HD MANAGEMENT INTERFACE v1.1

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1SFF Committee documentation may be purchased in hard copy or electronic form.SFF specifications are available at ftp://ftp.seagate.com/sffSFF CommitteeSFF-8449 Specification forHD MANAGEMENT INTERFACERev 1.1 May 5, 2010Secretariat: SFF CommitteeAbstract: This specification defines a common management interface for shieldedcable assemblies. Physical layer and mechanical details of the connector interfaceare outside the scope of this document.This specification provides a common reference for systems manufacturers, systemintegrators, and suppliers. This is an internal working specification of the SFFCommittee, an industry ad hoc group.This specification is made available for public review, and written comments aresolicited from readers. Comments received by the members will be considered forinclusion in future revisions of this specification.Support: This specification is supported by the identified member companies of theSFF Committee.POINTS OF CONTACT:Barry OlawskyI. Dal AllanHewlett PackardChairman SFF Committee11445 Compaq Center Drive West 14426 Black Walnut CourtHouston, TX 77070 Saratoga CA 95070Ph:281-514-8624 Ph: 408-867-6630barry.olawsky@hp.com endlcom@acm.orgHD Management Interface Page 1

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1EXPRESSION OF SUPPORT BY MANUFACTURERSThe following member companies of the SFF Committee voted in favor of this industryspecification.TBDThe following member companies of the SFF Committee voted against this industryspecification.TBDThe following member companies of the SFF Committee voted to abstain on thisindustry specification.TBDThe user's attention is called to the possibility that implementation to thisSpecification may require use of an invention covered by patent rights. Bydistribution of this specification, no position is taken with respect to thevalidity of a claim or claims or of any patent rights in connection therewith.Members of the SFF Committee which advise that a patent exists are required toprovide a statement of willingness to grant a license under these rights onreasonable and non-discriminatory terms and conditions to applicants desiring toobtain such a license.HD Management Interface Page 2

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1ForewordThe development work on this specification was done by the SFF Committee, anindustry group. The membership of the committee since its formation in August 1990has included a mix of companies which are leaders across the industry.When 2 1/2" diameter disk drives were introduced, there was no commonality onexternal dimensions e.g. physical size, mounting locations, connector type, andconnector location, between vendors.The first use of these disk drives was in specific applications such as laptopportable computers and system integrators worked individually with vendors todevelop the packaging. The result was wide diversity, and incompatibility.The problems faced by integrators, device suppliers, and component suppliers led tothe formation of the SFF Committee as an industry ad hoc group to address themarketing and engineering considerations of the emerging new technology.During the development of the form factor definitions, other activities weresuggested because participants in the SFF Committee faced more problems than thephysical form factors of disk drives. In November 1992, the charter was expanded toaddress any issues of general interest and concern to the storage industry. The SFFCommittee became a forum for resolving industry issues that are either not addressedby the standards process or need an immediate solution.Those companies which have agreed to support a specification are identified in thefirst pages of each SFF Specification. Industry consensus is not an essentialrequirement to publish an SFF Specification because it is recognized that in anemerging product area, there is room for more than one approach. By making thedocumentation on competing proposals available, an integrator can examine thealternatives available and select the product that is felt to be most suitable.SFF Committee meetings are held during T10 weeks (see www.t10.org), and SpecificSubject Working Groups are held at the convenience of the participants. Materialpresented at SFF Committee meetings becomes public domain, and there are norestrictions on the open mailing of material presented at committee meetings.Most of the specifications developed by the SFF Committee have either beenincorporated into standards or adopted as standards by EIA (Electronic IndustriesAssociation), ANSI (American National Standards Institute) and IEC (InternationalElectrotechnical Commission).If you are interested in participating or wish to follow the activities of the SFFCommittee, the signup for membership and/or documentation can be found at:www.sffcommittee.com/ie/join.htmlThe complete list of SFF Specifications which have been completed or are currentlybeing worked on by the SFF Committee can be found at:ftp://ftp.seagate.com/sff/SFF-8000.TXTIf you wish to know more about the SFF Committee, the principles which guide theactivities can be found at:ftp://ftp.seagate.com/sff/SFF-8032.TXTSuggestions for improvement of this specification will be welcome. They should besent to the SFF Committee, 14426 Black Walnut Ct, Saratoga, CA 95070.HD Management Interface Page 3

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1SFF Committee -Common Management Interface1. Scope ..........................................................................................................................51.1 Description of Clauses............................................................................................52. References.......................................................................................................52.1 Industry Documents .....................................................................................................52.2 SFF Specifications .....................................................................................................62.3 Sources................................................................................................................................62.4 Conventions.........................................................................................................................63. Definitions ....................................................................................................63.1 Fixed versus Free........................................................................................................63.1.1 Fixed.................................................................................................................................63.1.2 Free ...................................................................................................................................63.2 Passive Cable .................................................................................................................63.3 Active Cable....................................................................................................................74. General Description .................................................................................74.1 Fixed-to-Free Side Block Diagram....................................................................74.2 Physical Cable Assembly Implementation .....................................................84.2.1 Direct Attach..............................................................................................................84.2.2 Separable .......................................................................................................................94.2.3 Management Interface Scope...............................................................................95. High Density (HD) Connector Physical Layer Interface105.1 Signal Assignment......................................................................................................105.2 High Speed Serial Interface..............................................................................115.3 Management Interface...............................................................................................115.3.1 Signal Definition ..................................................................................................115.3.1.1 Vman..............................................................................................................................115.3.1.2 Vact..............................................................................................................................115.3.1.3 ModPrsL.......................................................................................................................125.3.1.4 IntL..............................................................................................................................125.3.1.5 SCL ................................................................................................................................125.3.1.6 SDA ................................................................................................................................125.3.2 Free Side Device Addressing ..........................................................................125.4 ........................................................................................................................................................125.4.1 DC Electrical Characteristics .....................................................................125.4.1 Absolute Maximum/Minimum Ratings ..............................................................135.5 Timing Requirements.................................................................................................135.6 Power Consumption Modes .......................................................................................155.6 Power Supply Filtering Network.......................................................................165.X Squelch..............................................................................................................................175.X.1 RX Squelch .....................................................................................................................175.X.2 TX Squelch (optional)...........................................................................................17HD Management Interface Page 4

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1SFF Committee --Common Management Interface1. ScopeThis specification defines a management interface for SFF-8644 external cableassembly implementations. The detailed mechanical design is documented in SFF-8644.The interface memory map and protocol operation are also outside the scope of thisspecification but can be found in SFF-8636. This document provides a detaileddescription of the electrical interface characteristics.This approach facilitates a common memory map and management interface forapplications with different mechanical, physical layer and otherwise differentimplementations. For example, SFF-8449 defines a four channel solution whichdocuments the management interface physical layer, references SFF-8636 to ensurecompatibility with the common memory map and protocol. See figure 1.Figure 1 Hierarchy of Interface Specifications (Example)Note that SFF-8636 memory map is shared amongst multiple standards. SFF-8636 mayinclude signals beyond the scope of the SFF-8449 interface.1.1 Description of ClausesClause 1 contains the scope and purposeClause 2 identifies referenced and related standards and SFF specificationsClause 3 lists the definitions and conventionsClause 4 provides a general descriptionClause 5 describes the two-wire interfaceClause 6 details the common memory map for managed external interfaces2. ReferencesThe SFF Committee activities support the requirements of the storage industry, andit is involved with several standards.2.1 Industry DocumentsThe following interface standards and specifications are relevant to thisspecification.HD Management Interface Page 5

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.12.2 SFF SpecificationsThere are several projects active within the SFF Committee. The complete list ofspecifications which have been completed or are still being worked on are listed inthe specification at ftp://ftp.seagate.com/sff/SFF-8000.TXT2.3 SourcesThose who join the SFF Committee as an Observer or Member receive electronic copiesof the minutes and SFF specifications (http://www.sffcommittee.com/ie/join.html).Copies of ANSI standards may be purchased from the Inter-National Committee forInformation Technology Standards (http://tinyurl.com/c4psg).Copies of SFF, ASC T10 (SCSI), T11 (Fibre Channel) and T13 (ATA/SATA) standardsstill in development are available on the HPE version of CD_Access(http://tinyurl.com/85fts).2.4 ConventionsThe American convention of numbering is used (i.e., a comma separates the thousandsand higher multiples, and a period is used as the decimal point). This is equivalentto the ISO/IEC convention of a space and comma.American ISO0.6 0,61,000 1 0001,323,462.9 1 323 462,93. Definitions3.1 Fixed versus Free3.1.1 FixedThe terminology "fixed" is used to describe the gender of the mating side of theconnector that accepts its mate upon mating. This gender is frequently, but notalways, associated with the common terminology "receptacle". Other terms commonlyused are "female" and "socket connector". The term "fixed" is adopted from EIAstandard terminology as the gender that most commonly exists on the fixed end of aconnection, for example, on the board or bulkhead side.3.1.2 FreeThe terminology "free" is used to describe the gender of the mating side of theconnector that penetrates its mate upon mating. This gender is frequently, but notalways, associated with the common terminology "plug". Other terms commonly used are"male" and "pin connector". The term "free" is adopted from EIA standard terminologyas the gender that most commonly exists on the free end of a connection, forexample, on the cable side.3.2 Passive CableIn this standard, a passive cable only requires power to operate the managementinterface circuitry.HD Management Interface Page 6

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.13.3 Active CableIn this standard, an active cable requires power for circuitry that is integral toany of the TX/RX high speed serial channels supported by the cable. In addition, theactive cable requires power to operate the management interface.4. General DescriptionThe external cable management interface provides a method for the fixed side todetermine the characteristics and status of the free side. In some implementations,the interface also provides a mechanism to control the operation of the free sidecircuitry. For the case where the free side is a cable, the fixed side can determineif the cable is passive, active copper, or active optical. Parameters such assupplier, part number, propagation delay and loss (for passive cables) can also bedetermined.4.1 Fixed-to-Free Side Block DiagramFigure 2 depicts the fixed-to-free side management interface. Note the limitationsin scope of SFF-8636.HD Management Interface Page 7

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1FREE SIDEFREE SIDEFIXED SIDEFigure 3 Direct Attach Cable Assembly Implementation4.2.2 SeparableFigure 4 depicts a separable active copper and optical cable interconnectimplementation.FREESIDETHIS INTERFACE ISOUTSIDE THE SCOPEOF THIS SPECIFICATIONFREESIDEFIXEDSIDEFigure 4 Separable Cable Assembly Implementation4.2.3 Management Interface ScopeFigure 5 depicts the limited scope of the management and active cable powerinterfaces. Note that management and power interfaces do not extend from one freeside end of the cable to the other.HD Management Interface Page 9

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1FIXEDSIDEFREESIDEFREESIDEFIXEDSIDEMANAGEMENTINTERFACEPOWERINTERFACEMANAGEMENTINTERFACEPOWERINTERFACEHIGH SPEEDSERIAL INTERFACEFigure 5 Management Interface Scope5. High Density (HD) Connector Physical Layer Interface5.1 Signal AssignmentThe fixed and free-side HD connector interface supports four bi-directional highspeed differential serial links and a management interface. Table 1 identifies allsignals of the connector interface.Signal Pin Mating DefinitionLevelReserved A1 Second Reserved for future useIntL A2 Second Management interface interrupt signalGND A3 First Signal groundRX1+ A4 Third Fixed side receiver channel 1 non-inverting inputRX1- A5 Third Fixed side receiver channel 1 inverting inputGND A6 First Signal groundRX3+ A7 Third Fixed side receiver channel 3 non-inverting inputRX3- A8 Third Fixed side receiver channel 3 inverting inputGND A9 First Signal groundVact B1 Second Free side power input for non-management interfacecircuitryModPrsL B2 Second Free side active low present outputGND B3 First Signal groundRX0+ B4 Third Fixed side receiver channel 0 non-inverting inputRX0- B5 Third Fixed side receiver channel 0 inverting inputGND B6 First Signal groundHD Management Interface Page 10

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1RX2+RX2-GNDSCLSDAGNDTX1+TX1-GNDTX3+TX3-GNDVactVmanGNDTX0+TX0-GNDTX2+TX2-GNDB7 Third Fixed side receiver channel 2 non-inverting inputB8 Third Fixed side receiver channel 2 inverting inputB9 First Signal groundC1 Second Management interface serial clockC2 Second Management interface serial data outputC3 First Signal groundC4 Third Fixed side transmitter channel 1 non-inverting outputC5 Third Fixed side transmitter channel 1 inverting outputC6 First Signal groundC7 Third Fixed side transmitter channel 3 non-inverting outputC8 Third Fixed side transmitter channel 3 inverting outputC9 First Signal groundD1 Second Free side power input for non-management interfacecircuitryD2 Second Free side power input for management interfacecircuitryD3 First Signal groundD4 Third Fixed side transmitter channel 0 non-inverting outputD5 Third Fixed side transmitter channel 0 inverting outputD6 First Signal groundD7 Third Fixed side transmitter channel 2 non-inverting outputD8 Third Fixed side transmitter channel 2 inverting outputD9 First Signal groundTable 1 HD Connector Physical Layer Interface5.2 High Speed Serial InterfacePins A4, A5, A7, A8, B4, B5, B7, B8, C4, C5, C7, C8, D4, D5, D7 and D8 are outsidethe scope of this document.5.3 Management InterfacePins A1, A2, B1, B2, C1, C2, D1 and D2 comprise the management interface. Note thatGND pins A3, A6, A9, B3, B6, B9, C3, C6, C9, D3, D6 and D9 are required for reliablemanagement interface operation although they are not classified as part of themanagement interface.5.3.1 Signal Definition5.3.1.1 VmanThe fixed-side shall provide power for the free-side device management interfacecircuitry on the Vman signal. Removal of power from the Vman signal shall disablethe free-side management circuitry. Upon restoration of power to the Vman signal,the management interface shall perform all necessary power up tasks. The SFF-8449management interface does not include a dedicated reset signal. To reset the freesidemanagement interface circuitry, the fixed side may cycle power off and on. Seetable TBD for Initialization Time requirements, signal levels and other resetcircuitry parameters.5.3.1.2 VactTo support active cable designs, the fixed side shall provide power to both Vactpins in addition to the Vman pin. Designs not supporting active cables terminateVact as specified in table TBD. Timing requirements are detailed in table TBD.HD Management Interface Page 11

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.15.3.1.3 ModPrsLThe fixed-side shall de-assert the active-low ModPrsL signal. When mated with thefixed side, the free-side device shall assert ModPrsL low. See table TBD forelectrical characteristics of the signal, fixed-side and free-side terminationcharacteristics.5.3.1.4 IntLThe fixed-side shall de-assert the active-low ModPrsL signal. The free-side deviceshall assert IntL low to indicate that an event has occurred that requires interruptservice. The free-side device shall de-assert IntL after the fixed side has clearedthe appropriate interrupt flag bits within the free-side device memory map. Inaddition, the free-side device indicates completion of power up initialization byposting an IntL signal with the Data_Not_Ready (See SFF-8636) bit negated. See tableTBD for electrical characteristics of the signal, fixed-side and free-sidetermination characteristics.5.3.1.5 SCLTwo-wire interface clock.5.3.1.6 SDATwo-wire interface data.5.3.2 Free Side Device AddressingThe SFF-8449 management interface does not provide a mechanism to address individualfree-side devices. The fixed-side shall provide an independent physical layerinterface for each free-side device. Multiple free-side devices shall not share thesame clock and data signals.5.45.4.1 DC Electrical CharacteristicsSignal Symbol Min Max Unit ConditionVol 0 0.4 V Iol(max)=3.0mASCL, SDA Voh Vman-0.5 Vman+0.3 VVil -0.3 Vman*0.3 V(see note 1) Vih Vman*0.7 Vman+0.5 VVol 0 0.4 VModPrsL, IntL Voh Vman-0.5 Vman+0.3 V Iol=2.0mAVil -0.3 Vman*0.3 V(see note 1) Vih Vman*0.7 Vman+0.5 VManagement InterfacePower Supply Voltage Vman 1.7 3.6 VManagement InterfacePower Supply Current Iman - 8 mAActive Circuitry PowerSupply Voltage Vact - 3.6 VVin(nom) = 3.3V, 1Wfree side consumptionActive Circuitry PowerSupply Current Iact - 300mA mAMust add other casesfor reduced power andHD Management Interface Page 12

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1input voltageNote 1. Fixed side termination to Vman between 4.7KOhm and 10KOhm5.4.1 Absolute Maximum/Minimum RatingsTable 2. DC Electrical CharacteristicsSignal Min Max Unit ConditionVman -0.3 3.6 VVact -0.3 3.6 VSCL, SDA, ModPrsL, IntL -0.3 Vman+1.0 V With respect to GNDDifferential High SpeedSerial Receiver Inputs -0.3 1.6 V Peak-to-peak differentialInput capacitance forSCL and SDA - 14 pFTable 3. Absolute Maximum/Minimum Ratings5.5 Timing RequirementsThe free side device software control and status function timing specifications aredescribed in Table 4. Free side device timing parameters involving memory mapparameters are specified in table TBD.Table 4. Timing for soft control and status functionsParameter Symbol Max Unit ConditionsInitializationTimet_init 2000 ms Time from power on 2 or hot plug eventuntil the free side device is fullyfunctional 3 . This parameter does notapply to passive free side devices.Does not include delay due to deviceSerial BusHardware ReadyTimeMonitor DataReady TimeLPMode AssertTimeIntL AssertTimeIntL DeassertTimeRx LOS AssertTimeTx Fault AssertTimeFlag AssertTimet_serialt_datainterrogation.2000 ms Time from power on 2 until the free sideresponds to data transmission over the2-wire serial bus2000 ms Time from power on 2 to data not ready,IntL asserted and bit 0 of Byte 2,deasserted. See SFF-8636.ton_LPMode 100 us Time from assertion of LPMode (referto LPMode state or bits?) until modulepower consumption does not exceedPower Level 1. See SFF-8636.ton_IntL 200 ms Time from occurrence of conditiontriggering IntL until Vout:IntL=Voltoff_IntL 500 us Time from clear on read 4 operation ofassociated flag until Vout:IntL=Voh.This includes deassert times for RxLOS, Tx Fault and other flag bits. SeeSFF-8636.ton_los100 ms Time from Rx LOS state to Rx LOS bitset (value = 1b) and IntL asserted.See SFF-8636.ton_Txfault 200 ms Time from Tx Fault state to Tx Faultbit set (value = 1b) and IntLasserted. See SFF-8636.ton_flag200 ms Time from occurrence of conditiontriggering flag to associated flag bitHD Management Interface Page 13

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1Mask AssertTimeMask DeassertTimeApplication orRate SelectChange TimePower_over-rideor Power-setAssert TimePower_over-rideor Power-setset (value = 1b) and IntL asserted.See SFF-8636.ton_mask 100 ms Time from mask bit set (value = 1b) 1until associated IntL assertion isinhibited . See SFF-8636.toff_mask 100 ms Time from mask bit cleared (value =0b) 1 until associated IntL operationresumes. See SFF-8636.t_ratesel 100 ms Time from change of state ofApplication or Rate Select bit 1 untiltransmitter or receiver bandwidth isin conformance with appropriatespecification. See SFF-8636.ton_Pdown 100 ms Time from P_Down bit set (value = 1b) 1until module power consumption reachesPower Level 1. See SFF-8636.toff_Pdown 300 ms Time from P_Down bit cleared (value =0b) 1 until the module is fullyfunctional 3 See SFF-8636.Deassert TimeNote 1. Measured from falling clock edge after stop bit of write transactionNote 2. Power on is defined as the instant when supply voltages reach andremain at or above the minimum level specified in Table TBDNote 3. Fully functional is defined as IntL asserted due to data not readybit, bit 0 byte 2, deasserted. The module should also meet optical andelectrical specifications.Note 4. Measured from falling clock edge after stop bit of read transactionTiming requirements for TX and RX squelch and disable controls are defined in table5.Table 5. Squelch & Disable Control TimingParameter Symbol Max Unit ConditionsRx SquelchAssert Timeton_Rxsq 80 us Time from loss of Rx input signaluntil the squelched outputRx SquelchDeassert TimeTx SquelchAssert TimeTx SquelchDeassert TimeTx DisableAssert TimeTx DisableDeassert TimeRx OutputDisable AssertTimeRx OutputDisable DeassertTimeSquelch DisableAssert Timecondition is reached.toff_Rxsq 80 us Time from resumption of Rx inputsignals until normal Rx outputcondition is reached.ton_Txsq 400 ms Time from loss of Tx input signaluntil the squelched outputcondition is reached.toff_Txsq 400 ms Time from resumption of Tx inputsignals until normal Tx outputcondition is reached.ton_txdis 100 ms Time from Tx Disable bit set(value = 1b) 1 until optical outputfalls below 10% of nominal. SeeSFF-8636.toff_txdis 400 ms Time from Tx Disable bit cleared(value = 0b) 1 until optical outputrises above 90% of nominal. SeeSFF-8636.ton_rxdis 100 ms Time from Rx Output Disable bitset (value = 1b) 1 until Rx outputfalls below 10% of nominal. SeeSFF-8636.toff_rxdis 100 ms Time from Rx Output Disable bitcleared (value = 0b) 1 until Rxoutput rises above 90% of nominal.See SFF-8636.ton_sqdis 100 ms This applies to Rx and Tx Squelchand is the time from bit set1HD Management Interface Page 14

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1Squelch DisableDeassert Time(value = 0b) 1 until squelchfunctionality is disabled. SeeSFF-8636.toff_sqdis 100 ms This applies to Rx and Tx Squelchand is the time from bit cleared(value = 0b) 1 until squelchfunctionality is enabled. See SFF-8636.Note 1: Measured from falling clock edge after stop bit of write transaction5.6 Power Consumption ModesThe management interface provides one mechanism to limit power consumption of thefree side device on the Vact pins.If the Power Override bit (See SFF-8636, page 00h, byte 93, bit 0) is low, the freesidedevice power is in the low power mode and power consumption shall be 1.5W orless. In addition, the free-side device shall be in low power mode if the Power Setbit (See SFF-8646, page 00h, byte 93, bit 1) is high, regardless of the PowerOverride bit state.If the Power Override bit is in the high state and the Power Set bit is low, thefree-side device power consumption may be greater than 1.5W. For this case, theExtended Identifier bits (See SFF-8636, page 00h, byte 129, bits 6-7) indicate themaximum consumption for the specific free-side device.If both Extended Identifier bits (See SFF-8636, Page 00h, byte 129, bits 6-7) are inthe low state, the free side device power consumption shall be 1.5W or less. In thiscase, the free side device shall be fully functional regardless of power mode (lowor high).If the Extended Identifier bits indicate a power consumption greater than 1.5W andthe free side device is in low power mode, the free side device shall reduce powerconsumption to 1.5W or less. The exact method of reducing power consumption is notspecified. However, it is likely that either the Tx or Rx or both will not beoperational in this state.A truth table for the relevant configurations of the Power Override, Power Set andextended identifier bits is shown in table 6.Table 6. Power Consumption Control FunctionalityPower Power Byte 129, Module Power AllowedOverride Set bits 7-60 X X 1.5W Default Power Level1 0 00 High Power (1.5W)1 0 01 High Power (2.0W)1 0 10 High Power (2.5W)1 0 11 High Power (3.5W)1 1 X Low Power (1.5W)Note, the symbol ‘X’ in a column indicates any entry satisfies the condition.The free side device may declare maximum power consumption levels less than 1.5W byusing the using ‘Advanced Low Power Mode’ parameter shown in table TBD. For example,if the fixed side does not support free side devices consuming more than 1W, thisHD Management Interface Page 15

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.1parameter will allow the fixed side to determine if it has adequate power allocatedprior to application of power to the Vact pins.Table 7. Reduced Power Consumption LevelsAdvanced Low Power Mode Declared Maximum Power Consumption(Byte 110, bits 7-6)00 Advanced Low Power Mode Not supported01 1W10 0.75W11 0.5WNote, free-side power levels specified for 3.3V level on both Vact inputs.Additional power savings can be obtained by reducing the Vact input voltage level.The minimum operating voltage is specified by bits 4-3 of byte 110.Minimum OperatingVoltageTable 8. Minimum Operating VoltageDeclared Minimum OperatingVoltage00 Not Supported (Default is 3.3V)01 2.5V10 1.8V11 Reserved5.6 Power Supply Filtering NetworkThe following fixed side power supply filtering network is recommended for the Vmanand both Vact pins. Since the two free side connections to Vact may be electricallyisolated a separate network is recommended for each Vact pin.Optional :Vman maybe switchedper portVman22 uF0.1uF1uH22uF0.1uFTo Vman pinof externalMini SAS HD4x ConnectorOptional :Support foractive cablesoptionalOptional :Vact maybe switchedper portVact22uF1uH0.1uF22uF0.1uFTo Vact pins ofexternal MiniSAS HD 4xConnectorHD Management Interface Page 16

Development *** THIS IS NOT A FINAL DRAFT *** SFF-8449 Rev 1.15.7 Squelch5.7.1 RX SquelchThe receiver data output shall be squelched or disabled when the optical inputsignal is equal to or less than the level required to assert LOS. See table TBD foroptical signal level. The output impedance levels shall be maintained while thedifferential voltage swing shall be less than 50 mVpp.In normal operation the default case has Rx Squelch active. Rx Squelch can bedeactivated using Rx Squelch Disable through the 2-wire serial interface. Rx SquelchDisable is an optional function.5.7.2 TX Squelch (optional)If the differential peak-to-peak electrical input signal becomes equal to or lessthan 50 mVpp, the transmitter optical output shall be squelched or disabled and theassociated TxLOS (loss of input) flag set. When squelched, the transmitter OMA shallbe less than or equal to -26 dBm and when disabled the transmitter power shall beless than or equal to -30 dBm.By default, Tx Squelch shall be active. Tx Squelch can be deactivated using TxSquelch Disable through the 2-wire serial interface. Tx Squelch Disable is anoptional function.HD Management Interface Page 17