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Contents 목적 및 배경 DIMM TOPOLOGY 이해• DDR2 DIMM Topology 이해• DDR3 DIMM Topology 이해 CONCEPT• Write Levelling 이해• Tester에서의 Write Levelling 구현 CONCLUSIONS1 / 9

SoC Design Flow from DFT Engineers' angle

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High site count complex mixed-signal device parallel testing soultion

Optimal SoC Test Interface for Wafer and Final Tests

Novel Vertical MEMS Probe Card for High Speed Devices

Contents 목적 및 배경 DIMM TOPOLOGY 이해• DDR2 DIMM Topology 이해• DDR3 DIMM Topology 이해 CONCEPT• Write Levelling 이해• Tester에서의 Write Levelling 구현 CONCLUSIONS1 / 9

목적 및 배경목 적기존 DDR2 Module Electrical Test 장비를 활용하여DDR3 Module Electrical Test를 가능하게 한다.배 경DDR3 Module의 Topology가 DDR2 Module의 Topology와 달라기존 장비로는 DDR3 Module을 Test 할 수 없다.2 / 9

Page 1: DDR2 Tester 성능 Upgrade를 통
Page 5 and 6: DDR2 DIMM의 Topology 구성DDR2 Mo
Page 7 and 8: Write Leveling FunctionCTLRDifferen
Page 9 and 10: Wrtie Levelling 구현DRAM#1DRAM#2D

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