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230JONG-EUN LEE et al : SYSTEM LEVEL ARCHITECTURE EVALUATION AND OPTIMIZATION: AN INDUSTRIAL...Thus we further address how to evaluate and optimize thememory controllers, focusing on our test environment andmethodology. Using our architecture evaluation schemeswe could successfully find the performance bottleneck andprovide appropriate feedback on time to designers andsystem integrators.II. Design FlowFig. 1. Overall design flow from IP’s to chip layout.Fig. 2. Example system architecture.SOC designs. As a result of our system level analysis thememory controller was found to be the single mostimportant component that affects the overall performance.Figure 1 illustrates our overall design flow startingfrom a list of IPs to chip layout. The goal of the designprocess is to determine from the given set of IPs aninterconnect and memory subsystem architecture so as tomeet the performance requirements. Figure 2 illustrates anexample system architecture, where the IPs can access thememory through three AHB bus layers, one AMBA3 AXI[4] interconnect, and the memory controllers. In the figurethe interconnect architecture parameters may include thenumber of AHB layers, the layer organization (e.g., whichIP is located in which layer), and the bus arbitrationalgorithm, while it is also conceivable to explore differentbus protocols and different memory controller algorithms.We assume that IPs can be provided either as TLM modelsor as RTL netlists. In the case of the TLM models, IPdesign is still under way, so there may be more room forarchitectural exploration, whereas in the latter case theremay be a more restricted design space to explore. Ourmethodology can be applied in both cases.Table. 1. Worst case scenario example (MPEG4 decoding).

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, DECEMBER, 2005 231III. System Level ArchitectureEvaluationTable. 2. Performance requirement example.1. Worst Case ScenarioOur system level architecture evaluation process startswith scenario definition, where a scenario can be consideredas a refined form of performance requirements. Theperformance requirements do not have to be detailed butshould show what will be the final performance perceivedby the end user. An example of the performancerequirements is listed in Table 2. From the performancerequirements, we derive the worst case scenarios.A scenario is a set of actions played by participating IPswith (if any) timing restrictions specified. For example, theperformance requirement for MPEG4 decoding states thatseveral IPs including MPEG Codec, Deblock Filter, PostProcessor, and LCD Controller should perform theiroperations at certain rates. The MPEG4 decoding scenariocan be described as in Table 1. Note that the actiondescription part represents the test condition that needs tobe modeled, and the timing restriction part represents thetargets that should be matched by the simulation results.The action description may have “modes” (orparameters) in which each IP performs its task. Forinstance, the MPEG Codec is in the “decode” mode in theMPEG4 decoding scenario. Some parameters are free tochange, however, either by user at run time or by designerat design time. These optional parameters produce a set ofscenarios, all of which may be interesting. Preparingmodels and running simulations for all of them is a certainwaste of effort, and we prune most of the scenarios andselect only the most interesting ones, those that demandthe greatest performance to the system architecture (i.e.,the bus and memory controller subsystem). Those arecalled worst case scenarios.2. TLM Modeling and SimulationEvaluating the system level architecture fast andaccurately is key to finding optimal interconnectarchitectures of an SOC. For the most accurate analysisresults, the dynamic effects between various IPs, busses,and memory controllers should be taken into account. Dueto its prohibitively large computational resourcerequirement, RTL simulation is often not feasible for thiskind of system level analysis. Also hardware emulation istoo costly an approach at the early stages of the designprocess, since the system architecture is very likely tochange as a result of the architecture evaluation andexploration.We use the Transaction Level Modeling (TLM)technique to capture the behavior of IPs, busses, andmemory controllers, and to evaluate and explore differentsystem level architectures. For the most credible results,we model the components at the Bus Cycle Accurate(BCA) level of abstraction. This ensures that dynamiceffects such as bus arbitration and memory controllerscheduling are accurately reflected in our TLM simulationresults. One big drawback of the bus cycle accuratemodeling at the system level is the modeling effort. Tominimize the modeling effort we model only the IPs thatappear in the worst case scenarios. Modern MAPs consistof at least a few dozens of IPs to integrate at the top level.Modeling only a subset of the IPs is the most obvious wayto reduce the modeling effort. Further, each IP has anumber of modes and parameters. It is arguable thatmodeling and testing an IP for all its modes andparameters may require more effort than modelingmultiple IPs for a subset of modes and parameters. Thuswe model only those features that will be used in the worstcase scenarios, which should reduce the modeling effort.Figure 3 illustrates our system architecture evaluationflow using TLM. Using the worst case scenarios we canreduce the number of IPs and of simulation runs tominimum. The major effort is then put into (if IPs areprovided in RTL only) developing TLM models andrunning simulations making sure all the action description

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, DECEMBER, 2005 233Fig. 4. Memory controller refinement flow.Fig. 5. Memory controller test environment.found that the memory controller does not perform writebank interleaving even when it is significantlyadvantageous. Figure 6 shows the simulation resultshighlighting the ineffective behavior of the memorycontroller. The waveform shown is for a transaction withthe burst size being four. In this particular case the fourtransfers access four different banks of the memory andthere is no prior transaction that is still in execution. Thenthe ideal memory controller should issue row activationcommands for each of the four memory banks and try toexpedite the overall transaction, hiding the row activationlatency. However as the figure suggests, the initial memorycontroller wasn’t doing this obvious optimization. Afteridentifying the cause of the problem we could enhance thewrite performance when write bank interleaving can beperformed. Figure shows the transaction after write bankinterleaving is implemented in the memory controller. Inthis case the write latency is reduced from 71 cycles to 32cycles (corresponding to 45% improvement).2. Write Data FIFO MergingAnother example of improving the memory controllerperformance through our automatic test environment isrelated to the write data FIFO, which resides in thememory controller. To support multiple outstandingtransactions the memory controller has an internal writedata FIFO. But if the write data FIFO becomes full, atransaction with more than one write data items wouldenter the FIFO as if it were two separate transactions. Wewere able to identify this erroneous behavior using our testenvironment, as depicted in Figure 8. After removing thisinefficiency by merging the (incorrectly separated) twotransactions, the memory controller could perform as itshould (reducing the latency from 17 to 13 cycles, in theexample).Fig. 6. Before write bank interleaving.Fig. 7. After write bank interleaving.

234JONG-EUN LEE et al : SYSTEM LEVEL ARCHITECTURE EVALUATION AND OPTIMIZATION: AN INDUSTRIAL...VI. AcknowledgmentsThe authors would like to thank Dr. Byeong Min inCAE Center, Samsung and Harry Cho in ProcessorArchitecture Lab., Samsung for their useful comments anddiscussion.Fig. 8. Erroneous behavior when write data FIFO is full.ReferencesV. ConclusionsIn this paper we presented a case study designing acomplex SOC for modern mobile application processors,which typically have stringent requirements for cost,power, and performance. To address the challenge ofanalyzing and exploring different interconnectarchitectures in a timely manner with the highest accuracy,we used the TLM technique at the BCA modeling level.To reduce the high modeling effort of BCA modeling, weexploited the concept of worst case scenarios for modelingsystem level architectures. Our architecture analysistechnique provides reliable system level performanceestimates taking into account dynamic effects between IPsand busses, and also enables system level architectureexploration. We also addressed how to evaluate andoptimize the memory controller, which was found to be asystem level component with critical importance for MAPperformance. We demonstrated the efficacy of our designevaluation technique using a real industrial design.Applying our architecture evaluation technique we couldeasily find performance bottlenecks and provideappropriate feedback to designers and system integrators.Our future work includes investigating and quantifyinghow much our technique can save the modeling effort forsystem level architecture evaluation. Being based onscenarios and ultimately on performance requirements, oursystem level evaluation technique is susceptive to therequirement change. An incremental method thereforewould be desirable to accommodate the performancerequirement change.[1] “Mobile application processor for 3G phones,” 3GNewsletter, Sept. 2004, online document available athttp://www.3g.co.uk/PR/Sept2004/8344.htm, lastaccessed July 20, 2005.[2] “New multimedia application processor chips for2.5/3G mobile phones,” 3G Newsletter, Feb. 2003,online document available at http://www.3g.co.uk/PR/Feb2003/4832.htm, last accessed July 20, 2005.[3] T. Grotker et al., System Design with SystemC, Kluwer,2002.[4] “AMBA AXI Protocol Specification,” ARM Limited,2003.[5] “PrimeCell AXI Configurable Interconnect,” ARMLimited, Ref: ARM DDI 0354A, Dec 2004.[6] “ARM PrimeCell Dynamic Memory ControllerTechnical Reference Manual,” ARM Limited, Ref:ARM DDI 0331A, June 2004.[7] Specman eVC, further information available onhttp://www.cadence.com/verisity.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, DECEMBER, 2005 235Jong-Eun Lee He received a B.S. and anM.S. in electrical engineering and a Ph.D.in electrical engineering and computerscience all from Seoul NationalUniversity. He was a visiting scholar inCenter for Embedded Computer Systems,University of California, Irvine during January 2002 throughMarch 2003. He is currently with Design Technology Group ofSamsung SoC R&D Center in Korea. His research interestsinclude automation of embedded system design, reconfigurableprocessor architecture, and SoC on-chip interconnect.Kyu-Myung Choi He received B.S. andM.S. degrees from Hanyang University,Seoul, Korea, in 1983 and 1985,respectively and Ph.D degree in electricalengineering from the University ofPittsburgh, USA, in 1995. His Ph.Dresearch focused on the development of algorithms for CADtools on system-level design automation. Since 1985, he is withSamsung Electronics as an engineer of CAE(Computer AidedEngineering) team. He studied his Ph.D course as a Samsungscholarship. Now he is a Vice President of CAE center,System-LSI Division, Samsung Electronics.Woo-Cheol Kwon He is a researcher inCAE center, Semiconductor Division,Samsung Electronics Co., Ltd in Korea.His research interests include system-leveldesign, on-chip interconnects andalgorithm design & analysis. He receivedthe B.S. and M.S. degrees in computer science from KoreaAdvanced Institute of Science and Technology.Tae-Hun Kim He is a researcher in CAEcenter, Semiconductor Division, SamsungElectronics Co., Ltd in Korea. His researchinterests include high-performancearchitecture system and high-bandwidthmemory controller design. He received theB.S. degrees in electronic engineering from Inha university.Eui-Young Chung He received the PhDdegree in electrical engineering fromStanford University in 2002. He is aassociate professor of electrical andelectronic engineering at Yonsei University,Seoul, Korea. From 1990 to 2005, he was aprincipal engineer at SoC R&D center, Samsung Electronics,Kiheung, Korea. Dr. Chung’s research interests are systemarchitecture and VLSI design including all aspects of computeraided design with the special emphasis on low power applicationsand in the design of mobile systems.Jeong-Taek Kong He received the B.S.degree in electronics engineering fromHanyang University, Korea, in 1981, theM.S. degree in electronics engineeringfrom Yonsei University, Korea, in 1983,and the Ph.D. degree in electricalengineering from Duke University, Durham, NC, in 1994.From 1983 to 1990, he was with Samsung Electronics Co.,Ltd., as a VLSI CAD manager. From 1990 to 1994, he was atDuke University granted by a Fellowship from SamsungElectronics Co., Ltd. Currently, he is with SemiconductorBusiness, Samsung Electronics Co., as VP of CAE Team. Hehas authored and coauthored more than 110 technical papers ininternational journals and conferences and coauthored a booktitled Digital Timing Macromodeling for VLSI DesignVerification (Norwell, MA: Kluwer, 1995). His researchinterests focus on various VLSI CAD tools and designtechnologies.He has served on the program committees of IEEEInternational Workshop on Statistical Metrology, InternationalConference on VLSI and CAD, International Symposium onQuality of Electronic Design, International Conference onSimulation of Semiconductor Processes and Devices,International Workshop on Behavioral Modeling andSimulation, International Symposium on Low PowerElectronics and Design, International SOC Design Conference,and International Electron Devices Meeting. He is a Memberof Nanoelectronics and Giga-Scale Systems (NaGS) TechnicalCommittee and serves as a Distinguished Lecturer for the IEEECircuits and Systems Society. He was an Associate Editor ofIEEE Transactions on Circuits and Systems-II and IEEE

236JONG-EUN LEE et al : SYSTEM LEVEL ARCHITECTURE EVALUATION AND OPTIMIZATION: AN INDUSTRIAL...Transactions on Very Large Scale Integrated (VLSI) Systemsand was nominated as a member of IMEC Scientific AdvisoryBoard in Belgium in 2004.Soo-Kwan Eo He has been senior vicepresident of Samsung Electronics’ SoCR&D Center focusing on the ESL Designsince late 2002. He currently directs the teamthat deals in SoC on-chip communicationsfabrications including NoC and pre-siliconSoC solution development methodology. His team developed theSamsung’s Virtual Platform, called ViP, low power architecturedesign technology, HW/SW co-design technology, and SamsungSoC bus architecture. He played a key role to deploy these ESLdesign technologies within companies. Mr. Eo received MS inECE from the University of Arizona Tucson, Arizona in 1986 andhad worked in various companies including Cadence, Synopsys,Intel, VIA Technologies in San Jose, California for 16 years beforehe joined the Samsung.Dave Gwilt He is the engineering managerfor the Fabric IP Business Unit of ARM inCambridge. His industrial experienceincludes development of the ARM920T andARM1136JS processors, and architecture ofthe PL340 family of SDRAM controllersand PL330 family of DMA controllers. His technology interestsinclude transaction-level modeling of IP. He received a Mastersdegree in engineering from Cambridge University.