lecture 13 14 15 class room slides - BITS Pilani

lecture 13 14 15 class room slides - BITS Pilani

lecture 13 14 15 class room slides - BITS Pilani

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HARDWARE SOFTWARECO-DESIGN<strong>BITS</strong> <strong>Pilani</strong>Dubai CampusDr Jagadish Nayak

Specification Languages<strong>BITS</strong> <strong>Pilani</strong>Dubai Campus

VHDLCharacteristics supported☺Behavioral hierarchy : single level of processes☺Structural hierarchy : nested blocks and componentinstantiations☺Concurrency : task-level (process), statement-level (signalassignment)☺Programming constructs☺Communication : shared-memory using global signals☺Synchronization : wait on and wait until statements☺Timing : wait for statement, after clause in assignments<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

VHDL (Structural Hierarchy)entity Counter_E isport(clk : in bit ; cnt : out integer);End counter_E;architecture Counter_struct of Counter_E iscomponent Reg_Eport(d : in integer; clk: bit; o: out integer; clear : in bit);end component;component Add_Eport(a,b : in integer; o: out integer)end component<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

VHDL (Structural Hierarchy)component Cmp_Eport(i0,i1 : in integer; o : out bit)end componentsignal one : integer :=1;signal nine : integer :=9;signal cnt_in,cnt_out, add_out : integer;signal clear bit;<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

VHDL (Structural Hierarchy)BeginConreg : Reg_Eport map(cnt_in, clk, cnt_out, clear);Adder: Add_Eport map(cnt_out, one, add_out)Comparator : cmp_Eport map(nine, cnt_in, clear);cnt

VHDL BehavioralEntity Counter_E isport(clk: in bit ; cnt : out register)end Counter_E;architecture counter_beh of Counter_E isbeginprocessvariable convar: integer :=0;begincnt

VHDL Behavioralelseconvar:=convar+1;end ifend processend Counter_beh;<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

VHDL (Dataflow)Entity Counter_E isport(clk: in bit ; cnt : out register)end Counter_E;architecture Counter_dflow of Counter_E issignal consig: integer:=0;beginblock((clk=‘1’) and not(clk’stable))beginconsig

VHDL☺How do we get communication between the two processes– By adopting shared memory model, which uses signals thatcan be assigned by any process and are visible to otherprocesses.☺Synchronization (Consider a process P)P: process(start,x)begin………..end process-process P will be suspended until an event occurs on either of the signalstart or x, it enables the designer to synchronize the execution of theprocess P with other processes that incarporate the start and x signals.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

VHDL☺Wait statement also provides synchronization– This statement will suspend the process until it detects either theoccurrence an event on one of the specified signal, or the presenceof a specified condition.Ex: wait on x,y until (start =‘1’);– The process will resume only when an event occurs on signals x or yor when start =1☺Specification of timing:a

VHDL☺VHDL lacks in some areas– No exceptions (except gaurded concurrent signalassignments)– It does not support state transition– concurrency in any level of hierarchy is notsupported.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

VerilogSupports structural hierarchy:System is specified as hierarchy of interconnected modules.These modules are specified either low level or specifying thebehavior.Supports behavior hierarchy:Any process at any level of hierarchy can be decomposed intoset of procedures, which can be specified by means of C-likesyntax.Data flow behavior can be captured through the use ofcontinuous assignment statements.Communication is implemented through shared memory usingwires connecting the ports on modules, on registers andmemories.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

VerilogSynchronization :Fork-join statement , event control statementsEx: @(negedge) clock#10 q=d;q will be updated with the value d, 10 units after the negativeedge of the clock.Same effect can be achieved using wait statementwait(clock=0);#10 q=d;Q will be updated 10 time units after the negative edge onclock.Exceptions are handled using disable statement.Verilog does not support specification of the state transition.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

Hardware C♫ Synthesis oriented HDL♫Based on the C programing language♫Has additional well-defined semantics and constructs forhardware description.♫Single level concurrent processes communicate with each other, which can be enclosed within hierarchy of blocks (Structuralhierarchy)♫Task level concurrency can be specified by writing algorithmsas set of sequential operations. (Functions)♫Statement level concurrency : parallel compound statement.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

Hardware CCommunication is established either by shared memory ormessage passing models.process Main(n_p, r_p)out port n_p{write n_p=n;…….result=read(r_p)}N_pR_pN_pR_pprocess Factorial(n_p,r_p)in port n_pout port r_p;{n=read(n_p)/*compute factorial*/…………………………..Write r_p=result}Port passing<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

Hardware Cprocess Main(Ch1,Ch2)out channel ch1;In channel ch2;{send(Ch1,N);…….received(Ch2,Result);}Ch1Ch2process Factorial(Ch1,Ch2)In channel ch1;out channel ch2;{receive(Ch1,N)/*compute factorial*/…………………………..send(ch2,result)}Message passing<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

Hardware CSynchronization:♫Uses Blocking message servicesmsgwait will detects pending messages that are alreadywaiting in the channel, so designer can make process to waituntil an appropriate signal has been received from anotherprocess.♫Various models can be constructed using process,procedures and functions. This can be used as libraryTiming constraints can be specified by using tags or labels.♫It does not support specification of dataflow behaviour, statetransition or exceptions.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

CSP♫Communicating Sequential Processes.♫Proposed by CAR Hoare, in1978, to overcome the limitations ofthe traditional programming languages to execute on the multiprocessorsystem.♫Program is specified as a set of concurrent processes, which isa simplified form of communication and synchronizationbetween these processes.♫This can specify hardware systems.♫Parallel commands can be sub divided concurrent subprocesses at any level of hierarchy thus providing behavioralhierarchy.♫These parallel command can execute concurrently completedonly when all the processes have been terminated.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

CSPControl constructs:if (a>b) max=a;else max=b;Same can be alternatively represented in CSP command[a>b → max:=a[]a ≤ b →max:=b]♫There are no global variables , so communicationbetween concurrent processes can be achieved only bymeans of message passing with explicit input and outputcommand specified.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

CSP♫Communication between two concurrent processes occurswhen the following criteria is met.1. The output command of the first process specifies thesecond process as the destination of the data to be sent2. The input command of the second process specifies the firstprocess as the source of the data received.3. The type of the target (into which the data is received) in theinput command matches the expression of the inputcommand.♫Limitations are no construct for specifying structure, statetransitions, timing, dataflow behavior or exception handling.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

Statecharts♫This language specifies reactive systems, which are eventdriven, control dominated systems, such as those used in theavionics and communication systems.♫Represents FSM (hierarchy, concurrency and communication)♫The basic object in Statecharts is a state, and transitionbetween states are determined by a combination of eventsand conditions.♫Supports behavioral hierarchy, there are two ways ofdecomposition.OR (sequential)and AND (Concurrent)<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

Statecharts<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

StatechartsSequentialdecomposition<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

StatechartsConcurrentdecomposition<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

Statecharts♫Exponential blowup of states may not occur ascompared to conventional FSMs♫Transition arc and states are zero delay computations♫Actions can be continuous or depend on the entry or exitof the state♫Allows state transitions across multiple levels in thehierarchy.♫There is a special timeout transition arc that defines thatdefines maximum and minimum amounts of time thesystem can spend in the desired state.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

Statecharts♫Communication is through broadcast mechanismevent generation, variable update or transitions in any portion of thestate chart will be immediately sensed by rest of the state chart.♫Synchronization can be achieved by initialization, commonevent common data, and status detection.♫Non deterministic behaviorwhenever there are two arcs transitioned simultaneously , one ofthose arcs chosen non-deterministically♫Disadvantage is that, it does not support the programmingconstruct♫Has no construct for specifying structure, behavioral completionand dataflow behavior.<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

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