Verifying a Synthesized Implementation of IEEE-754 Floating-Point ...

Verification of IEEE-754 Floating-Point Exponential Function 7Otherwise, calculate R 1 byR 2 is obtained byR 1 := (X − N ∗ L 1 ).R 2 := −N ∗ L 2 .• To complete this step, we decompose N into M and J ,thus:M := N 132J := N 2 .Step 3. Approximate exp(R 1 + R 2 ) − 1 by a polynomialp(R 1 + R 2 ), wherep(t) = t + a 1 t 2 + a 2 t 3 +···+a n t n+1 .The polynomial is computed by a standard recurrence:R := R 1 + R 2Q := R ∗ R ∗ (A 1 + R ∗ (A 2 + R ∗ (...+ R ∗ A n )...))P := R 1 + (R 2 + Q)The coefficients are obtained from a Remez algorithmimplemented by Tang [8]. Our method for bounding theapproximation error in this polynomial [7] ispost-hoc, andworks equally well if the polynomial is derived in other ways,e.g. via Chebyshev expansions [39] or more delicate means [40].Step 4. Reconstruct exp(X) viaexp(X) = 2 M (2 j/32 + 2 j/32 p(R 1 + R 2 )).Each of the values 2 j/32 ,j = 0, 1,...,31, is calculatedbeforehand and represented by two working-precision numbersS_lead(J ) and S_trail(J). The sum approximates 2 j/32 toroughly double the working precision. Thus, we may consider2 j/32 = S_lead(J )+S_trail(J)for all practical purposes. TheReconstruction is as follows:S := S − lead(J ) + S_trail(J)exp := 2 M ∗ (S_lead(J ) + (S_trail(J) + S ∗ P))5.2. Formal implementation of the exponential functionThe implementation of the algorithm in RTL was done by Buiet al. [9] using two different hardware description languages,namely, Verilog and VHDL.A block diagram of the whole system is shown in Fig. 2.In this diagram, we use the same labels as in the algorithmspecification.The part constructed using VHDL made use of the sequentialmode in contrast to the Verilog implementation that usedcombinational logic. Both essentially implement the samealgorithm outlined in the previous section.FIGURE 2. Floating-point exponential function main block diagram.The Computer Journal, 2009