Sameh Rehan's CV

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• Northern Telecom Electronics (NTE) 1.2μm CMOS process.• Gennum 3.0μm BiFET, LSI, and DLI processes.Employment HistoryI. Academic ExperienceSeptember 2003 to present Assistant Prof., C&EE Dept., MU, Mansoura, Egypt• Instructor for the following term courses (on-line courses are @ http://osp.mans.edu.eg/rehan ):1. Artificial Neural Networks: for senior students of the C&EE Dept., Fall 2003.2. Assembly Language (MIPS): For senior students of the C&EE Dept., Winter 2004, for thirdyear students of the C&EE Dept., Winter 2005, and for third year students of the ComputerSciences Dept., Faculty of Information and Computers, MU, Winter 2005.3. Solid State Electronics: for first year students of the C&EE Dept., Fall 2003/04/05/06.• Instructor for the CAD (03/04 & 04/05) and Nano-electronics (05/06 & 06/07) full-year M.Sc. graduatecourses at MU.• Co-supervises graduate students on their research work in the areas of:1. Nano-electronics:• Eng. Lobna (Design of an 8-bit ADC using Single Electron Transistor (SET))• Eng. Iman (Design of a full-adder using Single Electron Transistor (SET)),2. DSP:• Eng. Hossam (Application of registration techniques to biomedical images), and3. e-Learning:• Eng. Mahmoud (Animations for the analysis and design of electronic devices)• Eng. Reham (Animations for the analysis and design of analog electronics)• Eng. M. Samy (Animations for the analysis and design of digital electronics)• Supervises students working on their final full-year graduation projects (6 students in 2004/05 & 10students in both 05/06 and 06/07) in the area of e-Learning (Development of an Electronic Virtual lab).September 1997 to Aug. 1998 Assistant Prof., C&EE Dept., MU, Mansoura, Egypt• Instructor for the following full-year courses:1. Integrated Circuits: for senior students of the Electronics Engineering Dept.2. Acoustics: for senior students of the Architecture Civil Engineering Dept.3. Electronics: for junior students of the Electrical Engineering Dept.• Supervised students working on their final year graduation projects in the general areas of ANNs &VLSI.September 1989 to May 1995 Ph.D. Candidate, Research Associate & TeachingAssistant, Department of Electrical & Computer Engineering (E&CE), University ofWaterloo, Waterloo, Ontario, Canada• Researched and gained experience in the following areas: VLSI implementation, ANNs, CMOS ICdesign, CAD tools, DSP, computational linguistics, expert systems, and character recognition systems.• Designed, simulated, laid out, and tested three CMOS chips:1. The first chip had the basic ANN building block circuits,2. The second chip had a mixed-mode ANN circuit that solves the XOR problem, and3. The third chip was a two-character ANN recognition system that encodes the Back-Propagation (BP) learning algorithm of the multi-layer perceptron (MLP) model simulator.The chip was implemented using the NTE 1.2μm CMOS process.• Published several research papers, and attended research conferences as well as technical workshops.• Conducted tutorials and lectures for undergraduate students in the areas of: Switching and DigitalCircuits (E&CE 438), and Electrical Engineering Circuits (E&CE 123).• Demonstrated experiments to undergraduate students; supervised them during laboratory sessions andmarked their reports, projects, and exams.Jan. 1988 to Aug. 1989 Ass. Lecturer, C&EE Department, MU, Mansoura, EgyptCV of Dr. Sameh Rehan 8/2/2007 page 4 of 8
• Conducted tutorials and lectures for undergraduate students in the areas of: Digital Circuits, SwitchedCapacitor Circuits, Active Filters, Analog ICs, Electronics, and Computer Applications.• Demonstrated experiments to undergraduate students; supervised them during laboratory sessions andmarked their reports, projects, and exams.September 1984 to December 1987 M.Sc. Candidate, Research Associate & TeachingAssistant, C&EE Department, MU, Mansoura, Egypt• Researched and gained experience in the following areas: Switched-Resistor (SR) Circuits, ActiveFilters, Digital Circuit Design, PCB design, and CAD tools.• Designed, implemented, and tested sampled-data active filters & oscillators and an accurate (6 bitresolution) digital clock with varying duty-cycle using PCBs.• Supervised undergraduate students during Electronics laboratory sessions and graduation projects.II. Industrial ExperienceSeptember 2003 to December 2004 Physical IC Design Consultant, Wireless andAudio R&D Division, Gennum Corporation, Burlington, Ontario, Canada• Conducted the physical design activities (floor-planning, P&R, layout, DRC, LVS, and tape out) of twoDSP HIP products using UMC 0.18μm CMOS process. This work was done (using Gennum’s designtools) remotely from Egypt through high-speed Internet connection.December 2000 to August 2003 Physical IC Design Team Leader, HearingInstrument Products (HIP) R&D Division, Gennum Corporation, Burlington,Ontario, Canada• Managed the activities of the physical design team of the HIP R&D division to achieve the tape out of:1. 7 chips for 5 hearing aid systems using CSM 0.25μm / UMC 0.18μm CMOS processes and2. 6 test chips for future products using UMC 0.18μm CMOS process.• Supervised the physical design activities (floor-planning, P&R, layout, DRC, and LVS) and approved thesign-off of all DSP HIP products and test chips using CSM and UMC CMOS processes.• Supervised and trained new hires to do physical design using PDP, SE, Virtuoso, and Calibre CAD tools.• Supervised & approved of product physical design documentation for 2 hearing aid chips and 5 testchips.December 1999 to November 2000 IC Design Engineer, Digital Signal Processing(DSP) Group, Hearing Instrument Products (HIP) R&D Division, GennumCorporation, Burlington, Ontario, Canada• Designed, simulated, generated test-benches, and verified several digital modules including: the clockgenerator module, the FIFO RAM module, the system word module, and the debounce circuits for the firstDSP HIP product at Gennum Corporation.• Conducted the physical design activities (floor-planning, P&R, layout, DRC, and LVS) of the DSP HIPchip using CSM 0.25μm CMOS process.• Prepared product physical design documentation for the DSP HIP hearing aid chip.September 1998 to November 1999 IC Design Engineer, HIP Analog IC DesignGroup, R&D Division, Gennum Corporation, Burlington, Ontario, Canada• Designed, simulated, laid out, and verified one full-custom BiFET AGCO class B analog signal processorfor hearing aid applications.• Laid out and verified one full-custom BiFET analog signal processor chip for one of Gennum’s biggestcustomers (Phonak of Switzerland) that is now being used for hearing aid applications.• Prepared specs, test plan, and product design documentation for a class B hearing aid amplifier product.March 1994 to August 1998 Product Development Engineer, HIP Analog IC DesignGroup, R&D Division, Gennum Corporation, Burlington, Ontario, Canada• Designed, simulated, laid out, and verified several full-custom BiFET amplifier chips for hearing aidapplications (including class D, class H, and class B amplifiers).• Resolved a low-yield problem in one full-custom class B BiFET amplifier chip.CV of Dr. Sameh Rehan 8/2/2007 page 5 of 8
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