FPGA Glitch Power Analysis and Reduction

Fig. 4.Experimental flow.V. EXPERIMENTAL STUDYWe perform our glitch reduction algorithm on 20 MCNCbenchmark circuits. The experimental methodology was chosento include commercial CAD tools wherever possible,to evaluate the efficacy of the algorithm on real-world FP-GAs. The flow is shown in Figure 4. We perform a fullcompilation using Quartus II 10.1 (synthesis, placement androuting) targeting the Altera Stratix III 65nm FPGA family [1].This is followed by a timing simulation using ModelSimSE 6.3e. For each circuit, 5000 random input vectors areapplied. We use a set of custom scripts to transform thesimulation netlist generated by Quartus into BLIF format,which can then be read into ABC, where the glitch reductionis performed. Combinational equivalence checking (commandcec in ABC [13]) is used after the glitch reduction step toensure that the functionality of the circuit remains the same.The output from ABC is used to modify the configurationbits in the simulation netlist, thus ensuring that the placementand routing remain identical. Three passes of the optimizationloop are performed. Experiments show that very few changes,if any, are made after this point. The power measurements areperformed using Quartus PowerPlay.A. ResultsThe leftmost bars in Figure 5(a) (vs. baseline) represent thepercentage reduction in total core dynamic power after performingthe glitch reduction algorithm. The average reductionis 4.0%, with a peak of 12.5%. Figure 5(b) shows the correspondingreduction in glitch power. The average reduction is13.7%, with a peak of 84.0%. Naturally, the amount of powerreduction possible is based on the amount of glitching presentand the number of don’t-cares available. While the overallaverage power reductions are relatively modest, we believethey will interest FPGA vendors and power-sensitive FPGAcustomers, as they come at no cost to performance or area.For some circuits, over 10% power reduction can be achievedessentially for “free”.It is also interesting to look at the optimized power vs. theworst case don’t-care settings possible, as illustrated by therightmost bars in Figure 5 (vs. worst-case). In this experiment,we set the don’t-cares to the opposite of how they wouldnormally be set by our optimization algorithm, to examinethe potential worst-case glitch power arising from don’t-cares.Here, we see an average total dynamic power savings of 9.8%(a)(b)Fig. 5. (a) Dynamic power reduction vs. baseline (default) don’t-care settingsand worst-case settings. (b) Glitch power reduction vs. baseline (default)don’t-care settings and worst-case settings.and a peak savings of 30.8% (Figure 5(a)). These results showthat don’t-care settings can potentially have a large impact onpower if set to sub-optimal values.The varied results in Figure 5 can be correlated with theglitch power and don’t-care data in Tables II and III. Forinstance, des had a high glitch power in Table II, yet we did notobserve a significant power reduction for this circuit. However,in Table III, we see that it had only 0.8% of LUT inputsas don’t-cares, thus reducing the number of opportunities foroptimization. On the other hand, pdc had a high amount ofglitching as well as ample don’t-cares, thus allowing it to begreatly improved by the algorithm – 12.5% dynamic powerreduction.The relationship between don’t-cares, power and fanoutpresents a challenge to the glitch reduction algorithm. Fanoutis closely related to interconnect capacitance, and interconnectcan represent 60% of total FPGA dynamic power, on average[14]. Figure 6(a) shows logic signal power consumptionversus fanout, averaged across all signals in all circuits.Observe that, as expected, average signal power increases withfanout, due to the increase in capacitance. We also examined,for each signal, the fraction of minterms in its driving LUT thatwere don’t-cares, and averaged this across all signals of a givenfanout in all circuits. The results are shown in Figure 6(b).While the results are “noisy” for high fanout (due to a small